1 /* 2 * sh_eth.c - Driver for Renesas ethernet controler. 3 * 4 * Copyright (C) 2008, 2011 Renesas Solutions Corp. 5 * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu 6 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <config.h> 12 #include <common.h> 13 #include <malloc.h> 14 #include <net.h> 15 #include <netdev.h> 16 #include <miiphy.h> 17 #include <asm/errno.h> 18 #include <asm/io.h> 19 20 #include "sh_eth.h" 21 22 #ifndef CONFIG_SH_ETHER_USE_PORT 23 # error "Please define CONFIG_SH_ETHER_USE_PORT" 24 #endif 25 #ifndef CONFIG_SH_ETHER_PHY_ADDR 26 # error "Please define CONFIG_SH_ETHER_PHY_ADDR" 27 #endif 28 29 #ifdef CONFIG_SH_ETHER_CACHE_WRITEBACK 30 #define flush_cache_wback(addr, len) \ 31 flush_dcache_range((u32)addr, (u32)(addr + len - 1)) 32 #else 33 #define flush_cache_wback(...) 34 #endif 35 36 #define TIMEOUT_CNT 1000 37 38 int sh_eth_send(struct eth_device *dev, void *packet, int len) 39 { 40 struct sh_eth_dev *eth = dev->priv; 41 int port = eth->port, ret = 0, timeout; 42 struct sh_eth_info *port_info = ð->port_info[port]; 43 44 if (!packet || len > 0xffff) { 45 printf(SHETHER_NAME ": %s: Invalid argument\n", __func__); 46 ret = -EINVAL; 47 goto err; 48 } 49 50 /* packet must be a 4 byte boundary */ 51 if ((int)packet & 3) { 52 printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n", __func__); 53 ret = -EFAULT; 54 goto err; 55 } 56 57 /* Update tx descriptor */ 58 flush_cache_wback(packet, len); 59 port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet); 60 port_info->tx_desc_cur->td1 = len << 16; 61 /* Must preserve the end of descriptor list indication */ 62 if (port_info->tx_desc_cur->td0 & TD_TDLE) 63 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE; 64 else 65 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP; 66 67 /* Restart the transmitter if disabled */ 68 if (!(sh_eth_read(eth, EDTRR) & EDTRR_TRNS)) 69 sh_eth_write(eth, EDTRR_TRNS, EDTRR); 70 71 /* Wait until packet is transmitted */ 72 timeout = TIMEOUT_CNT; 73 while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--) 74 udelay(100); 75 76 if (timeout < 0) { 77 printf(SHETHER_NAME ": transmit timeout\n"); 78 ret = -ETIMEDOUT; 79 goto err; 80 } 81 82 port_info->tx_desc_cur++; 83 if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC) 84 port_info->tx_desc_cur = port_info->tx_desc_base; 85 86 err: 87 return ret; 88 } 89 90 int sh_eth_recv(struct eth_device *dev) 91 { 92 struct sh_eth_dev *eth = dev->priv; 93 int port = eth->port, len = 0; 94 struct sh_eth_info *port_info = ð->port_info[port]; 95 uchar *packet; 96 97 /* Check if the rx descriptor is ready */ 98 if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) { 99 /* Check for errors */ 100 if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) { 101 len = port_info->rx_desc_cur->rd1 & 0xffff; 102 packet = (uchar *) 103 ADDR_TO_P2(port_info->rx_desc_cur->rd2); 104 NetReceive(packet, len); 105 } 106 107 /* Make current descriptor available again */ 108 if (port_info->rx_desc_cur->rd0 & RD_RDLE) 109 port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE; 110 else 111 port_info->rx_desc_cur->rd0 = RD_RACT; 112 113 /* Point to the next descriptor */ 114 port_info->rx_desc_cur++; 115 if (port_info->rx_desc_cur >= 116 port_info->rx_desc_base + NUM_RX_DESC) 117 port_info->rx_desc_cur = port_info->rx_desc_base; 118 } 119 120 /* Restart the receiver if disabled */ 121 if (!(sh_eth_read(eth, EDRRR) & EDRRR_R)) 122 sh_eth_write(eth, EDRRR_R, EDRRR); 123 124 return len; 125 } 126 127 static int sh_eth_reset(struct sh_eth_dev *eth) 128 { 129 #if defined(SH_ETH_TYPE_GETHER) 130 int ret = 0, i; 131 132 /* Start e-dmac transmitter and receiver */ 133 sh_eth_write(eth, EDSR_ENALL, EDSR); 134 135 /* Perform a software reset and wait for it to complete */ 136 sh_eth_write(eth, EDMR_SRST, EDMR); 137 for (i = 0; i < TIMEOUT_CNT ; i++) { 138 if (!(sh_eth_read(eth, EDMR) & EDMR_SRST)) 139 break; 140 udelay(1000); 141 } 142 143 if (i == TIMEOUT_CNT) { 144 printf(SHETHER_NAME ": Software reset timeout\n"); 145 ret = -EIO; 146 } 147 148 return ret; 149 #else 150 sh_eth_write(eth, sh_eth_read(eth, EDMR) | EDMR_SRST, EDMR); 151 udelay(3000); 152 sh_eth_write(eth, sh_eth_read(eth, EDMR) & ~EDMR_SRST, EDMR); 153 154 return 0; 155 #endif 156 } 157 158 static int sh_eth_tx_desc_init(struct sh_eth_dev *eth) 159 { 160 int port = eth->port, i, ret = 0; 161 u32 tmp_addr; 162 struct sh_eth_info *port_info = ð->port_info[port]; 163 struct tx_desc_s *cur_tx_desc; 164 165 /* 166 * Allocate tx descriptors. They must be TX_DESC_SIZE bytes aligned 167 */ 168 port_info->tx_desc_malloc = malloc(NUM_TX_DESC * 169 sizeof(struct tx_desc_s) + 170 TX_DESC_SIZE - 1); 171 if (!port_info->tx_desc_malloc) { 172 printf(SHETHER_NAME ": malloc failed\n"); 173 ret = -ENOMEM; 174 goto err; 175 } 176 177 tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) & 178 ~(TX_DESC_SIZE - 1)); 179 flush_cache_wback(tmp_addr, NUM_TX_DESC * sizeof(struct tx_desc_s)); 180 /* Make sure we use a P2 address (non-cacheable) */ 181 port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr); 182 port_info->tx_desc_cur = port_info->tx_desc_base; 183 184 /* Initialize all descriptors */ 185 for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC; 186 cur_tx_desc++, i++) { 187 cur_tx_desc->td0 = 0x00; 188 cur_tx_desc->td1 = 0x00; 189 cur_tx_desc->td2 = 0x00; 190 } 191 192 /* Mark the end of the descriptors */ 193 cur_tx_desc--; 194 cur_tx_desc->td0 |= TD_TDLE; 195 196 /* Point the controller to the tx descriptor list. Must use physical 197 addresses */ 198 sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR); 199 #if defined(SH_ETH_TYPE_GETHER) 200 sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR); 201 sh_eth_write(eth, ADDR_TO_PHY(cur_tx_desc), TDFXR); 202 sh_eth_write(eth, 0x01, TDFFR);/* Last discriptor bit */ 203 #endif 204 205 err: 206 return ret; 207 } 208 209 static int sh_eth_rx_desc_init(struct sh_eth_dev *eth) 210 { 211 int port = eth->port, i , ret = 0; 212 struct sh_eth_info *port_info = ð->port_info[port]; 213 struct rx_desc_s *cur_rx_desc; 214 u32 tmp_addr; 215 u8 *rx_buf; 216 217 /* 218 * Allocate rx descriptors. They must be RX_DESC_SIZE bytes aligned 219 */ 220 port_info->rx_desc_malloc = malloc(NUM_RX_DESC * 221 sizeof(struct rx_desc_s) + 222 RX_DESC_SIZE - 1); 223 if (!port_info->rx_desc_malloc) { 224 printf(SHETHER_NAME ": malloc failed\n"); 225 ret = -ENOMEM; 226 goto err; 227 } 228 229 tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) & 230 ~(RX_DESC_SIZE - 1)); 231 flush_cache_wback(tmp_addr, NUM_RX_DESC * sizeof(struct rx_desc_s)); 232 /* Make sure we use a P2 address (non-cacheable) */ 233 port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr); 234 235 port_info->rx_desc_cur = port_info->rx_desc_base; 236 237 /* 238 * Allocate rx data buffers. They must be 32 bytes aligned and in 239 * P2 area 240 */ 241 port_info->rx_buf_malloc = malloc(NUM_RX_DESC * MAX_BUF_SIZE + 31); 242 if (!port_info->rx_buf_malloc) { 243 printf(SHETHER_NAME ": malloc failed\n"); 244 ret = -ENOMEM; 245 goto err_buf_malloc; 246 } 247 248 tmp_addr = (u32)(((int)port_info->rx_buf_malloc + (32 - 1)) & 249 ~(32 - 1)); 250 port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr); 251 252 /* Initialize all descriptors */ 253 for (cur_rx_desc = port_info->rx_desc_base, 254 rx_buf = port_info->rx_buf_base, i = 0; 255 i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) { 256 cur_rx_desc->rd0 = RD_RACT; 257 cur_rx_desc->rd1 = MAX_BUF_SIZE << 16; 258 cur_rx_desc->rd2 = (u32) ADDR_TO_PHY(rx_buf); 259 } 260 261 /* Mark the end of the descriptors */ 262 cur_rx_desc--; 263 cur_rx_desc->rd0 |= RD_RDLE; 264 265 /* Point the controller to the rx descriptor list */ 266 sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR); 267 #if defined(SH_ETH_TYPE_GETHER) 268 sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR); 269 sh_eth_write(eth, ADDR_TO_PHY(cur_rx_desc), RDFXR); 270 sh_eth_write(eth, RDFFR_RDLF, RDFFR); 271 #endif 272 273 return ret; 274 275 err_buf_malloc: 276 free(port_info->rx_desc_malloc); 277 port_info->rx_desc_malloc = NULL; 278 279 err: 280 return ret; 281 } 282 283 static void sh_eth_tx_desc_free(struct sh_eth_dev *eth) 284 { 285 int port = eth->port; 286 struct sh_eth_info *port_info = ð->port_info[port]; 287 288 if (port_info->tx_desc_malloc) { 289 free(port_info->tx_desc_malloc); 290 port_info->tx_desc_malloc = NULL; 291 } 292 } 293 294 static void sh_eth_rx_desc_free(struct sh_eth_dev *eth) 295 { 296 int port = eth->port; 297 struct sh_eth_info *port_info = ð->port_info[port]; 298 299 if (port_info->rx_desc_malloc) { 300 free(port_info->rx_desc_malloc); 301 port_info->rx_desc_malloc = NULL; 302 } 303 304 if (port_info->rx_buf_malloc) { 305 free(port_info->rx_buf_malloc); 306 port_info->rx_buf_malloc = NULL; 307 } 308 } 309 310 static int sh_eth_desc_init(struct sh_eth_dev *eth) 311 { 312 int ret = 0; 313 314 ret = sh_eth_tx_desc_init(eth); 315 if (ret) 316 goto err_tx_init; 317 318 ret = sh_eth_rx_desc_init(eth); 319 if (ret) 320 goto err_rx_init; 321 322 return ret; 323 err_rx_init: 324 sh_eth_tx_desc_free(eth); 325 326 err_tx_init: 327 return ret; 328 } 329 330 static int sh_eth_phy_config(struct sh_eth_dev *eth) 331 { 332 int port = eth->port, ret = 0; 333 struct sh_eth_info *port_info = ð->port_info[port]; 334 struct eth_device *dev = port_info->dev; 335 struct phy_device *phydev; 336 337 phydev = phy_connect( 338 miiphy_get_dev_by_name(dev->name), 339 port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE); 340 port_info->phydev = phydev; 341 phy_config(phydev); 342 343 return ret; 344 } 345 346 static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) 347 { 348 int port = eth->port, ret = 0; 349 u32 val; 350 struct sh_eth_info *port_info = ð->port_info[port]; 351 struct eth_device *dev = port_info->dev; 352 struct phy_device *phy; 353 354 /* Configure e-dmac registers */ 355 sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) | EDMR_EL, 356 EDMR); 357 sh_eth_write(eth, 0, EESIPR); 358 sh_eth_write(eth, 0, TRSCER); 359 sh_eth_write(eth, 0, TFTR); 360 sh_eth_write(eth, (FIFO_SIZE_T | FIFO_SIZE_R), FDR); 361 sh_eth_write(eth, RMCR_RST, RMCR); 362 #if defined(SH_ETH_TYPE_GETHER) 363 sh_eth_write(eth, 0, RPADIR); 364 #endif 365 sh_eth_write(eth, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR); 366 367 /* Configure e-mac registers */ 368 sh_eth_write(eth, 0, ECSIPR); 369 370 /* Set Mac address */ 371 val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 | 372 dev->enetaddr[2] << 8 | dev->enetaddr[3]; 373 sh_eth_write(eth, val, MAHR); 374 375 val = dev->enetaddr[4] << 8 | dev->enetaddr[5]; 376 sh_eth_write(eth, val, MALR); 377 378 sh_eth_write(eth, RFLR_RFL_MIN, RFLR); 379 #if defined(SH_ETH_TYPE_GETHER) 380 sh_eth_write(eth, 0, PIPR); 381 sh_eth_write(eth, APR_AP, APR); 382 sh_eth_write(eth, MPR_MP, MPR); 383 sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER); 384 #endif 385 386 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740) 387 sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII); 388 #endif 389 /* Configure phy */ 390 ret = sh_eth_phy_config(eth); 391 if (ret) { 392 printf(SHETHER_NAME ": phy config timeout\n"); 393 goto err_phy_cfg; 394 } 395 phy = port_info->phydev; 396 ret = phy_startup(phy); 397 if (ret) { 398 printf(SHETHER_NAME ": phy startup failure\n"); 399 return ret; 400 } 401 402 val = 0; 403 404 /* Set the transfer speed */ 405 if (phy->speed == 100) { 406 printf(SHETHER_NAME ": 100Base/"); 407 #if defined(SH_ETH_TYPE_GETHER) 408 sh_eth_write(eth, GECMR_100B, GECMR); 409 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) 410 sh_eth_write(eth, 1, RTRATE); 411 #elif defined(CONFIG_CPU_SH7724) 412 val = ECMR_RTM; 413 #endif 414 } else if (phy->speed == 10) { 415 printf(SHETHER_NAME ": 10Base/"); 416 #if defined(SH_ETH_TYPE_GETHER) 417 sh_eth_write(eth, GECMR_10B, GECMR); 418 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) 419 sh_eth_write(eth, 0, RTRATE); 420 #endif 421 } 422 #if defined(SH_ETH_TYPE_GETHER) 423 else if (phy->speed == 1000) { 424 printf(SHETHER_NAME ": 1000Base/"); 425 sh_eth_write(eth, GECMR_1000B, GECMR); 426 } 427 #endif 428 429 /* Check if full duplex mode is supported by the phy */ 430 if (phy->duplex) { 431 printf("Full\n"); 432 sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), 433 ECMR); 434 } else { 435 printf("Half\n"); 436 sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR); 437 } 438 439 return ret; 440 441 err_phy_cfg: 442 return ret; 443 } 444 445 static void sh_eth_start(struct sh_eth_dev *eth) 446 { 447 /* 448 * Enable the e-dmac receiver only. The transmitter will be enabled when 449 * we have something to transmit 450 */ 451 sh_eth_write(eth, EDRRR_R, EDRRR); 452 } 453 454 static void sh_eth_stop(struct sh_eth_dev *eth) 455 { 456 sh_eth_write(eth, ~EDRRR_R, EDRRR); 457 } 458 459 int sh_eth_init(struct eth_device *dev, bd_t *bd) 460 { 461 int ret = 0; 462 struct sh_eth_dev *eth = dev->priv; 463 464 ret = sh_eth_reset(eth); 465 if (ret) 466 goto err; 467 468 ret = sh_eth_desc_init(eth); 469 if (ret) 470 goto err; 471 472 ret = sh_eth_config(eth, bd); 473 if (ret) 474 goto err_config; 475 476 sh_eth_start(eth); 477 478 return ret; 479 480 err_config: 481 sh_eth_tx_desc_free(eth); 482 sh_eth_rx_desc_free(eth); 483 484 err: 485 return ret; 486 } 487 488 void sh_eth_halt(struct eth_device *dev) 489 { 490 struct sh_eth_dev *eth = dev->priv; 491 sh_eth_stop(eth); 492 } 493 494 int sh_eth_initialize(bd_t *bd) 495 { 496 int ret = 0; 497 struct sh_eth_dev *eth = NULL; 498 struct eth_device *dev = NULL; 499 500 eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev)); 501 if (!eth) { 502 printf(SHETHER_NAME ": %s: malloc failed\n", __func__); 503 ret = -ENOMEM; 504 goto err; 505 } 506 507 dev = (struct eth_device *)malloc(sizeof(struct eth_device)); 508 if (!dev) { 509 printf(SHETHER_NAME ": %s: malloc failed\n", __func__); 510 ret = -ENOMEM; 511 goto err; 512 } 513 memset(dev, 0, sizeof(struct eth_device)); 514 memset(eth, 0, sizeof(struct sh_eth_dev)); 515 516 eth->port = CONFIG_SH_ETHER_USE_PORT; 517 eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR; 518 519 dev->priv = (void *)eth; 520 dev->iobase = 0; 521 dev->init = sh_eth_init; 522 dev->halt = sh_eth_halt; 523 dev->send = sh_eth_send; 524 dev->recv = sh_eth_recv; 525 eth->port_info[eth->port].dev = dev; 526 527 sprintf(dev->name, SHETHER_NAME); 528 529 /* Register Device to EtherNet subsystem */ 530 eth_register(dev); 531 532 bb_miiphy_buses[0].priv = eth; 533 miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write); 534 535 if (!eth_getenv_enetaddr("ethaddr", dev->enetaddr)) 536 puts("Please set MAC address\n"); 537 538 return ret; 539 540 err: 541 if (dev) 542 free(dev); 543 544 if (eth) 545 free(eth); 546 547 printf(SHETHER_NAME ": Failed\n"); 548 return ret; 549 } 550 551 /******* for bb_miiphy *******/ 552 static int sh_eth_bb_init(struct bb_miiphy_bus *bus) 553 { 554 return 0; 555 } 556 557 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus) 558 { 559 struct sh_eth_dev *eth = bus->priv; 560 561 sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MMD, PIR); 562 563 return 0; 564 } 565 566 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus) 567 { 568 struct sh_eth_dev *eth = bus->priv; 569 570 sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MMD, PIR); 571 572 return 0; 573 } 574 575 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v) 576 { 577 struct sh_eth_dev *eth = bus->priv; 578 579 if (v) 580 sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDO, PIR); 581 else 582 sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDO, PIR); 583 584 return 0; 585 } 586 587 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) 588 { 589 struct sh_eth_dev *eth = bus->priv; 590 591 *v = (sh_eth_read(eth, PIR) & PIR_MDI) >> 3; 592 593 return 0; 594 } 595 596 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v) 597 { 598 struct sh_eth_dev *eth = bus->priv; 599 600 if (v) 601 sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDC, PIR); 602 else 603 sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDC, PIR); 604 605 return 0; 606 } 607 608 static int sh_eth_bb_delay(struct bb_miiphy_bus *bus) 609 { 610 udelay(10); 611 612 return 0; 613 } 614 615 struct bb_miiphy_bus bb_miiphy_buses[] = { 616 { 617 .name = "sh_eth", 618 .init = sh_eth_bb_init, 619 .mdio_active = sh_eth_bb_mdio_active, 620 .mdio_tristate = sh_eth_bb_mdio_tristate, 621 .set_mdio = sh_eth_bb_set_mdio, 622 .get_mdio = sh_eth_bb_get_mdio, 623 .set_mdc = sh_eth_bb_set_mdc, 624 .delay = sh_eth_bb_delay, 625 } 626 }; 627 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses); 628