1 /* 2 * rtl8169.c : U-Boot driver for the RealTek RTL8169 3 * 4 * Masami Komiya (mkomiya@sonare.it) 5 * 6 * Most part is taken from r8169.c of etherboot 7 * 8 */ 9 10 /************************************************************************** 11 * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit 12 * Written 2003 by Timothy Legge <tlegge@rogers.com> 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 * 16 * Portions of this code based on: 17 * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver 18 * for Linux kernel 2.4.x. 19 * 20 * Written 2002 ShuChen <shuchen@realtek.com.tw> 21 * See Linux Driver for full information 22 * 23 * Linux Driver Version 1.27a, 10.02.2002 24 * 25 * Thanks to: 26 * Jean Chen of RealTek Semiconductor Corp. for 27 * providing the evaluation NIC used to develop 28 * this driver. RealTek's support for Etherboot 29 * is appreciated. 30 * 31 * REVISION HISTORY: 32 * ================ 33 * 34 * v1.0 11-26-2003 timlegge Initial port of Linux driver 35 * v1.5 01-17-2004 timlegge Initial driver output cleanup 36 * 37 * Indent Options: indent -kr -i8 38 ***************************************************************************/ 39 /* 40 * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk> 41 * Modified to use le32_to_cpu and cpu_to_le32 properly 42 */ 43 #include <common.h> 44 #include <dm.h> 45 #include <errno.h> 46 #include <malloc.h> 47 #include <memalign.h> 48 #include <net.h> 49 #ifndef CONFIG_DM_ETH 50 #include <netdev.h> 51 #endif 52 #include <asm/io.h> 53 #include <pci.h> 54 55 #undef DEBUG_RTL8169 56 #undef DEBUG_RTL8169_TX 57 #undef DEBUG_RTL8169_RX 58 59 #define drv_version "v1.5" 60 #define drv_date "01-17-2004" 61 62 static unsigned long ioaddr; 63 64 /* Condensed operations for readability. */ 65 #define currticks() get_timer(0) 66 67 /* media options */ 68 #define MAX_UNITS 8 69 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 }; 70 71 /* MAC address length*/ 72 #define MAC_ADDR_LEN 6 73 74 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/ 75 #define MAX_ETH_FRAME_SIZE 1536 76 77 #define TX_FIFO_THRESH 256 /* In bytes */ 78 79 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ 80 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 81 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 82 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ 83 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */ 84 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 85 86 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */ 87 #ifdef CONFIG_SYS_RX_ETH_BUFFER 88 #define NUM_RX_DESC CONFIG_SYS_RX_ETH_BUFFER 89 #else 90 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */ 91 #endif 92 #define RX_BUF_SIZE 1536 /* Rx Buffer size */ 93 #define RX_BUF_LEN 8192 94 95 #define RTL_MIN_IO_SIZE 0x80 96 #define TX_TIMEOUT (6*HZ) 97 98 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */ 99 #define RTL_W8(reg, val8) writeb((val8), ioaddr + (reg)) 100 #define RTL_W16(reg, val16) writew((val16), ioaddr + (reg)) 101 #define RTL_W32(reg, val32) writel((val32), ioaddr + (reg)) 102 #define RTL_R8(reg) readb(ioaddr + (reg)) 103 #define RTL_R16(reg) readw(ioaddr + (reg)) 104 #define RTL_R32(reg) readl(ioaddr + (reg)) 105 106 #define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE 107 #define ETH_ALEN MAC_ADDR_LEN 108 #define ETH_ZLEN 60 109 110 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)(unsigned long)dev->priv, \ 111 (pci_addr_t)(unsigned long)a) 112 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)(unsigned long)dev->priv, \ 113 (phys_addr_t)a) 114 115 enum RTL8169_registers { 116 MAC0 = 0, /* Ethernet hardware address. */ 117 MAR0 = 8, /* Multicast filter. */ 118 TxDescStartAddrLow = 0x20, 119 TxDescStartAddrHigh = 0x24, 120 TxHDescStartAddrLow = 0x28, 121 TxHDescStartAddrHigh = 0x2c, 122 FLASH = 0x30, 123 ERSR = 0x36, 124 ChipCmd = 0x37, 125 TxPoll = 0x38, 126 IntrMask = 0x3C, 127 IntrStatus = 0x3E, 128 TxConfig = 0x40, 129 RxConfig = 0x44, 130 RxMissed = 0x4C, 131 Cfg9346 = 0x50, 132 Config0 = 0x51, 133 Config1 = 0x52, 134 Config2 = 0x53, 135 Config3 = 0x54, 136 Config4 = 0x55, 137 Config5 = 0x56, 138 MultiIntr = 0x5C, 139 PHYAR = 0x60, 140 TBICSR = 0x64, 141 TBI_ANAR = 0x68, 142 TBI_LPAR = 0x6A, 143 PHYstatus = 0x6C, 144 RxMaxSize = 0xDA, 145 CPlusCmd = 0xE0, 146 RxDescStartAddrLow = 0xE4, 147 RxDescStartAddrHigh = 0xE8, 148 EarlyTxThres = 0xEC, 149 FuncEvent = 0xF0, 150 FuncEventMask = 0xF4, 151 FuncPresetState = 0xF8, 152 FuncForceEvent = 0xFC, 153 }; 154 155 enum RTL8169_register_content { 156 /*InterruptStatusBits */ 157 SYSErr = 0x8000, 158 PCSTimeout = 0x4000, 159 SWInt = 0x0100, 160 TxDescUnavail = 0x80, 161 RxFIFOOver = 0x40, 162 RxUnderrun = 0x20, 163 RxOverflow = 0x10, 164 TxErr = 0x08, 165 TxOK = 0x04, 166 RxErr = 0x02, 167 RxOK = 0x01, 168 169 /*RxStatusDesc */ 170 RxRES = 0x00200000, 171 RxCRC = 0x00080000, 172 RxRUNT = 0x00100000, 173 RxRWT = 0x00400000, 174 175 /*ChipCmdBits */ 176 CmdReset = 0x10, 177 CmdRxEnb = 0x08, 178 CmdTxEnb = 0x04, 179 RxBufEmpty = 0x01, 180 181 /*Cfg9346Bits */ 182 Cfg9346_Lock = 0x00, 183 Cfg9346_Unlock = 0xC0, 184 185 /*rx_mode_bits */ 186 AcceptErr = 0x20, 187 AcceptRunt = 0x10, 188 AcceptBroadcast = 0x08, 189 AcceptMulticast = 0x04, 190 AcceptMyPhys = 0x02, 191 AcceptAllPhys = 0x01, 192 193 /*RxConfigBits */ 194 RxCfgFIFOShift = 13, 195 RxCfgDMAShift = 8, 196 197 /*TxConfigBits */ 198 TxInterFrameGapShift = 24, 199 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 200 201 /*rtl8169_PHYstatus */ 202 TBI_Enable = 0x80, 203 TxFlowCtrl = 0x40, 204 RxFlowCtrl = 0x20, 205 _1000bpsF = 0x10, 206 _100bps = 0x08, 207 _10bps = 0x04, 208 LinkStatus = 0x02, 209 FullDup = 0x01, 210 211 /*GIGABIT_PHY_registers */ 212 PHY_CTRL_REG = 0, 213 PHY_STAT_REG = 1, 214 PHY_AUTO_NEGO_REG = 4, 215 PHY_1000_CTRL_REG = 9, 216 217 /*GIGABIT_PHY_REG_BIT */ 218 PHY_Restart_Auto_Nego = 0x0200, 219 PHY_Enable_Auto_Nego = 0x1000, 220 221 /* PHY_STAT_REG = 1; */ 222 PHY_Auto_Nego_Comp = 0x0020, 223 224 /* PHY_AUTO_NEGO_REG = 4; */ 225 PHY_Cap_10_Half = 0x0020, 226 PHY_Cap_10_Full = 0x0040, 227 PHY_Cap_100_Half = 0x0080, 228 PHY_Cap_100_Full = 0x0100, 229 230 /* PHY_1000_CTRL_REG = 9; */ 231 PHY_Cap_1000_Full = 0x0200, 232 233 PHY_Cap_Null = 0x0, 234 235 /*_MediaType*/ 236 _10_Half = 0x01, 237 _10_Full = 0x02, 238 _100_Half = 0x04, 239 _100_Full = 0x08, 240 _1000_Full = 0x10, 241 242 /*_TBICSRBit*/ 243 TBILinkOK = 0x02000000, 244 }; 245 246 static struct { 247 const char *name; 248 u8 version; /* depend on RTL8169 docs */ 249 u32 RxConfigMask; /* should clear the bits supported by this chip */ 250 } rtl_chip_info[] = { 251 {"RTL-8169", 0x00, 0xff7e1880,}, 252 {"RTL-8169", 0x04, 0xff7e1880,}, 253 {"RTL-8169", 0x00, 0xff7e1880,}, 254 {"RTL-8169s/8110s", 0x02, 0xff7e1880,}, 255 {"RTL-8169s/8110s", 0x04, 0xff7e1880,}, 256 {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,}, 257 {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,}, 258 {"RTL-8168b/8111sb", 0x30, 0xff7e1880,}, 259 {"RTL-8168b/8111sb", 0x38, 0xff7e1880,}, 260 {"RTL-8168d/8111d", 0x28, 0xff7e1880,}, 261 {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,}, 262 {"RTL-8168/8111g", 0x4c, 0xff7e1880,}, 263 {"RTL-8101e", 0x34, 0xff7e1880,}, 264 {"RTL-8100e", 0x32, 0xff7e1880,}, 265 }; 266 267 enum _DescStatusBit { 268 OWNbit = 0x80000000, 269 EORbit = 0x40000000, 270 FSbit = 0x20000000, 271 LSbit = 0x10000000, 272 }; 273 274 struct TxDesc { 275 u32 status; 276 u32 vlan_tag; 277 u32 buf_addr; 278 u32 buf_Haddr; 279 }; 280 281 struct RxDesc { 282 u32 status; 283 u32 vlan_tag; 284 u32 buf_addr; 285 u32 buf_Haddr; 286 }; 287 288 static unsigned char rxdata[RX_BUF_LEN]; 289 290 #define RTL8169_DESC_SIZE 16 291 292 #if ARCH_DMA_MINALIGN > 256 293 # define RTL8169_ALIGN ARCH_DMA_MINALIGN 294 #else 295 # define RTL8169_ALIGN 256 296 #endif 297 298 /* 299 * Warn if the cache-line size is larger than the descriptor size. In such 300 * cases the driver will likely fail because the CPU needs to flush the cache 301 * when requeuing RX buffers, therefore descriptors written by the hardware 302 * may be discarded. 303 * 304 * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause 305 * the driver to allocate descriptors from a pool of non-cached memory. 306 */ 307 #if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN 308 #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \ 309 !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86) 310 #warning cache-line size is larger than descriptor size 311 #endif 312 #endif 313 314 /* 315 * Create a static buffer of size RX_BUF_SZ for each TX Descriptor. All 316 * descriptors point to a part of this buffer. 317 */ 318 DEFINE_ALIGN_BUFFER(u8, txb, NUM_TX_DESC * RX_BUF_SIZE, RTL8169_ALIGN); 319 320 /* 321 * Create a static buffer of size RX_BUF_SZ for each RX Descriptor. All 322 * descriptors point to a part of this buffer. 323 */ 324 DEFINE_ALIGN_BUFFER(u8, rxb, NUM_RX_DESC * RX_BUF_SIZE, RTL8169_ALIGN); 325 326 struct rtl8169_private { 327 ulong iobase; 328 void *mmio_addr; /* memory map physical address */ 329 int chipset; 330 unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 331 unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 332 unsigned long dirty_tx; 333 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */ 334 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */ 335 unsigned char *RxBufferRings; /* Index of Rx Buffer */ 336 unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */ 337 unsigned char *Tx_skbuff[NUM_TX_DESC]; 338 } tpx; 339 340 static struct rtl8169_private *tpc; 341 342 static const u16 rtl8169_intr_mask = 343 SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr | 344 TxOK | RxErr | RxOK; 345 static const unsigned int rtl8169_rx_config = 346 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); 347 348 static struct pci_device_id supported[] = { 349 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167) }, 350 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168) }, 351 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169) }, 352 {} 353 }; 354 355 void mdio_write(int RegAddr, int value) 356 { 357 int i; 358 359 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value); 360 udelay(1000); 361 362 for (i = 2000; i > 0; i--) { 363 /* Check if the RTL8169 has completed writing to the specified MII register */ 364 if (!(RTL_R32(PHYAR) & 0x80000000)) { 365 break; 366 } else { 367 udelay(100); 368 } 369 } 370 } 371 372 int mdio_read(int RegAddr) 373 { 374 int i, value = -1; 375 376 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16); 377 udelay(1000); 378 379 for (i = 2000; i > 0; i--) { 380 /* Check if the RTL8169 has completed retrieving data from the specified MII register */ 381 if (RTL_R32(PHYAR) & 0x80000000) { 382 value = (int) (RTL_R32(PHYAR) & 0xFFFF); 383 break; 384 } else { 385 udelay(100); 386 } 387 } 388 return value; 389 } 390 391 static int rtl8169_init_board(unsigned long dev_iobase, const char *name) 392 { 393 int i; 394 u32 tmp; 395 396 #ifdef DEBUG_RTL8169 397 printf ("%s\n", __FUNCTION__); 398 #endif 399 ioaddr = dev_iobase; 400 401 /* Soft reset the chip. */ 402 RTL_W8(ChipCmd, CmdReset); 403 404 /* Check that the chip has finished the reset. */ 405 for (i = 1000; i > 0; i--) 406 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 407 break; 408 else 409 udelay(10); 410 411 /* identify chip attached to board */ 412 tmp = RTL_R32(TxConfig); 413 tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24; 414 415 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){ 416 if (tmp == rtl_chip_info[i].version) { 417 tpc->chipset = i; 418 goto match; 419 } 420 } 421 422 /* if unknown chip, assume array element #0, original RTL-8169 in this case */ 423 printf("PCI device %s: unknown chip version, assuming RTL-8169\n", 424 name); 425 printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig)); 426 tpc->chipset = 0; 427 428 match: 429 return 0; 430 } 431 432 /* 433 * TX and RX descriptors are 16 bytes. This causes problems with the cache 434 * maintenance on CPUs where the cache-line size exceeds the size of these 435 * descriptors. What will happen is that when the driver receives a packet 436 * it will be immediately requeued for the hardware to reuse. The CPU will 437 * therefore need to flush the cache-line containing the descriptor, which 438 * will cause all other descriptors in the same cache-line to be flushed 439 * along with it. If one of those descriptors had been written to by the 440 * device those changes (and the associated packet) will be lost. 441 * 442 * To work around this, we make use of non-cached memory if available. If 443 * descriptors are mapped uncached there's no need to manually flush them 444 * or invalidate them. 445 * 446 * Note that this only applies to descriptors. The packet data buffers do 447 * not have the same constraints since they are 1536 bytes large, so they 448 * are unlikely to share cache-lines. 449 */ 450 static void *rtl_alloc_descs(unsigned int num) 451 { 452 size_t size = num * RTL8169_DESC_SIZE; 453 454 #ifdef CONFIG_SYS_NONCACHED_MEMORY 455 return (void *)noncached_alloc(size, RTL8169_ALIGN); 456 #else 457 return memalign(RTL8169_ALIGN, size); 458 #endif 459 } 460 461 /* 462 * Cache maintenance functions. These are simple wrappers around the more 463 * general purpose flush_cache() and invalidate_dcache_range() functions. 464 */ 465 466 static void rtl_inval_rx_desc(struct RxDesc *desc) 467 { 468 #ifndef CONFIG_SYS_NONCACHED_MEMORY 469 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); 470 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN); 471 472 invalidate_dcache_range(start, end); 473 #endif 474 } 475 476 static void rtl_flush_rx_desc(struct RxDesc *desc) 477 { 478 #ifndef CONFIG_SYS_NONCACHED_MEMORY 479 flush_cache((unsigned long)desc, sizeof(*desc)); 480 #endif 481 } 482 483 static void rtl_inval_tx_desc(struct TxDesc *desc) 484 { 485 #ifndef CONFIG_SYS_NONCACHED_MEMORY 486 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); 487 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN); 488 489 invalidate_dcache_range(start, end); 490 #endif 491 } 492 493 static void rtl_flush_tx_desc(struct TxDesc *desc) 494 { 495 #ifndef CONFIG_SYS_NONCACHED_MEMORY 496 flush_cache((unsigned long)desc, sizeof(*desc)); 497 #endif 498 } 499 500 static void rtl_inval_buffer(void *buf, size_t size) 501 { 502 unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1); 503 unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN); 504 505 invalidate_dcache_range(start, end); 506 } 507 508 static void rtl_flush_buffer(void *buf, size_t size) 509 { 510 flush_cache((unsigned long)buf, size); 511 } 512 513 /************************************************************************** 514 RECV - Receive a frame 515 ***************************************************************************/ 516 static int rtl_recv_common(pci_dev_t bdf, unsigned long dev_iobase, 517 uchar **packetp) 518 { 519 /* return true if there's an ethernet packet ready to read */ 520 /* nic->packet should contain data on return */ 521 /* nic->packetlen should contain length of data */ 522 int cur_rx; 523 int length = 0; 524 525 #ifdef DEBUG_RTL8169_RX 526 printf ("%s\n", __FUNCTION__); 527 #endif 528 ioaddr = dev_iobase; 529 530 cur_rx = tpc->cur_rx; 531 532 rtl_inval_rx_desc(&tpc->RxDescArray[cur_rx]); 533 534 if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) { 535 if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) { 536 length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx]. 537 status) & 0x00001FFF) - 4; 538 539 rtl_inval_buffer(tpc->RxBufferRing[cur_rx], length); 540 memcpy(rxdata, tpc->RxBufferRing[cur_rx], length); 541 542 if (cur_rx == NUM_RX_DESC - 1) 543 tpc->RxDescArray[cur_rx].status = 544 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); 545 else 546 tpc->RxDescArray[cur_rx].status = 547 cpu_to_le32(OWNbit + RX_BUF_SIZE); 548 tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32( 549 pci_mem_to_phys(bdf, (pci_addr_t)(unsigned long) 550 tpc->RxBufferRing[cur_rx])); 551 rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]); 552 #ifdef CONFIG_DM_ETH 553 *packetp = rxdata; 554 #else 555 net_process_received_packet(rxdata, length); 556 #endif 557 } else { 558 puts("Error Rx"); 559 length = -EIO; 560 } 561 cur_rx = (cur_rx + 1) % NUM_RX_DESC; 562 tpc->cur_rx = cur_rx; 563 return length; 564 565 } else { 566 ushort sts = RTL_R8(IntrStatus); 567 RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr)); 568 udelay(100); /* wait */ 569 } 570 tpc->cur_rx = cur_rx; 571 return (0); /* initially as this is called to flush the input */ 572 } 573 574 #ifdef CONFIG_DM_ETH 575 int rtl8169_eth_recv(struct udevice *dev, int flags, uchar **packetp) 576 { 577 struct rtl8169_private *priv = dev_get_priv(dev); 578 579 return rtl_recv_common(dm_pci_get_bdf(dev), priv->iobase, packetp); 580 } 581 #else 582 static int rtl_recv(struct eth_device *dev) 583 { 584 return rtl_recv_common((pci_dev_t)(unsigned long)dev->priv, 585 dev->iobase, NULL); 586 } 587 #endif /* nCONFIG_DM_ETH */ 588 589 #define HZ 1000 590 /************************************************************************** 591 SEND - Transmit a frame 592 ***************************************************************************/ 593 static int rtl_send_common(pci_dev_t bdf, unsigned long dev_iobase, 594 void *packet, int length) 595 { 596 /* send the packet to destination */ 597 598 u32 to; 599 u8 *ptxb; 600 int entry = tpc->cur_tx % NUM_TX_DESC; 601 u32 len = length; 602 int ret; 603 604 #ifdef DEBUG_RTL8169_TX 605 int stime = currticks(); 606 printf ("%s\n", __FUNCTION__); 607 printf("sending %d bytes\n", len); 608 #endif 609 610 ioaddr = dev_iobase; 611 612 /* point to the current txb incase multiple tx_rings are used */ 613 ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE]; 614 memcpy(ptxb, (char *)packet, (int)length); 615 rtl_flush_buffer(ptxb, length); 616 617 while (len < ETH_ZLEN) 618 ptxb[len++] = '\0'; 619 620 tpc->TxDescArray[entry].buf_Haddr = 0; 621 tpc->TxDescArray[entry].buf_addr = cpu_to_le32( 622 pci_mem_to_phys(bdf, (pci_addr_t)(unsigned long)ptxb)); 623 if (entry != (NUM_TX_DESC - 1)) { 624 tpc->TxDescArray[entry].status = 625 cpu_to_le32((OWNbit | FSbit | LSbit) | 626 ((len > ETH_ZLEN) ? len : ETH_ZLEN)); 627 } else { 628 tpc->TxDescArray[entry].status = 629 cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) | 630 ((len > ETH_ZLEN) ? len : ETH_ZLEN)); 631 } 632 rtl_flush_tx_desc(&tpc->TxDescArray[entry]); 633 RTL_W8(TxPoll, 0x40); /* set polling bit */ 634 635 tpc->cur_tx++; 636 to = currticks() + TX_TIMEOUT; 637 do { 638 rtl_inval_tx_desc(&tpc->TxDescArray[entry]); 639 } while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit) 640 && (currticks() < to)); /* wait */ 641 642 if (currticks() >= to) { 643 #ifdef DEBUG_RTL8169_TX 644 puts("tx timeout/error\n"); 645 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 646 #endif 647 ret = 0; 648 } else { 649 #ifdef DEBUG_RTL8169_TX 650 puts("tx done\n"); 651 #endif 652 ret = length; 653 } 654 /* Delay to make net console (nc) work properly */ 655 udelay(20); 656 return ret; 657 } 658 659 #ifdef CONFIG_DM_ETH 660 int rtl8169_eth_send(struct udevice *dev, void *packet, int length) 661 { 662 struct rtl8169_private *priv = dev_get_priv(dev); 663 664 return rtl_send_common(dm_pci_get_bdf(dev), priv->iobase, packet, 665 length); 666 } 667 668 #else 669 static int rtl_send(struct eth_device *dev, void *packet, int length) 670 { 671 return rtl_send_common((pci_dev_t)(unsigned long)dev->priv, 672 dev->iobase, packet, length); 673 } 674 #endif 675 676 static void rtl8169_set_rx_mode(void) 677 { 678 u32 mc_filter[2]; /* Multicast hash filter */ 679 int rx_mode; 680 u32 tmp = 0; 681 682 #ifdef DEBUG_RTL8169 683 printf ("%s\n", __FUNCTION__); 684 #endif 685 686 /* IFF_ALLMULTI */ 687 /* Too many to filter perfectly -- accept all multicasts. */ 688 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; 689 mc_filter[1] = mc_filter[0] = 0xffffffff; 690 691 tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) & 692 rtl_chip_info[tpc->chipset].RxConfigMask); 693 694 RTL_W32(RxConfig, tmp); 695 RTL_W32(MAR0 + 0, mc_filter[0]); 696 RTL_W32(MAR0 + 4, mc_filter[1]); 697 } 698 699 static void rtl8169_hw_start(pci_dev_t bdf) 700 { 701 u32 i; 702 703 #ifdef DEBUG_RTL8169 704 int stime = currticks(); 705 printf ("%s\n", __FUNCTION__); 706 #endif 707 708 #if 0 709 /* Soft reset the chip. */ 710 RTL_W8(ChipCmd, CmdReset); 711 712 /* Check that the chip has finished the reset. */ 713 for (i = 1000; i > 0; i--) { 714 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 715 break; 716 else 717 udelay(10); 718 } 719 #endif 720 721 RTL_W8(Cfg9346, Cfg9346_Unlock); 722 723 /* RTL-8169sb/8110sb or previous version */ 724 if (tpc->chipset <= 5) 725 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 726 727 RTL_W8(EarlyTxThres, EarlyTxThld); 728 729 /* For gigabit rtl8169 */ 730 RTL_W16(RxMaxSize, RxPacketMaxSize); 731 732 /* Set Rx Config register */ 733 i = rtl8169_rx_config | (RTL_R32(RxConfig) & 734 rtl_chip_info[tpc->chipset].RxConfigMask); 735 RTL_W32(RxConfig, i); 736 737 /* Set DMA burst size and Interframe Gap Time */ 738 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | 739 (InterFrameGap << TxInterFrameGapShift)); 740 741 742 tpc->cur_rx = 0; 743 744 RTL_W32(TxDescStartAddrLow, pci_mem_to_phys(bdf, 745 (pci_addr_t)(unsigned long)tpc->TxDescArray)); 746 RTL_W32(TxDescStartAddrHigh, (unsigned long)0); 747 RTL_W32(RxDescStartAddrLow, pci_mem_to_phys( 748 bdf, (pci_addr_t)(unsigned long)tpc->RxDescArray)); 749 RTL_W32(RxDescStartAddrHigh, (unsigned long)0); 750 751 /* RTL-8169sc/8110sc or later version */ 752 if (tpc->chipset > 5) 753 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 754 755 RTL_W8(Cfg9346, Cfg9346_Lock); 756 udelay(10); 757 758 RTL_W32(RxMissed, 0); 759 760 rtl8169_set_rx_mode(); 761 762 /* no early-rx interrupts */ 763 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); 764 765 #ifdef DEBUG_RTL8169 766 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 767 #endif 768 } 769 770 static void rtl8169_init_ring(pci_dev_t bdf) 771 { 772 int i; 773 774 #ifdef DEBUG_RTL8169 775 int stime = currticks(); 776 printf ("%s\n", __FUNCTION__); 777 #endif 778 779 tpc->cur_rx = 0; 780 tpc->cur_tx = 0; 781 tpc->dirty_tx = 0; 782 memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc)); 783 memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc)); 784 785 for (i = 0; i < NUM_TX_DESC; i++) { 786 tpc->Tx_skbuff[i] = &txb[i]; 787 } 788 789 for (i = 0; i < NUM_RX_DESC; i++) { 790 if (i == (NUM_RX_DESC - 1)) 791 tpc->RxDescArray[i].status = 792 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); 793 else 794 tpc->RxDescArray[i].status = 795 cpu_to_le32(OWNbit + RX_BUF_SIZE); 796 797 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE]; 798 tpc->RxDescArray[i].buf_addr = cpu_to_le32(pci_mem_to_phys( 799 bdf, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i])); 800 rtl_flush_rx_desc(&tpc->RxDescArray[i]); 801 } 802 803 #ifdef DEBUG_RTL8169 804 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 805 #endif 806 } 807 808 static void rtl8169_common_start(pci_dev_t bdf, unsigned char *enetaddr) 809 { 810 int i; 811 812 #ifdef DEBUG_RTL8169 813 int stime = currticks(); 814 printf ("%s\n", __FUNCTION__); 815 #endif 816 817 rtl8169_init_ring(bdf); 818 rtl8169_hw_start(bdf); 819 /* Construct a perfect filter frame with the mac address as first match 820 * and broadcast for all others */ 821 for (i = 0; i < 192; i++) 822 txb[i] = 0xFF; 823 824 txb[0] = enetaddr[0]; 825 txb[1] = enetaddr[1]; 826 txb[2] = enetaddr[2]; 827 txb[3] = enetaddr[3]; 828 txb[4] = enetaddr[4]; 829 txb[5] = enetaddr[5]; 830 831 #ifdef DEBUG_RTL8169 832 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 833 #endif 834 } 835 836 #ifdef CONFIG_DM_ETH 837 static int rtl8169_eth_start(struct udevice *dev) 838 { 839 struct eth_pdata *plat = dev_get_platdata(dev); 840 841 rtl8169_common_start(dm_pci_get_bdf(dev), plat->enetaddr); 842 843 return 0; 844 } 845 #else 846 /************************************************************************** 847 RESET - Finish setting up the ethernet interface 848 ***************************************************************************/ 849 static int rtl_reset(struct eth_device *dev, bd_t *bis) 850 { 851 rtl8169_common_start((pci_dev_t)(unsigned long)dev->priv, 852 dev->enetaddr); 853 854 return 0; 855 } 856 #endif /* nCONFIG_DM_ETH */ 857 858 static void rtl_halt_common(unsigned long dev_iobase) 859 { 860 int i; 861 862 #ifdef DEBUG_RTL8169 863 printf ("%s\n", __FUNCTION__); 864 #endif 865 866 ioaddr = dev_iobase; 867 868 /* Stop the chip's Tx and Rx DMA processes. */ 869 RTL_W8(ChipCmd, 0x00); 870 871 /* Disable interrupts by clearing the interrupt mask. */ 872 RTL_W16(IntrMask, 0x0000); 873 874 RTL_W32(RxMissed, 0); 875 876 for (i = 0; i < NUM_RX_DESC; i++) { 877 tpc->RxBufferRing[i] = NULL; 878 } 879 } 880 881 #ifdef CONFIG_DM_ETH 882 void rtl8169_eth_stop(struct udevice *dev) 883 { 884 struct rtl8169_private *priv = dev_get_priv(dev); 885 886 rtl_halt_common(priv->iobase); 887 } 888 #else 889 /************************************************************************** 890 HALT - Turn off ethernet interface 891 ***************************************************************************/ 892 static void rtl_halt(struct eth_device *dev) 893 { 894 rtl_halt_common(dev->iobase); 895 } 896 #endif 897 898 /************************************************************************** 899 INIT - Look for an adapter, this routine's visible to the outside 900 ***************************************************************************/ 901 902 #define board_found 1 903 #define valid_link 0 904 static int rtl_init(unsigned long dev_ioaddr, const char *name, 905 unsigned char *enetaddr) 906 { 907 static int board_idx = -1; 908 int i, rc; 909 int option = -1, Cap10_100 = 0, Cap1000 = 0; 910 911 #ifdef DEBUG_RTL8169 912 printf ("%s\n", __FUNCTION__); 913 #endif 914 ioaddr = dev_ioaddr; 915 916 board_idx++; 917 918 /* point to private storage */ 919 tpc = &tpx; 920 921 rc = rtl8169_init_board(ioaddr, name); 922 if (rc) 923 return rc; 924 925 /* Get MAC address. FIXME: read EEPROM */ 926 for (i = 0; i < MAC_ADDR_LEN; i++) 927 enetaddr[i] = RTL_R8(MAC0 + i); 928 929 #ifdef DEBUG_RTL8169 930 printf("chipset = %d\n", tpc->chipset); 931 printf("MAC Address"); 932 for (i = 0; i < MAC_ADDR_LEN; i++) 933 printf(":%02x", enetaddr[i]); 934 putc('\n'); 935 #endif 936 937 #ifdef DEBUG_RTL8169 938 /* Print out some hardware info */ 939 printf("%s: at ioaddr 0x%lx\n", name, ioaddr); 940 #endif 941 942 /* if TBI is not endbled */ 943 if (!(RTL_R8(PHYstatus) & TBI_Enable)) { 944 int val = mdio_read(PHY_AUTO_NEGO_REG); 945 946 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx]; 947 /* Force RTL8169 in 10/100/1000 Full/Half mode. */ 948 if (option > 0) { 949 #ifdef DEBUG_RTL8169 950 printf("%s: Force-mode Enabled.\n", dev->name); 951 #endif 952 Cap10_100 = 0, Cap1000 = 0; 953 switch (option) { 954 case _10_Half: 955 Cap10_100 = PHY_Cap_10_Half; 956 Cap1000 = PHY_Cap_Null; 957 break; 958 case _10_Full: 959 Cap10_100 = PHY_Cap_10_Full; 960 Cap1000 = PHY_Cap_Null; 961 break; 962 case _100_Half: 963 Cap10_100 = PHY_Cap_100_Half; 964 Cap1000 = PHY_Cap_Null; 965 break; 966 case _100_Full: 967 Cap10_100 = PHY_Cap_100_Full; 968 Cap1000 = PHY_Cap_Null; 969 break; 970 case _1000_Full: 971 Cap10_100 = PHY_Cap_Null; 972 Cap1000 = PHY_Cap_1000_Full; 973 break; 974 default: 975 break; 976 } 977 mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 978 mdio_write(PHY_1000_CTRL_REG, Cap1000); 979 } else { 980 #ifdef DEBUG_RTL8169 981 printf("%s: Auto-negotiation Enabled.\n", 982 dev->name); 983 #endif 984 /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 985 mdio_write(PHY_AUTO_NEGO_REG, 986 PHY_Cap_10_Half | PHY_Cap_10_Full | 987 PHY_Cap_100_Half | PHY_Cap_100_Full | 988 (val & 0x1F)); 989 990 /* enable 1000 Full Mode */ 991 mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full); 992 993 } 994 995 /* Enable auto-negotiation and restart auto-nigotiation */ 996 mdio_write(PHY_CTRL_REG, 997 PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego); 998 udelay(100); 999 1000 /* wait for auto-negotiation process */ 1001 for (i = 10000; i > 0; i--) { 1002 /* check if auto-negotiation complete */ 1003 if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) { 1004 udelay(100); 1005 option = RTL_R8(PHYstatus); 1006 if (option & _1000bpsF) { 1007 #ifdef DEBUG_RTL8169 1008 printf("%s: 1000Mbps Full-duplex operation.\n", 1009 dev->name); 1010 #endif 1011 } else { 1012 #ifdef DEBUG_RTL8169 1013 printf("%s: %sMbps %s-duplex operation.\n", 1014 dev->name, 1015 (option & _100bps) ? "100" : 1016 "10", 1017 (option & FullDup) ? "Full" : 1018 "Half"); 1019 #endif 1020 } 1021 break; 1022 } else { 1023 udelay(100); 1024 } 1025 } /* end for-loop to wait for auto-negotiation process */ 1026 1027 } else { 1028 udelay(100); 1029 #ifdef DEBUG_RTL8169 1030 printf 1031 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n", 1032 dev->name, 1033 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed"); 1034 #endif 1035 } 1036 1037 1038 tpc->RxDescArray = rtl_alloc_descs(NUM_RX_DESC); 1039 if (!tpc->RxDescArray) 1040 return -ENOMEM; 1041 1042 tpc->TxDescArray = rtl_alloc_descs(NUM_TX_DESC); 1043 if (!tpc->TxDescArray) 1044 return -ENOMEM; 1045 1046 return 0; 1047 } 1048 1049 #ifndef CONFIG_DM_ETH 1050 int rtl8169_initialize(bd_t *bis) 1051 { 1052 pci_dev_t devno; 1053 int card_number = 0; 1054 struct eth_device *dev; 1055 u32 iobase; 1056 int idx=0; 1057 1058 while(1){ 1059 unsigned int region; 1060 u16 device; 1061 int err; 1062 1063 /* Find RTL8169 */ 1064 if ((devno = pci_find_devices(supported, idx++)) < 0) 1065 break; 1066 1067 pci_read_config_word(devno, PCI_DEVICE_ID, &device); 1068 switch (device) { 1069 case 0x8168: 1070 region = 2; 1071 break; 1072 1073 default: 1074 region = 1; 1075 break; 1076 } 1077 1078 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase); 1079 iobase &= ~0xf; 1080 1081 debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); 1082 1083 dev = (struct eth_device *)malloc(sizeof *dev); 1084 if (!dev) { 1085 printf("Can not allocate memory of rtl8169\n"); 1086 break; 1087 } 1088 1089 memset(dev, 0, sizeof(*dev)); 1090 sprintf (dev->name, "RTL8169#%d", card_number); 1091 1092 dev->priv = (void *)(unsigned long)devno; 1093 dev->iobase = (int)pci_mem_to_phys(devno, iobase); 1094 1095 dev->init = rtl_reset; 1096 dev->halt = rtl_halt; 1097 dev->send = rtl_send; 1098 dev->recv = rtl_recv; 1099 1100 err = rtl_init(dev->iobase, dev->name, dev->enetaddr); 1101 if (err < 0) { 1102 printf(pr_fmt("failed to initialize card: %d\n"), err); 1103 free(dev); 1104 continue; 1105 } 1106 1107 eth_register (dev); 1108 1109 card_number++; 1110 } 1111 return card_number; 1112 } 1113 #endif 1114 1115 #ifdef CONFIG_DM_ETH 1116 static int rtl8169_eth_probe(struct udevice *dev) 1117 { 1118 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev); 1119 struct rtl8169_private *priv = dev_get_priv(dev); 1120 struct eth_pdata *plat = dev_get_platdata(dev); 1121 u32 iobase; 1122 int region; 1123 int ret; 1124 1125 debug("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); 1126 switch (pplat->device) { 1127 case 0x8168: 1128 region = 2; 1129 break; 1130 default: 1131 region = 1; 1132 break; 1133 } 1134 pci_read_config32(dm_pci_get_bdf(dev), PCI_BASE_ADDRESS_0 + region * 4, 1135 &iobase); 1136 iobase &= ~0xf; 1137 priv->iobase = (int)pci_mem_to_phys(dm_pci_get_bdf(dev), iobase); 1138 1139 ret = rtl_init(priv->iobase, dev->name, plat->enetaddr); 1140 if (ret < 0) { 1141 printf(pr_fmt("failed to initialize card: %d\n"), ret); 1142 return ret; 1143 } 1144 1145 return 0; 1146 } 1147 1148 static const struct eth_ops rtl8169_eth_ops = { 1149 .start = rtl8169_eth_start, 1150 .send = rtl8169_eth_send, 1151 .recv = rtl8169_eth_recv, 1152 .stop = rtl8169_eth_stop, 1153 }; 1154 1155 static const struct udevice_id rtl8169_eth_ids[] = { 1156 { .compatible = "realtek,rtl8169" }, 1157 { } 1158 }; 1159 1160 U_BOOT_DRIVER(eth_rtl8169) = { 1161 .name = "eth_rtl8169", 1162 .id = UCLASS_ETH, 1163 .of_match = rtl8169_eth_ids, 1164 .probe = rtl8169_eth_probe, 1165 .ops = &rtl8169_eth_ops, 1166 .priv_auto_alloc_size = sizeof(struct rtl8169_private), 1167 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 1168 }; 1169 1170 U_BOOT_PCI_DEVICE(eth_rtl8169, supported); 1171 #endif 1172