1 /* 2 * rtl8169.c : U-Boot driver for the RealTek RTL8169 3 * 4 * Masami Komiya (mkomiya@sonare.it) 5 * 6 * Most part is taken from r8169.c of etherboot 7 * 8 */ 9 10 /************************************************************************** 11 * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit 12 * Written 2003 by Timothy Legge <tlegge@rogers.com> 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 * 16 * Portions of this code based on: 17 * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver 18 * for Linux kernel 2.4.x. 19 * 20 * Written 2002 ShuChen <shuchen@realtek.com.tw> 21 * See Linux Driver for full information 22 * 23 * Linux Driver Version 1.27a, 10.02.2002 24 * 25 * Thanks to: 26 * Jean Chen of RealTek Semiconductor Corp. for 27 * providing the evaluation NIC used to develop 28 * this driver. RealTek's support for Etherboot 29 * is appreciated. 30 * 31 * REVISION HISTORY: 32 * ================ 33 * 34 * v1.0 11-26-2003 timlegge Initial port of Linux driver 35 * v1.5 01-17-2004 timlegge Initial driver output cleanup 36 * 37 * Indent Options: indent -kr -i8 38 ***************************************************************************/ 39 /* 40 * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk> 41 * Modified to use le32_to_cpu and cpu_to_le32 properly 42 */ 43 #include <common.h> 44 #include <malloc.h> 45 #include <net.h> 46 #include <netdev.h> 47 #include <asm/io.h> 48 #include <pci.h> 49 50 #undef DEBUG_RTL8169 51 #undef DEBUG_RTL8169_TX 52 #undef DEBUG_RTL8169_RX 53 54 #define drv_version "v1.5" 55 #define drv_date "01-17-2004" 56 57 static u32 ioaddr; 58 59 /* Condensed operations for readability. */ 60 #define currticks() get_timer(0) 61 62 /* media options */ 63 #define MAX_UNITS 8 64 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 }; 65 66 /* MAC address length*/ 67 #define MAC_ADDR_LEN 6 68 69 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/ 70 #define MAX_ETH_FRAME_SIZE 1536 71 72 #define TX_FIFO_THRESH 256 /* In bytes */ 73 74 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ 75 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 76 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 77 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ 78 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */ 79 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 80 81 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */ 82 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */ 83 #define RX_BUF_SIZE 1536 /* Rx Buffer size */ 84 #define RX_BUF_LEN 8192 85 86 #define RTL_MIN_IO_SIZE 0x80 87 #define TX_TIMEOUT (6*HZ) 88 89 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */ 90 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) 91 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) 92 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) 93 #define RTL_R8(reg) readb (ioaddr + (reg)) 94 #define RTL_R16(reg) readw (ioaddr + (reg)) 95 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) 96 97 #define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE 98 #define ETH_ALEN MAC_ADDR_LEN 99 #define ETH_ZLEN 60 100 101 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, (pci_addr_t)a) 102 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, (phys_addr_t)a) 103 104 enum RTL8169_registers { 105 MAC0 = 0, /* Ethernet hardware address. */ 106 MAR0 = 8, /* Multicast filter. */ 107 TxDescStartAddrLow = 0x20, 108 TxDescStartAddrHigh = 0x24, 109 TxHDescStartAddrLow = 0x28, 110 TxHDescStartAddrHigh = 0x2c, 111 FLASH = 0x30, 112 ERSR = 0x36, 113 ChipCmd = 0x37, 114 TxPoll = 0x38, 115 IntrMask = 0x3C, 116 IntrStatus = 0x3E, 117 TxConfig = 0x40, 118 RxConfig = 0x44, 119 RxMissed = 0x4C, 120 Cfg9346 = 0x50, 121 Config0 = 0x51, 122 Config1 = 0x52, 123 Config2 = 0x53, 124 Config3 = 0x54, 125 Config4 = 0x55, 126 Config5 = 0x56, 127 MultiIntr = 0x5C, 128 PHYAR = 0x60, 129 TBICSR = 0x64, 130 TBI_ANAR = 0x68, 131 TBI_LPAR = 0x6A, 132 PHYstatus = 0x6C, 133 RxMaxSize = 0xDA, 134 CPlusCmd = 0xE0, 135 RxDescStartAddrLow = 0xE4, 136 RxDescStartAddrHigh = 0xE8, 137 EarlyTxThres = 0xEC, 138 FuncEvent = 0xF0, 139 FuncEventMask = 0xF4, 140 FuncPresetState = 0xF8, 141 FuncForceEvent = 0xFC, 142 }; 143 144 enum RTL8169_register_content { 145 /*InterruptStatusBits */ 146 SYSErr = 0x8000, 147 PCSTimeout = 0x4000, 148 SWInt = 0x0100, 149 TxDescUnavail = 0x80, 150 RxFIFOOver = 0x40, 151 RxUnderrun = 0x20, 152 RxOverflow = 0x10, 153 TxErr = 0x08, 154 TxOK = 0x04, 155 RxErr = 0x02, 156 RxOK = 0x01, 157 158 /*RxStatusDesc */ 159 RxRES = 0x00200000, 160 RxCRC = 0x00080000, 161 RxRUNT = 0x00100000, 162 RxRWT = 0x00400000, 163 164 /*ChipCmdBits */ 165 CmdReset = 0x10, 166 CmdRxEnb = 0x08, 167 CmdTxEnb = 0x04, 168 RxBufEmpty = 0x01, 169 170 /*Cfg9346Bits */ 171 Cfg9346_Lock = 0x00, 172 Cfg9346_Unlock = 0xC0, 173 174 /*rx_mode_bits */ 175 AcceptErr = 0x20, 176 AcceptRunt = 0x10, 177 AcceptBroadcast = 0x08, 178 AcceptMulticast = 0x04, 179 AcceptMyPhys = 0x02, 180 AcceptAllPhys = 0x01, 181 182 /*RxConfigBits */ 183 RxCfgFIFOShift = 13, 184 RxCfgDMAShift = 8, 185 186 /*TxConfigBits */ 187 TxInterFrameGapShift = 24, 188 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 189 190 /*rtl8169_PHYstatus */ 191 TBI_Enable = 0x80, 192 TxFlowCtrl = 0x40, 193 RxFlowCtrl = 0x20, 194 _1000bpsF = 0x10, 195 _100bps = 0x08, 196 _10bps = 0x04, 197 LinkStatus = 0x02, 198 FullDup = 0x01, 199 200 /*GIGABIT_PHY_registers */ 201 PHY_CTRL_REG = 0, 202 PHY_STAT_REG = 1, 203 PHY_AUTO_NEGO_REG = 4, 204 PHY_1000_CTRL_REG = 9, 205 206 /*GIGABIT_PHY_REG_BIT */ 207 PHY_Restart_Auto_Nego = 0x0200, 208 PHY_Enable_Auto_Nego = 0x1000, 209 210 /* PHY_STAT_REG = 1; */ 211 PHY_Auto_Nego_Comp = 0x0020, 212 213 /* PHY_AUTO_NEGO_REG = 4; */ 214 PHY_Cap_10_Half = 0x0020, 215 PHY_Cap_10_Full = 0x0040, 216 PHY_Cap_100_Half = 0x0080, 217 PHY_Cap_100_Full = 0x0100, 218 219 /* PHY_1000_CTRL_REG = 9; */ 220 PHY_Cap_1000_Full = 0x0200, 221 222 PHY_Cap_Null = 0x0, 223 224 /*_MediaType*/ 225 _10_Half = 0x01, 226 _10_Full = 0x02, 227 _100_Half = 0x04, 228 _100_Full = 0x08, 229 _1000_Full = 0x10, 230 231 /*_TBICSRBit*/ 232 TBILinkOK = 0x02000000, 233 }; 234 235 static struct { 236 const char *name; 237 u8 version; /* depend on RTL8169 docs */ 238 u32 RxConfigMask; /* should clear the bits supported by this chip */ 239 } rtl_chip_info[] = { 240 {"RTL-8169", 0x00, 0xff7e1880,}, 241 {"RTL-8169", 0x04, 0xff7e1880,}, 242 {"RTL-8169", 0x00, 0xff7e1880,}, 243 {"RTL-8169s/8110s", 0x02, 0xff7e1880,}, 244 {"RTL-8169s/8110s", 0x04, 0xff7e1880,}, 245 {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,}, 246 {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,}, 247 {"RTL-8168b/8111sb", 0x30, 0xff7e1880,}, 248 {"RTL-8168b/8111sb", 0x38, 0xff7e1880,}, 249 {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,}, 250 {"RTL-8101e", 0x34, 0xff7e1880,}, 251 {"RTL-8100e", 0x32, 0xff7e1880,}, 252 }; 253 254 enum _DescStatusBit { 255 OWNbit = 0x80000000, 256 EORbit = 0x40000000, 257 FSbit = 0x20000000, 258 LSbit = 0x10000000, 259 }; 260 261 struct TxDesc { 262 u32 status; 263 u32 vlan_tag; 264 u32 buf_addr; 265 u32 buf_Haddr; 266 }; 267 268 struct RxDesc { 269 u32 status; 270 u32 vlan_tag; 271 u32 buf_addr; 272 u32 buf_Haddr; 273 }; 274 275 /* Define the TX Descriptor */ 276 static u8 tx_ring[NUM_TX_DESC * sizeof(struct TxDesc) + 256]; 277 /* __attribute__ ((aligned(256))); */ 278 279 /* Create a static buffer of size RX_BUF_SZ for each 280 TX Descriptor. All descriptors point to a 281 part of this buffer */ 282 static unsigned char txb[NUM_TX_DESC * RX_BUF_SIZE]; 283 284 /* Define the RX Descriptor */ 285 static u8 rx_ring[NUM_RX_DESC * sizeof(struct TxDesc) + 256]; 286 /* __attribute__ ((aligned(256))); */ 287 288 /* Create a static buffer of size RX_BUF_SZ for each 289 RX Descriptor All descriptors point to a 290 part of this buffer */ 291 static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE]; 292 293 struct rtl8169_private { 294 void *mmio_addr; /* memory map physical address */ 295 int chipset; 296 unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 297 unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 298 unsigned long dirty_tx; 299 unsigned char *TxDescArrays; /* Index of Tx Descriptor buffer */ 300 unsigned char *RxDescArrays; /* Index of Rx Descriptor buffer */ 301 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */ 302 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */ 303 unsigned char *RxBufferRings; /* Index of Rx Buffer */ 304 unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */ 305 unsigned char *Tx_skbuff[NUM_TX_DESC]; 306 } tpx; 307 308 static struct rtl8169_private *tpc; 309 310 static const u16 rtl8169_intr_mask = 311 SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr | 312 TxOK | RxErr | RxOK; 313 static const unsigned int rtl8169_rx_config = 314 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); 315 316 static struct pci_device_id supported[] = { 317 {PCI_VENDOR_ID_REALTEK, 0x8167}, 318 {PCI_VENDOR_ID_REALTEK, 0x8169}, 319 {} 320 }; 321 322 void mdio_write(int RegAddr, int value) 323 { 324 int i; 325 326 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value); 327 udelay(1000); 328 329 for (i = 2000; i > 0; i--) { 330 /* Check if the RTL8169 has completed writing to the specified MII register */ 331 if (!(RTL_R32(PHYAR) & 0x80000000)) { 332 break; 333 } else { 334 udelay(100); 335 } 336 } 337 } 338 339 int mdio_read(int RegAddr) 340 { 341 int i, value = -1; 342 343 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16); 344 udelay(1000); 345 346 for (i = 2000; i > 0; i--) { 347 /* Check if the RTL8169 has completed retrieving data from the specified MII register */ 348 if (RTL_R32(PHYAR) & 0x80000000) { 349 value = (int) (RTL_R32(PHYAR) & 0xFFFF); 350 break; 351 } else { 352 udelay(100); 353 } 354 } 355 return value; 356 } 357 358 static int rtl8169_init_board(struct eth_device *dev) 359 { 360 int i; 361 u32 tmp; 362 363 #ifdef DEBUG_RTL8169 364 printf ("%s\n", __FUNCTION__); 365 #endif 366 ioaddr = dev->iobase; 367 368 /* Soft reset the chip. */ 369 RTL_W8(ChipCmd, CmdReset); 370 371 /* Check that the chip has finished the reset. */ 372 for (i = 1000; i > 0; i--) 373 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 374 break; 375 else 376 udelay(10); 377 378 /* identify chip attached to board */ 379 tmp = RTL_R32(TxConfig); 380 tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24; 381 382 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){ 383 if (tmp == rtl_chip_info[i].version) { 384 tpc->chipset = i; 385 goto match; 386 } 387 } 388 389 /* if unknown chip, assume array element #0, original RTL-8169 in this case */ 390 printf("PCI device %s: unknown chip version, assuming RTL-8169\n", dev->name); 391 printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig)); 392 tpc->chipset = 0; 393 394 match: 395 return 0; 396 } 397 398 /************************************************************************** 399 RECV - Receive a frame 400 ***************************************************************************/ 401 static int rtl_recv(struct eth_device *dev) 402 { 403 /* return true if there's an ethernet packet ready to read */ 404 /* nic->packet should contain data on return */ 405 /* nic->packetlen should contain length of data */ 406 int cur_rx; 407 int length = 0; 408 409 #ifdef DEBUG_RTL8169_RX 410 printf ("%s\n", __FUNCTION__); 411 #endif 412 ioaddr = dev->iobase; 413 414 cur_rx = tpc->cur_rx; 415 flush_cache((unsigned long)&tpc->RxDescArray[cur_rx], 416 sizeof(struct RxDesc)); 417 if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) { 418 if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) { 419 unsigned char rxdata[RX_BUF_LEN]; 420 length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx]. 421 status) & 0x00001FFF) - 4; 422 423 memcpy(rxdata, tpc->RxBufferRing[cur_rx], length); 424 NetReceive(rxdata, length); 425 426 if (cur_rx == NUM_RX_DESC - 1) 427 tpc->RxDescArray[cur_rx].status = 428 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); 429 else 430 tpc->RxDescArray[cur_rx].status = 431 cpu_to_le32(OWNbit + RX_BUF_SIZE); 432 tpc->RxDescArray[cur_rx].buf_addr = 433 cpu_to_le32(bus_to_phys(tpc->RxBufferRing[cur_rx])); 434 flush_cache((unsigned long)tpc->RxBufferRing[cur_rx], 435 RX_BUF_SIZE); 436 } else { 437 puts("Error Rx"); 438 } 439 cur_rx = (cur_rx + 1) % NUM_RX_DESC; 440 tpc->cur_rx = cur_rx; 441 return 1; 442 443 } else { 444 ushort sts = RTL_R8(IntrStatus); 445 RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr)); 446 udelay(100); /* wait */ 447 } 448 tpc->cur_rx = cur_rx; 449 return (0); /* initially as this is called to flush the input */ 450 } 451 452 #define HZ 1000 453 /************************************************************************** 454 SEND - Transmit a frame 455 ***************************************************************************/ 456 static int rtl_send(struct eth_device *dev, void *packet, int length) 457 { 458 /* send the packet to destination */ 459 460 u32 to; 461 u8 *ptxb; 462 int entry = tpc->cur_tx % NUM_TX_DESC; 463 u32 len = length; 464 int ret; 465 466 #ifdef DEBUG_RTL8169_TX 467 int stime = currticks(); 468 printf ("%s\n", __FUNCTION__); 469 printf("sending %d bytes\n", len); 470 #endif 471 472 ioaddr = dev->iobase; 473 474 /* point to the current txb incase multiple tx_rings are used */ 475 ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE]; 476 memcpy(ptxb, (char *)packet, (int)length); 477 flush_cache((unsigned long)ptxb, length); 478 479 while (len < ETH_ZLEN) 480 ptxb[len++] = '\0'; 481 482 tpc->TxDescArray[entry].buf_Haddr = 0; 483 tpc->TxDescArray[entry].buf_addr = cpu_to_le32(bus_to_phys(ptxb)); 484 if (entry != (NUM_TX_DESC - 1)) { 485 tpc->TxDescArray[entry].status = 486 cpu_to_le32((OWNbit | FSbit | LSbit) | 487 ((len > ETH_ZLEN) ? len : ETH_ZLEN)); 488 } else { 489 tpc->TxDescArray[entry].status = 490 cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) | 491 ((len > ETH_ZLEN) ? len : ETH_ZLEN)); 492 } 493 RTL_W8(TxPoll, 0x40); /* set polling bit */ 494 495 tpc->cur_tx++; 496 to = currticks() + TX_TIMEOUT; 497 do { 498 flush_cache((unsigned long)&tpc->TxDescArray[entry], 499 sizeof(struct TxDesc)); 500 } while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit) 501 && (currticks() < to)); /* wait */ 502 503 if (currticks() >= to) { 504 #ifdef DEBUG_RTL8169_TX 505 puts("tx timeout/error\n"); 506 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 507 #endif 508 ret = 0; 509 } else { 510 #ifdef DEBUG_RTL8169_TX 511 puts("tx done\n"); 512 #endif 513 ret = length; 514 } 515 /* Delay to make net console (nc) work properly */ 516 udelay(20); 517 return ret; 518 } 519 520 static void rtl8169_set_rx_mode(struct eth_device *dev) 521 { 522 u32 mc_filter[2]; /* Multicast hash filter */ 523 int rx_mode; 524 u32 tmp = 0; 525 526 #ifdef DEBUG_RTL8169 527 printf ("%s\n", __FUNCTION__); 528 #endif 529 530 /* IFF_ALLMULTI */ 531 /* Too many to filter perfectly -- accept all multicasts. */ 532 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; 533 mc_filter[1] = mc_filter[0] = 0xffffffff; 534 535 tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) & 536 rtl_chip_info[tpc->chipset].RxConfigMask); 537 538 RTL_W32(RxConfig, tmp); 539 RTL_W32(MAR0 + 0, mc_filter[0]); 540 RTL_W32(MAR0 + 4, mc_filter[1]); 541 } 542 543 static void rtl8169_hw_start(struct eth_device *dev) 544 { 545 u32 i; 546 547 #ifdef DEBUG_RTL8169 548 int stime = currticks(); 549 printf ("%s\n", __FUNCTION__); 550 #endif 551 552 #if 0 553 /* Soft reset the chip. */ 554 RTL_W8(ChipCmd, CmdReset); 555 556 /* Check that the chip has finished the reset. */ 557 for (i = 1000; i > 0; i--) { 558 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 559 break; 560 else 561 udelay(10); 562 } 563 #endif 564 565 RTL_W8(Cfg9346, Cfg9346_Unlock); 566 567 /* RTL-8169sb/8110sb or previous version */ 568 if (tpc->chipset <= 5) 569 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 570 571 RTL_W8(EarlyTxThres, EarlyTxThld); 572 573 /* For gigabit rtl8169 */ 574 RTL_W16(RxMaxSize, RxPacketMaxSize); 575 576 /* Set Rx Config register */ 577 i = rtl8169_rx_config | (RTL_R32(RxConfig) & 578 rtl_chip_info[tpc->chipset].RxConfigMask); 579 RTL_W32(RxConfig, i); 580 581 /* Set DMA burst size and Interframe Gap Time */ 582 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | 583 (InterFrameGap << TxInterFrameGapShift)); 584 585 586 tpc->cur_rx = 0; 587 588 RTL_W32(TxDescStartAddrLow, bus_to_phys(tpc->TxDescArray)); 589 RTL_W32(TxDescStartAddrHigh, (unsigned long)0); 590 RTL_W32(RxDescStartAddrLow, bus_to_phys(tpc->RxDescArray)); 591 RTL_W32(RxDescStartAddrHigh, (unsigned long)0); 592 593 /* RTL-8169sc/8110sc or later version */ 594 if (tpc->chipset > 5) 595 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 596 597 RTL_W8(Cfg9346, Cfg9346_Lock); 598 udelay(10); 599 600 RTL_W32(RxMissed, 0); 601 602 rtl8169_set_rx_mode(dev); 603 604 /* no early-rx interrupts */ 605 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); 606 607 #ifdef DEBUG_RTL8169 608 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 609 #endif 610 } 611 612 static void rtl8169_init_ring(struct eth_device *dev) 613 { 614 int i; 615 616 #ifdef DEBUG_RTL8169 617 int stime = currticks(); 618 printf ("%s\n", __FUNCTION__); 619 #endif 620 621 tpc->cur_rx = 0; 622 tpc->cur_tx = 0; 623 tpc->dirty_tx = 0; 624 memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc)); 625 memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc)); 626 627 for (i = 0; i < NUM_TX_DESC; i++) { 628 tpc->Tx_skbuff[i] = &txb[i]; 629 } 630 631 for (i = 0; i < NUM_RX_DESC; i++) { 632 if (i == (NUM_RX_DESC - 1)) 633 tpc->RxDescArray[i].status = 634 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); 635 else 636 tpc->RxDescArray[i].status = 637 cpu_to_le32(OWNbit + RX_BUF_SIZE); 638 639 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE]; 640 tpc->RxDescArray[i].buf_addr = 641 cpu_to_le32(bus_to_phys(tpc->RxBufferRing[i])); 642 flush_cache((unsigned long)tpc->RxBufferRing[i], RX_BUF_SIZE); 643 } 644 645 #ifdef DEBUG_RTL8169 646 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 647 #endif 648 } 649 650 /************************************************************************** 651 RESET - Finish setting up the ethernet interface 652 ***************************************************************************/ 653 static int rtl_reset(struct eth_device *dev, bd_t *bis) 654 { 655 int i; 656 657 #ifdef DEBUG_RTL8169 658 int stime = currticks(); 659 printf ("%s\n", __FUNCTION__); 660 #endif 661 662 tpc->TxDescArrays = tx_ring; 663 /* Tx Desscriptor needs 256 bytes alignment; */ 664 tpc->TxDescArray = (struct TxDesc *) ((unsigned long)(tpc->TxDescArrays + 665 255) & ~255); 666 667 tpc->RxDescArrays = rx_ring; 668 /* Rx Desscriptor needs 256 bytes alignment; */ 669 tpc->RxDescArray = (struct RxDesc *) ((unsigned long)(tpc->RxDescArrays + 670 255) & ~255); 671 672 rtl8169_init_ring(dev); 673 rtl8169_hw_start(dev); 674 /* Construct a perfect filter frame with the mac address as first match 675 * and broadcast for all others */ 676 for (i = 0; i < 192; i++) 677 txb[i] = 0xFF; 678 679 txb[0] = dev->enetaddr[0]; 680 txb[1] = dev->enetaddr[1]; 681 txb[2] = dev->enetaddr[2]; 682 txb[3] = dev->enetaddr[3]; 683 txb[4] = dev->enetaddr[4]; 684 txb[5] = dev->enetaddr[5]; 685 686 #ifdef DEBUG_RTL8169 687 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 688 #endif 689 return 0; 690 } 691 692 /************************************************************************** 693 HALT - Turn off ethernet interface 694 ***************************************************************************/ 695 static void rtl_halt(struct eth_device *dev) 696 { 697 int i; 698 699 #ifdef DEBUG_RTL8169 700 printf ("%s\n", __FUNCTION__); 701 #endif 702 703 ioaddr = dev->iobase; 704 705 /* Stop the chip's Tx and Rx DMA processes. */ 706 RTL_W8(ChipCmd, 0x00); 707 708 /* Disable interrupts by clearing the interrupt mask. */ 709 RTL_W16(IntrMask, 0x0000); 710 711 RTL_W32(RxMissed, 0); 712 713 tpc->TxDescArrays = NULL; 714 tpc->RxDescArrays = NULL; 715 tpc->TxDescArray = NULL; 716 tpc->RxDescArray = NULL; 717 for (i = 0; i < NUM_RX_DESC; i++) { 718 tpc->RxBufferRing[i] = NULL; 719 } 720 } 721 722 /************************************************************************** 723 INIT - Look for an adapter, this routine's visible to the outside 724 ***************************************************************************/ 725 726 #define board_found 1 727 #define valid_link 0 728 static int rtl_init(struct eth_device *dev, bd_t *bis) 729 { 730 static int board_idx = -1; 731 int i, rc; 732 int option = -1, Cap10_100 = 0, Cap1000 = 0; 733 734 #ifdef DEBUG_RTL8169 735 printf ("%s\n", __FUNCTION__); 736 #endif 737 738 ioaddr = dev->iobase; 739 740 board_idx++; 741 742 /* point to private storage */ 743 tpc = &tpx; 744 745 rc = rtl8169_init_board(dev); 746 if (rc) 747 return rc; 748 749 /* Get MAC address. FIXME: read EEPROM */ 750 for (i = 0; i < MAC_ADDR_LEN; i++) 751 dev->enetaddr[i] = RTL_R8(MAC0 + i); 752 753 #ifdef DEBUG_RTL8169 754 printf("chipset = %d\n", tpc->chipset); 755 printf("MAC Address"); 756 for (i = 0; i < MAC_ADDR_LEN; i++) 757 printf(":%02x", dev->enetaddr[i]); 758 putc('\n'); 759 #endif 760 761 #ifdef DEBUG_RTL8169 762 /* Print out some hardware info */ 763 printf("%s: at ioaddr 0x%x\n", dev->name, ioaddr); 764 #endif 765 766 /* if TBI is not endbled */ 767 if (!(RTL_R8(PHYstatus) & TBI_Enable)) { 768 int val = mdio_read(PHY_AUTO_NEGO_REG); 769 770 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx]; 771 /* Force RTL8169 in 10/100/1000 Full/Half mode. */ 772 if (option > 0) { 773 #ifdef DEBUG_RTL8169 774 printf("%s: Force-mode Enabled.\n", dev->name); 775 #endif 776 Cap10_100 = 0, Cap1000 = 0; 777 switch (option) { 778 case _10_Half: 779 Cap10_100 = PHY_Cap_10_Half; 780 Cap1000 = PHY_Cap_Null; 781 break; 782 case _10_Full: 783 Cap10_100 = PHY_Cap_10_Full; 784 Cap1000 = PHY_Cap_Null; 785 break; 786 case _100_Half: 787 Cap10_100 = PHY_Cap_100_Half; 788 Cap1000 = PHY_Cap_Null; 789 break; 790 case _100_Full: 791 Cap10_100 = PHY_Cap_100_Full; 792 Cap1000 = PHY_Cap_Null; 793 break; 794 case _1000_Full: 795 Cap10_100 = PHY_Cap_Null; 796 Cap1000 = PHY_Cap_1000_Full; 797 break; 798 default: 799 break; 800 } 801 mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 802 mdio_write(PHY_1000_CTRL_REG, Cap1000); 803 } else { 804 #ifdef DEBUG_RTL8169 805 printf("%s: Auto-negotiation Enabled.\n", 806 dev->name); 807 #endif 808 /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 809 mdio_write(PHY_AUTO_NEGO_REG, 810 PHY_Cap_10_Half | PHY_Cap_10_Full | 811 PHY_Cap_100_Half | PHY_Cap_100_Full | 812 (val & 0x1F)); 813 814 /* enable 1000 Full Mode */ 815 mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full); 816 817 } 818 819 /* Enable auto-negotiation and restart auto-nigotiation */ 820 mdio_write(PHY_CTRL_REG, 821 PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego); 822 udelay(100); 823 824 /* wait for auto-negotiation process */ 825 for (i = 10000; i > 0; i--) { 826 /* check if auto-negotiation complete */ 827 if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) { 828 udelay(100); 829 option = RTL_R8(PHYstatus); 830 if (option & _1000bpsF) { 831 #ifdef DEBUG_RTL8169 832 printf("%s: 1000Mbps Full-duplex operation.\n", 833 dev->name); 834 #endif 835 } else { 836 #ifdef DEBUG_RTL8169 837 printf("%s: %sMbps %s-duplex operation.\n", 838 dev->name, 839 (option & _100bps) ? "100" : 840 "10", 841 (option & FullDup) ? "Full" : 842 "Half"); 843 #endif 844 } 845 break; 846 } else { 847 udelay(100); 848 } 849 } /* end for-loop to wait for auto-negotiation process */ 850 851 } else { 852 udelay(100); 853 #ifdef DEBUG_RTL8169 854 printf 855 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n", 856 dev->name, 857 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed"); 858 #endif 859 } 860 861 return 1; 862 } 863 864 int rtl8169_initialize(bd_t *bis) 865 { 866 pci_dev_t devno; 867 int card_number = 0; 868 struct eth_device *dev; 869 u32 iobase; 870 int idx=0; 871 872 while(1){ 873 /* Find RTL8169 */ 874 if ((devno = pci_find_devices(supported, idx++)) < 0) 875 break; 876 877 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); 878 iobase &= ~0xf; 879 880 debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); 881 882 dev = (struct eth_device *)malloc(sizeof *dev); 883 if (!dev) { 884 printf("Can not allocate memory of rtl8169\n"); 885 break; 886 } 887 888 memset(dev, 0, sizeof(*dev)); 889 sprintf (dev->name, "RTL8169#%d", card_number); 890 891 dev->priv = (void *) devno; 892 dev->iobase = (int)pci_mem_to_phys(devno, iobase); 893 894 dev->init = rtl_reset; 895 dev->halt = rtl_halt; 896 dev->send = rtl_send; 897 dev->recv = rtl_recv; 898 899 eth_register (dev); 900 901 rtl_init(dev, bis); 902 903 card_number++; 904 } 905 return card_number; 906 } 907