1 /* 2 * rtl8169.c : U-Boot driver for the RealTek RTL8169 3 * 4 * Masami Komiya (mkomiya@sonare.it) 5 * 6 * Most part is taken from r8169.c of etherboot 7 * 8 */ 9 10 /************************************************************************** 11 * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit 12 * Written 2003 by Timothy Legge <tlegge@rogers.com> 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 * 16 * Portions of this code based on: 17 * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver 18 * for Linux kernel 2.4.x. 19 * 20 * Written 2002 ShuChen <shuchen@realtek.com.tw> 21 * See Linux Driver for full information 22 * 23 * Linux Driver Version 1.27a, 10.02.2002 24 * 25 * Thanks to: 26 * Jean Chen of RealTek Semiconductor Corp. for 27 * providing the evaluation NIC used to develop 28 * this driver. RealTek's support for Etherboot 29 * is appreciated. 30 * 31 * REVISION HISTORY: 32 * ================ 33 * 34 * v1.0 11-26-2003 timlegge Initial port of Linux driver 35 * v1.5 01-17-2004 timlegge Initial driver output cleanup 36 * 37 * Indent Options: indent -kr -i8 38 ***************************************************************************/ 39 /* 40 * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk> 41 * Modified to use le32_to_cpu and cpu_to_le32 properly 42 */ 43 #include <common.h> 44 #include <malloc.h> 45 #include <net.h> 46 #include <netdev.h> 47 #include <asm/io.h> 48 #include <pci.h> 49 50 #undef DEBUG_RTL8169 51 #undef DEBUG_RTL8169_TX 52 #undef DEBUG_RTL8169_RX 53 54 #define drv_version "v1.5" 55 #define drv_date "01-17-2004" 56 57 static u32 ioaddr; 58 59 /* Condensed operations for readability. */ 60 #define currticks() get_timer(0) 61 62 /* media options */ 63 #define MAX_UNITS 8 64 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 }; 65 66 /* MAC address length*/ 67 #define MAC_ADDR_LEN 6 68 69 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/ 70 #define MAX_ETH_FRAME_SIZE 1536 71 72 #define TX_FIFO_THRESH 256 /* In bytes */ 73 74 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ 75 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 76 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 77 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ 78 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */ 79 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 80 81 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */ 82 #ifdef CONFIG_SYS_RX_ETH_BUFFER 83 #define NUM_RX_DESC CONFIG_SYS_RX_ETH_BUFFER 84 #else 85 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */ 86 #endif 87 #define RX_BUF_SIZE 1536 /* Rx Buffer size */ 88 #define RX_BUF_LEN 8192 89 90 #define RTL_MIN_IO_SIZE 0x80 91 #define TX_TIMEOUT (6*HZ) 92 93 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */ 94 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) 95 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) 96 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) 97 #define RTL_R8(reg) readb (ioaddr + (reg)) 98 #define RTL_R16(reg) readw (ioaddr + (reg)) 99 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) 100 101 #define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE 102 #define ETH_ALEN MAC_ADDR_LEN 103 #define ETH_ZLEN 60 104 105 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, (pci_addr_t)a) 106 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, (phys_addr_t)a) 107 108 enum RTL8169_registers { 109 MAC0 = 0, /* Ethernet hardware address. */ 110 MAR0 = 8, /* Multicast filter. */ 111 TxDescStartAddrLow = 0x20, 112 TxDescStartAddrHigh = 0x24, 113 TxHDescStartAddrLow = 0x28, 114 TxHDescStartAddrHigh = 0x2c, 115 FLASH = 0x30, 116 ERSR = 0x36, 117 ChipCmd = 0x37, 118 TxPoll = 0x38, 119 IntrMask = 0x3C, 120 IntrStatus = 0x3E, 121 TxConfig = 0x40, 122 RxConfig = 0x44, 123 RxMissed = 0x4C, 124 Cfg9346 = 0x50, 125 Config0 = 0x51, 126 Config1 = 0x52, 127 Config2 = 0x53, 128 Config3 = 0x54, 129 Config4 = 0x55, 130 Config5 = 0x56, 131 MultiIntr = 0x5C, 132 PHYAR = 0x60, 133 TBICSR = 0x64, 134 TBI_ANAR = 0x68, 135 TBI_LPAR = 0x6A, 136 PHYstatus = 0x6C, 137 RxMaxSize = 0xDA, 138 CPlusCmd = 0xE0, 139 RxDescStartAddrLow = 0xE4, 140 RxDescStartAddrHigh = 0xE8, 141 EarlyTxThres = 0xEC, 142 FuncEvent = 0xF0, 143 FuncEventMask = 0xF4, 144 FuncPresetState = 0xF8, 145 FuncForceEvent = 0xFC, 146 }; 147 148 enum RTL8169_register_content { 149 /*InterruptStatusBits */ 150 SYSErr = 0x8000, 151 PCSTimeout = 0x4000, 152 SWInt = 0x0100, 153 TxDescUnavail = 0x80, 154 RxFIFOOver = 0x40, 155 RxUnderrun = 0x20, 156 RxOverflow = 0x10, 157 TxErr = 0x08, 158 TxOK = 0x04, 159 RxErr = 0x02, 160 RxOK = 0x01, 161 162 /*RxStatusDesc */ 163 RxRES = 0x00200000, 164 RxCRC = 0x00080000, 165 RxRUNT = 0x00100000, 166 RxRWT = 0x00400000, 167 168 /*ChipCmdBits */ 169 CmdReset = 0x10, 170 CmdRxEnb = 0x08, 171 CmdTxEnb = 0x04, 172 RxBufEmpty = 0x01, 173 174 /*Cfg9346Bits */ 175 Cfg9346_Lock = 0x00, 176 Cfg9346_Unlock = 0xC0, 177 178 /*rx_mode_bits */ 179 AcceptErr = 0x20, 180 AcceptRunt = 0x10, 181 AcceptBroadcast = 0x08, 182 AcceptMulticast = 0x04, 183 AcceptMyPhys = 0x02, 184 AcceptAllPhys = 0x01, 185 186 /*RxConfigBits */ 187 RxCfgFIFOShift = 13, 188 RxCfgDMAShift = 8, 189 190 /*TxConfigBits */ 191 TxInterFrameGapShift = 24, 192 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 193 194 /*rtl8169_PHYstatus */ 195 TBI_Enable = 0x80, 196 TxFlowCtrl = 0x40, 197 RxFlowCtrl = 0x20, 198 _1000bpsF = 0x10, 199 _100bps = 0x08, 200 _10bps = 0x04, 201 LinkStatus = 0x02, 202 FullDup = 0x01, 203 204 /*GIGABIT_PHY_registers */ 205 PHY_CTRL_REG = 0, 206 PHY_STAT_REG = 1, 207 PHY_AUTO_NEGO_REG = 4, 208 PHY_1000_CTRL_REG = 9, 209 210 /*GIGABIT_PHY_REG_BIT */ 211 PHY_Restart_Auto_Nego = 0x0200, 212 PHY_Enable_Auto_Nego = 0x1000, 213 214 /* PHY_STAT_REG = 1; */ 215 PHY_Auto_Nego_Comp = 0x0020, 216 217 /* PHY_AUTO_NEGO_REG = 4; */ 218 PHY_Cap_10_Half = 0x0020, 219 PHY_Cap_10_Full = 0x0040, 220 PHY_Cap_100_Half = 0x0080, 221 PHY_Cap_100_Full = 0x0100, 222 223 /* PHY_1000_CTRL_REG = 9; */ 224 PHY_Cap_1000_Full = 0x0200, 225 226 PHY_Cap_Null = 0x0, 227 228 /*_MediaType*/ 229 _10_Half = 0x01, 230 _10_Full = 0x02, 231 _100_Half = 0x04, 232 _100_Full = 0x08, 233 _1000_Full = 0x10, 234 235 /*_TBICSRBit*/ 236 TBILinkOK = 0x02000000, 237 }; 238 239 static struct { 240 const char *name; 241 u8 version; /* depend on RTL8169 docs */ 242 u32 RxConfigMask; /* should clear the bits supported by this chip */ 243 } rtl_chip_info[] = { 244 {"RTL-8169", 0x00, 0xff7e1880,}, 245 {"RTL-8169", 0x04, 0xff7e1880,}, 246 {"RTL-8169", 0x00, 0xff7e1880,}, 247 {"RTL-8169s/8110s", 0x02, 0xff7e1880,}, 248 {"RTL-8169s/8110s", 0x04, 0xff7e1880,}, 249 {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,}, 250 {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,}, 251 {"RTL-8168b/8111sb", 0x30, 0xff7e1880,}, 252 {"RTL-8168b/8111sb", 0x38, 0xff7e1880,}, 253 {"RTL-8168d/8111d", 0x28, 0xff7e1880,}, 254 {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,}, 255 {"RTL-8101e", 0x34, 0xff7e1880,}, 256 {"RTL-8100e", 0x32, 0xff7e1880,}, 257 }; 258 259 enum _DescStatusBit { 260 OWNbit = 0x80000000, 261 EORbit = 0x40000000, 262 FSbit = 0x20000000, 263 LSbit = 0x10000000, 264 }; 265 266 struct TxDesc { 267 u32 status; 268 u32 vlan_tag; 269 u32 buf_addr; 270 u32 buf_Haddr; 271 }; 272 273 struct RxDesc { 274 u32 status; 275 u32 vlan_tag; 276 u32 buf_addr; 277 u32 buf_Haddr; 278 }; 279 280 #define RTL8169_DESC_SIZE 16 281 282 #if ARCH_DMA_MINALIGN > 256 283 # define RTL8169_ALIGN ARCH_DMA_MINALIGN 284 #else 285 # define RTL8169_ALIGN 256 286 #endif 287 288 /* 289 * Warn if the cache-line size is larger than the descriptor size. In such 290 * cases the driver will likely fail because the CPU needs to flush the cache 291 * when requeuing RX buffers, therefore descriptors written by the hardware 292 * may be discarded. 293 */ 294 #if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN 295 #warning cache-line size is larger than descriptor size 296 #endif 297 298 /* Define the TX Descriptor */ 299 DEFINE_ALIGN_BUFFER(struct TxDesc, tx_ring, NUM_TX_DESC, RTL8169_ALIGN); 300 301 /* Define the RX Descriptor */ 302 DEFINE_ALIGN_BUFFER(struct RxDesc, rx_ring, NUM_RX_DESC, RTL8169_ALIGN); 303 304 /* 305 * Create a static buffer of size RX_BUF_SZ for each TX Descriptor. All 306 * descriptors point to a part of this buffer. 307 */ 308 DEFINE_ALIGN_BUFFER(u8, txb, NUM_TX_DESC * RX_BUF_SIZE, RTL8169_ALIGN); 309 310 /* 311 * Create a static buffer of size RX_BUF_SZ for each RX Descriptor. All 312 * descriptors point to a part of this buffer. 313 */ 314 DEFINE_ALIGN_BUFFER(u8, rxb, NUM_RX_DESC * RX_BUF_SIZE, RTL8169_ALIGN); 315 316 struct rtl8169_private { 317 void *mmio_addr; /* memory map physical address */ 318 int chipset; 319 unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 320 unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 321 unsigned long dirty_tx; 322 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */ 323 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */ 324 unsigned char *RxBufferRings; /* Index of Rx Buffer */ 325 unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */ 326 unsigned char *Tx_skbuff[NUM_TX_DESC]; 327 } tpx; 328 329 static struct rtl8169_private *tpc; 330 331 static const u16 rtl8169_intr_mask = 332 SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr | 333 TxOK | RxErr | RxOK; 334 static const unsigned int rtl8169_rx_config = 335 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); 336 337 static struct pci_device_id supported[] = { 338 {PCI_VENDOR_ID_REALTEK, 0x8167}, 339 {PCI_VENDOR_ID_REALTEK, 0x8168}, 340 {PCI_VENDOR_ID_REALTEK, 0x8169}, 341 {} 342 }; 343 344 void mdio_write(int RegAddr, int value) 345 { 346 int i; 347 348 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value); 349 udelay(1000); 350 351 for (i = 2000; i > 0; i--) { 352 /* Check if the RTL8169 has completed writing to the specified MII register */ 353 if (!(RTL_R32(PHYAR) & 0x80000000)) { 354 break; 355 } else { 356 udelay(100); 357 } 358 } 359 } 360 361 int mdio_read(int RegAddr) 362 { 363 int i, value = -1; 364 365 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16); 366 udelay(1000); 367 368 for (i = 2000; i > 0; i--) { 369 /* Check if the RTL8169 has completed retrieving data from the specified MII register */ 370 if (RTL_R32(PHYAR) & 0x80000000) { 371 value = (int) (RTL_R32(PHYAR) & 0xFFFF); 372 break; 373 } else { 374 udelay(100); 375 } 376 } 377 return value; 378 } 379 380 static int rtl8169_init_board(struct eth_device *dev) 381 { 382 int i; 383 u32 tmp; 384 385 #ifdef DEBUG_RTL8169 386 printf ("%s\n", __FUNCTION__); 387 #endif 388 ioaddr = dev->iobase; 389 390 /* Soft reset the chip. */ 391 RTL_W8(ChipCmd, CmdReset); 392 393 /* Check that the chip has finished the reset. */ 394 for (i = 1000; i > 0; i--) 395 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 396 break; 397 else 398 udelay(10); 399 400 /* identify chip attached to board */ 401 tmp = RTL_R32(TxConfig); 402 tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24; 403 404 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){ 405 if (tmp == rtl_chip_info[i].version) { 406 tpc->chipset = i; 407 goto match; 408 } 409 } 410 411 /* if unknown chip, assume array element #0, original RTL-8169 in this case */ 412 printf("PCI device %s: unknown chip version, assuming RTL-8169\n", dev->name); 413 printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig)); 414 tpc->chipset = 0; 415 416 match: 417 return 0; 418 } 419 420 /* 421 * Cache maintenance functions. These are simple wrappers around the more 422 * general purpose flush_cache() and invalidate_dcache_range() functions. 423 */ 424 425 static void rtl_inval_rx_desc(struct RxDesc *desc) 426 { 427 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); 428 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN); 429 430 invalidate_dcache_range(start, end); 431 } 432 433 static void rtl_flush_rx_desc(struct RxDesc *desc) 434 { 435 flush_cache((unsigned long)desc, sizeof(*desc)); 436 } 437 438 static void rtl_inval_tx_desc(struct TxDesc *desc) 439 { 440 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); 441 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN); 442 443 invalidate_dcache_range(start, end); 444 } 445 446 static void rtl_flush_tx_desc(struct TxDesc *desc) 447 { 448 flush_cache((unsigned long)desc, sizeof(*desc)); 449 } 450 451 static void rtl_inval_buffer(void *buf, size_t size) 452 { 453 unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1); 454 unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN); 455 456 invalidate_dcache_range(start, end); 457 } 458 459 static void rtl_flush_buffer(void *buf, size_t size) 460 { 461 flush_cache((unsigned long)buf, size); 462 } 463 464 /************************************************************************** 465 RECV - Receive a frame 466 ***************************************************************************/ 467 static int rtl_recv(struct eth_device *dev) 468 { 469 /* return true if there's an ethernet packet ready to read */ 470 /* nic->packet should contain data on return */ 471 /* nic->packetlen should contain length of data */ 472 int cur_rx; 473 int length = 0; 474 475 #ifdef DEBUG_RTL8169_RX 476 printf ("%s\n", __FUNCTION__); 477 #endif 478 ioaddr = dev->iobase; 479 480 cur_rx = tpc->cur_rx; 481 482 rtl_inval_rx_desc(&tpc->RxDescArray[cur_rx]); 483 484 if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) { 485 if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) { 486 unsigned char rxdata[RX_BUF_LEN]; 487 length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx]. 488 status) & 0x00001FFF) - 4; 489 490 rtl_inval_buffer(tpc->RxBufferRing[cur_rx], length); 491 memcpy(rxdata, tpc->RxBufferRing[cur_rx], length); 492 493 if (cur_rx == NUM_RX_DESC - 1) 494 tpc->RxDescArray[cur_rx].status = 495 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); 496 else 497 tpc->RxDescArray[cur_rx].status = 498 cpu_to_le32(OWNbit + RX_BUF_SIZE); 499 tpc->RxDescArray[cur_rx].buf_addr = 500 cpu_to_le32(bus_to_phys(tpc->RxBufferRing[cur_rx])); 501 rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]); 502 503 NetReceive(rxdata, length); 504 } else { 505 puts("Error Rx"); 506 } 507 cur_rx = (cur_rx + 1) % NUM_RX_DESC; 508 tpc->cur_rx = cur_rx; 509 return 1; 510 511 } else { 512 ushort sts = RTL_R8(IntrStatus); 513 RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr)); 514 udelay(100); /* wait */ 515 } 516 tpc->cur_rx = cur_rx; 517 return (0); /* initially as this is called to flush the input */ 518 } 519 520 #define HZ 1000 521 /************************************************************************** 522 SEND - Transmit a frame 523 ***************************************************************************/ 524 static int rtl_send(struct eth_device *dev, void *packet, int length) 525 { 526 /* send the packet to destination */ 527 528 u32 to; 529 u8 *ptxb; 530 int entry = tpc->cur_tx % NUM_TX_DESC; 531 u32 len = length; 532 int ret; 533 534 #ifdef DEBUG_RTL8169_TX 535 int stime = currticks(); 536 printf ("%s\n", __FUNCTION__); 537 printf("sending %d bytes\n", len); 538 #endif 539 540 ioaddr = dev->iobase; 541 542 /* point to the current txb incase multiple tx_rings are used */ 543 ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE]; 544 memcpy(ptxb, (char *)packet, (int)length); 545 rtl_flush_buffer(ptxb, length); 546 547 while (len < ETH_ZLEN) 548 ptxb[len++] = '\0'; 549 550 tpc->TxDescArray[entry].buf_Haddr = 0; 551 tpc->TxDescArray[entry].buf_addr = cpu_to_le32(bus_to_phys(ptxb)); 552 if (entry != (NUM_TX_DESC - 1)) { 553 tpc->TxDescArray[entry].status = 554 cpu_to_le32((OWNbit | FSbit | LSbit) | 555 ((len > ETH_ZLEN) ? len : ETH_ZLEN)); 556 } else { 557 tpc->TxDescArray[entry].status = 558 cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) | 559 ((len > ETH_ZLEN) ? len : ETH_ZLEN)); 560 } 561 rtl_flush_tx_desc(&tpc->TxDescArray[entry]); 562 RTL_W8(TxPoll, 0x40); /* set polling bit */ 563 564 tpc->cur_tx++; 565 to = currticks() + TX_TIMEOUT; 566 do { 567 rtl_inval_tx_desc(&tpc->TxDescArray[entry]); 568 } while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit) 569 && (currticks() < to)); /* wait */ 570 571 if (currticks() >= to) { 572 #ifdef DEBUG_RTL8169_TX 573 puts("tx timeout/error\n"); 574 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 575 #endif 576 ret = 0; 577 } else { 578 #ifdef DEBUG_RTL8169_TX 579 puts("tx done\n"); 580 #endif 581 ret = length; 582 } 583 /* Delay to make net console (nc) work properly */ 584 udelay(20); 585 return ret; 586 } 587 588 static void rtl8169_set_rx_mode(struct eth_device *dev) 589 { 590 u32 mc_filter[2]; /* Multicast hash filter */ 591 int rx_mode; 592 u32 tmp = 0; 593 594 #ifdef DEBUG_RTL8169 595 printf ("%s\n", __FUNCTION__); 596 #endif 597 598 /* IFF_ALLMULTI */ 599 /* Too many to filter perfectly -- accept all multicasts. */ 600 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; 601 mc_filter[1] = mc_filter[0] = 0xffffffff; 602 603 tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) & 604 rtl_chip_info[tpc->chipset].RxConfigMask); 605 606 RTL_W32(RxConfig, tmp); 607 RTL_W32(MAR0 + 0, mc_filter[0]); 608 RTL_W32(MAR0 + 4, mc_filter[1]); 609 } 610 611 static void rtl8169_hw_start(struct eth_device *dev) 612 { 613 u32 i; 614 615 #ifdef DEBUG_RTL8169 616 int stime = currticks(); 617 printf ("%s\n", __FUNCTION__); 618 #endif 619 620 #if 0 621 /* Soft reset the chip. */ 622 RTL_W8(ChipCmd, CmdReset); 623 624 /* Check that the chip has finished the reset. */ 625 for (i = 1000; i > 0; i--) { 626 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 627 break; 628 else 629 udelay(10); 630 } 631 #endif 632 633 RTL_W8(Cfg9346, Cfg9346_Unlock); 634 635 /* RTL-8169sb/8110sb or previous version */ 636 if (tpc->chipset <= 5) 637 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 638 639 RTL_W8(EarlyTxThres, EarlyTxThld); 640 641 /* For gigabit rtl8169 */ 642 RTL_W16(RxMaxSize, RxPacketMaxSize); 643 644 /* Set Rx Config register */ 645 i = rtl8169_rx_config | (RTL_R32(RxConfig) & 646 rtl_chip_info[tpc->chipset].RxConfigMask); 647 RTL_W32(RxConfig, i); 648 649 /* Set DMA burst size and Interframe Gap Time */ 650 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | 651 (InterFrameGap << TxInterFrameGapShift)); 652 653 654 tpc->cur_rx = 0; 655 656 RTL_W32(TxDescStartAddrLow, bus_to_phys(tpc->TxDescArray)); 657 RTL_W32(TxDescStartAddrHigh, (unsigned long)0); 658 RTL_W32(RxDescStartAddrLow, bus_to_phys(tpc->RxDescArray)); 659 RTL_W32(RxDescStartAddrHigh, (unsigned long)0); 660 661 /* RTL-8169sc/8110sc or later version */ 662 if (tpc->chipset > 5) 663 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 664 665 RTL_W8(Cfg9346, Cfg9346_Lock); 666 udelay(10); 667 668 RTL_W32(RxMissed, 0); 669 670 rtl8169_set_rx_mode(dev); 671 672 /* no early-rx interrupts */ 673 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); 674 675 #ifdef DEBUG_RTL8169 676 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 677 #endif 678 } 679 680 static void rtl8169_init_ring(struct eth_device *dev) 681 { 682 int i; 683 684 #ifdef DEBUG_RTL8169 685 int stime = currticks(); 686 printf ("%s\n", __FUNCTION__); 687 #endif 688 689 tpc->cur_rx = 0; 690 tpc->cur_tx = 0; 691 tpc->dirty_tx = 0; 692 memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc)); 693 memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc)); 694 695 for (i = 0; i < NUM_TX_DESC; i++) { 696 tpc->Tx_skbuff[i] = &txb[i]; 697 } 698 699 for (i = 0; i < NUM_RX_DESC; i++) { 700 if (i == (NUM_RX_DESC - 1)) 701 tpc->RxDescArray[i].status = 702 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); 703 else 704 tpc->RxDescArray[i].status = 705 cpu_to_le32(OWNbit + RX_BUF_SIZE); 706 707 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE]; 708 tpc->RxDescArray[i].buf_addr = 709 cpu_to_le32(bus_to_phys(tpc->RxBufferRing[i])); 710 rtl_flush_rx_desc(&tpc->RxDescArray[i]); 711 } 712 713 #ifdef DEBUG_RTL8169 714 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 715 #endif 716 } 717 718 /************************************************************************** 719 RESET - Finish setting up the ethernet interface 720 ***************************************************************************/ 721 static int rtl_reset(struct eth_device *dev, bd_t *bis) 722 { 723 int i; 724 725 #ifdef DEBUG_RTL8169 726 int stime = currticks(); 727 printf ("%s\n", __FUNCTION__); 728 #endif 729 730 rtl8169_init_ring(dev); 731 rtl8169_hw_start(dev); 732 /* Construct a perfect filter frame with the mac address as first match 733 * and broadcast for all others */ 734 for (i = 0; i < 192; i++) 735 txb[i] = 0xFF; 736 737 txb[0] = dev->enetaddr[0]; 738 txb[1] = dev->enetaddr[1]; 739 txb[2] = dev->enetaddr[2]; 740 txb[3] = dev->enetaddr[3]; 741 txb[4] = dev->enetaddr[4]; 742 txb[5] = dev->enetaddr[5]; 743 744 #ifdef DEBUG_RTL8169 745 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 746 #endif 747 return 0; 748 } 749 750 /************************************************************************** 751 HALT - Turn off ethernet interface 752 ***************************************************************************/ 753 static void rtl_halt(struct eth_device *dev) 754 { 755 int i; 756 757 #ifdef DEBUG_RTL8169 758 printf ("%s\n", __FUNCTION__); 759 #endif 760 761 ioaddr = dev->iobase; 762 763 /* Stop the chip's Tx and Rx DMA processes. */ 764 RTL_W8(ChipCmd, 0x00); 765 766 /* Disable interrupts by clearing the interrupt mask. */ 767 RTL_W16(IntrMask, 0x0000); 768 769 RTL_W32(RxMissed, 0); 770 771 for (i = 0; i < NUM_RX_DESC; i++) { 772 tpc->RxBufferRing[i] = NULL; 773 } 774 } 775 776 /************************************************************************** 777 INIT - Look for an adapter, this routine's visible to the outside 778 ***************************************************************************/ 779 780 #define board_found 1 781 #define valid_link 0 782 static int rtl_init(struct eth_device *dev, bd_t *bis) 783 { 784 static int board_idx = -1; 785 int i, rc; 786 int option = -1, Cap10_100 = 0, Cap1000 = 0; 787 788 #ifdef DEBUG_RTL8169 789 printf ("%s\n", __FUNCTION__); 790 #endif 791 792 ioaddr = dev->iobase; 793 794 board_idx++; 795 796 /* point to private storage */ 797 tpc = &tpx; 798 799 rc = rtl8169_init_board(dev); 800 if (rc) 801 return rc; 802 803 /* Get MAC address. FIXME: read EEPROM */ 804 for (i = 0; i < MAC_ADDR_LEN; i++) 805 dev->enetaddr[i] = RTL_R8(MAC0 + i); 806 807 #ifdef DEBUG_RTL8169 808 printf("chipset = %d\n", tpc->chipset); 809 printf("MAC Address"); 810 for (i = 0; i < MAC_ADDR_LEN; i++) 811 printf(":%02x", dev->enetaddr[i]); 812 putc('\n'); 813 #endif 814 815 #ifdef DEBUG_RTL8169 816 /* Print out some hardware info */ 817 printf("%s: at ioaddr 0x%x\n", dev->name, ioaddr); 818 #endif 819 820 /* if TBI is not endbled */ 821 if (!(RTL_R8(PHYstatus) & TBI_Enable)) { 822 int val = mdio_read(PHY_AUTO_NEGO_REG); 823 824 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx]; 825 /* Force RTL8169 in 10/100/1000 Full/Half mode. */ 826 if (option > 0) { 827 #ifdef DEBUG_RTL8169 828 printf("%s: Force-mode Enabled.\n", dev->name); 829 #endif 830 Cap10_100 = 0, Cap1000 = 0; 831 switch (option) { 832 case _10_Half: 833 Cap10_100 = PHY_Cap_10_Half; 834 Cap1000 = PHY_Cap_Null; 835 break; 836 case _10_Full: 837 Cap10_100 = PHY_Cap_10_Full; 838 Cap1000 = PHY_Cap_Null; 839 break; 840 case _100_Half: 841 Cap10_100 = PHY_Cap_100_Half; 842 Cap1000 = PHY_Cap_Null; 843 break; 844 case _100_Full: 845 Cap10_100 = PHY_Cap_100_Full; 846 Cap1000 = PHY_Cap_Null; 847 break; 848 case _1000_Full: 849 Cap10_100 = PHY_Cap_Null; 850 Cap1000 = PHY_Cap_1000_Full; 851 break; 852 default: 853 break; 854 } 855 mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 856 mdio_write(PHY_1000_CTRL_REG, Cap1000); 857 } else { 858 #ifdef DEBUG_RTL8169 859 printf("%s: Auto-negotiation Enabled.\n", 860 dev->name); 861 #endif 862 /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 863 mdio_write(PHY_AUTO_NEGO_REG, 864 PHY_Cap_10_Half | PHY_Cap_10_Full | 865 PHY_Cap_100_Half | PHY_Cap_100_Full | 866 (val & 0x1F)); 867 868 /* enable 1000 Full Mode */ 869 mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full); 870 871 } 872 873 /* Enable auto-negotiation and restart auto-nigotiation */ 874 mdio_write(PHY_CTRL_REG, 875 PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego); 876 udelay(100); 877 878 /* wait for auto-negotiation process */ 879 for (i = 10000; i > 0; i--) { 880 /* check if auto-negotiation complete */ 881 if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) { 882 udelay(100); 883 option = RTL_R8(PHYstatus); 884 if (option & _1000bpsF) { 885 #ifdef DEBUG_RTL8169 886 printf("%s: 1000Mbps Full-duplex operation.\n", 887 dev->name); 888 #endif 889 } else { 890 #ifdef DEBUG_RTL8169 891 printf("%s: %sMbps %s-duplex operation.\n", 892 dev->name, 893 (option & _100bps) ? "100" : 894 "10", 895 (option & FullDup) ? "Full" : 896 "Half"); 897 #endif 898 } 899 break; 900 } else { 901 udelay(100); 902 } 903 } /* end for-loop to wait for auto-negotiation process */ 904 905 } else { 906 udelay(100); 907 #ifdef DEBUG_RTL8169 908 printf 909 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n", 910 dev->name, 911 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed"); 912 #endif 913 } 914 915 tpc->TxDescArray = tx_ring; 916 tpc->RxDescArray = rx_ring; 917 918 return 1; 919 } 920 921 int rtl8169_initialize(bd_t *bis) 922 { 923 pci_dev_t devno; 924 int card_number = 0; 925 struct eth_device *dev; 926 u32 iobase; 927 int idx=0; 928 929 while(1){ 930 unsigned int region; 931 u16 device; 932 933 /* Find RTL8169 */ 934 if ((devno = pci_find_devices(supported, idx++)) < 0) 935 break; 936 937 pci_read_config_word(devno, PCI_DEVICE_ID, &device); 938 switch (device) { 939 case 0x8168: 940 region = 2; 941 break; 942 943 default: 944 region = 1; 945 break; 946 } 947 948 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase); 949 iobase &= ~0xf; 950 951 debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); 952 953 dev = (struct eth_device *)malloc(sizeof *dev); 954 if (!dev) { 955 printf("Can not allocate memory of rtl8169\n"); 956 break; 957 } 958 959 memset(dev, 0, sizeof(*dev)); 960 sprintf (dev->name, "RTL8169#%d", card_number); 961 962 dev->priv = (void *) devno; 963 dev->iobase = (int)pci_mem_to_phys(devno, iobase); 964 965 dev->init = rtl_reset; 966 dev->halt = rtl_halt; 967 dev->send = rtl_send; 968 dev->recv = rtl_recv; 969 970 eth_register (dev); 971 972 rtl_init(dev, bis); 973 974 card_number++; 975 } 976 return card_number; 977 } 978