1 /* 2 * rtl8169.c : U-Boot driver for the RealTek RTL8169 3 * 4 * Masami Komiya (mkomiya@sonare.it) 5 * 6 * Most part is taken from r8169.c of etherboot 7 * 8 */ 9 10 /************************************************************************** 11 * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit 12 * Written 2003 by Timothy Legge <tlegge@rogers.com> 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 * 16 * Portions of this code based on: 17 * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver 18 * for Linux kernel 2.4.x. 19 * 20 * Written 2002 ShuChen <shuchen@realtek.com.tw> 21 * See Linux Driver for full information 22 * 23 * Linux Driver Version 1.27a, 10.02.2002 24 * 25 * Thanks to: 26 * Jean Chen of RealTek Semiconductor Corp. for 27 * providing the evaluation NIC used to develop 28 * this driver. RealTek's support for Etherboot 29 * is appreciated. 30 * 31 * REVISION HISTORY: 32 * ================ 33 * 34 * v1.0 11-26-2003 timlegge Initial port of Linux driver 35 * v1.5 01-17-2004 timlegge Initial driver output cleanup 36 * 37 * Indent Options: indent -kr -i8 38 ***************************************************************************/ 39 /* 40 * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk> 41 * Modified to use le32_to_cpu and cpu_to_le32 properly 42 */ 43 #include <common.h> 44 #include <errno.h> 45 #include <malloc.h> 46 #include <net.h> 47 #include <netdev.h> 48 #include <asm/io.h> 49 #include <pci.h> 50 51 #undef DEBUG_RTL8169 52 #undef DEBUG_RTL8169_TX 53 #undef DEBUG_RTL8169_RX 54 55 #define drv_version "v1.5" 56 #define drv_date "01-17-2004" 57 58 static u32 ioaddr; 59 60 /* Condensed operations for readability. */ 61 #define currticks() get_timer(0) 62 63 /* media options */ 64 #define MAX_UNITS 8 65 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 }; 66 67 /* MAC address length*/ 68 #define MAC_ADDR_LEN 6 69 70 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/ 71 #define MAX_ETH_FRAME_SIZE 1536 72 73 #define TX_FIFO_THRESH 256 /* In bytes */ 74 75 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ 76 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 77 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 78 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ 79 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */ 80 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 81 82 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */ 83 #ifdef CONFIG_SYS_RX_ETH_BUFFER 84 #define NUM_RX_DESC CONFIG_SYS_RX_ETH_BUFFER 85 #else 86 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */ 87 #endif 88 #define RX_BUF_SIZE 1536 /* Rx Buffer size */ 89 #define RX_BUF_LEN 8192 90 91 #define RTL_MIN_IO_SIZE 0x80 92 #define TX_TIMEOUT (6*HZ) 93 94 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */ 95 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) 96 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) 97 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) 98 #define RTL_R8(reg) readb (ioaddr + (reg)) 99 #define RTL_R16(reg) readw (ioaddr + (reg)) 100 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) 101 102 #define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE 103 #define ETH_ALEN MAC_ADDR_LEN 104 #define ETH_ZLEN 60 105 106 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, (pci_addr_t)a) 107 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, (phys_addr_t)a) 108 109 enum RTL8169_registers { 110 MAC0 = 0, /* Ethernet hardware address. */ 111 MAR0 = 8, /* Multicast filter. */ 112 TxDescStartAddrLow = 0x20, 113 TxDescStartAddrHigh = 0x24, 114 TxHDescStartAddrLow = 0x28, 115 TxHDescStartAddrHigh = 0x2c, 116 FLASH = 0x30, 117 ERSR = 0x36, 118 ChipCmd = 0x37, 119 TxPoll = 0x38, 120 IntrMask = 0x3C, 121 IntrStatus = 0x3E, 122 TxConfig = 0x40, 123 RxConfig = 0x44, 124 RxMissed = 0x4C, 125 Cfg9346 = 0x50, 126 Config0 = 0x51, 127 Config1 = 0x52, 128 Config2 = 0x53, 129 Config3 = 0x54, 130 Config4 = 0x55, 131 Config5 = 0x56, 132 MultiIntr = 0x5C, 133 PHYAR = 0x60, 134 TBICSR = 0x64, 135 TBI_ANAR = 0x68, 136 TBI_LPAR = 0x6A, 137 PHYstatus = 0x6C, 138 RxMaxSize = 0xDA, 139 CPlusCmd = 0xE0, 140 RxDescStartAddrLow = 0xE4, 141 RxDescStartAddrHigh = 0xE8, 142 EarlyTxThres = 0xEC, 143 FuncEvent = 0xF0, 144 FuncEventMask = 0xF4, 145 FuncPresetState = 0xF8, 146 FuncForceEvent = 0xFC, 147 }; 148 149 enum RTL8169_register_content { 150 /*InterruptStatusBits */ 151 SYSErr = 0x8000, 152 PCSTimeout = 0x4000, 153 SWInt = 0x0100, 154 TxDescUnavail = 0x80, 155 RxFIFOOver = 0x40, 156 RxUnderrun = 0x20, 157 RxOverflow = 0x10, 158 TxErr = 0x08, 159 TxOK = 0x04, 160 RxErr = 0x02, 161 RxOK = 0x01, 162 163 /*RxStatusDesc */ 164 RxRES = 0x00200000, 165 RxCRC = 0x00080000, 166 RxRUNT = 0x00100000, 167 RxRWT = 0x00400000, 168 169 /*ChipCmdBits */ 170 CmdReset = 0x10, 171 CmdRxEnb = 0x08, 172 CmdTxEnb = 0x04, 173 RxBufEmpty = 0x01, 174 175 /*Cfg9346Bits */ 176 Cfg9346_Lock = 0x00, 177 Cfg9346_Unlock = 0xC0, 178 179 /*rx_mode_bits */ 180 AcceptErr = 0x20, 181 AcceptRunt = 0x10, 182 AcceptBroadcast = 0x08, 183 AcceptMulticast = 0x04, 184 AcceptMyPhys = 0x02, 185 AcceptAllPhys = 0x01, 186 187 /*RxConfigBits */ 188 RxCfgFIFOShift = 13, 189 RxCfgDMAShift = 8, 190 191 /*TxConfigBits */ 192 TxInterFrameGapShift = 24, 193 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 194 195 /*rtl8169_PHYstatus */ 196 TBI_Enable = 0x80, 197 TxFlowCtrl = 0x40, 198 RxFlowCtrl = 0x20, 199 _1000bpsF = 0x10, 200 _100bps = 0x08, 201 _10bps = 0x04, 202 LinkStatus = 0x02, 203 FullDup = 0x01, 204 205 /*GIGABIT_PHY_registers */ 206 PHY_CTRL_REG = 0, 207 PHY_STAT_REG = 1, 208 PHY_AUTO_NEGO_REG = 4, 209 PHY_1000_CTRL_REG = 9, 210 211 /*GIGABIT_PHY_REG_BIT */ 212 PHY_Restart_Auto_Nego = 0x0200, 213 PHY_Enable_Auto_Nego = 0x1000, 214 215 /* PHY_STAT_REG = 1; */ 216 PHY_Auto_Nego_Comp = 0x0020, 217 218 /* PHY_AUTO_NEGO_REG = 4; */ 219 PHY_Cap_10_Half = 0x0020, 220 PHY_Cap_10_Full = 0x0040, 221 PHY_Cap_100_Half = 0x0080, 222 PHY_Cap_100_Full = 0x0100, 223 224 /* PHY_1000_CTRL_REG = 9; */ 225 PHY_Cap_1000_Full = 0x0200, 226 227 PHY_Cap_Null = 0x0, 228 229 /*_MediaType*/ 230 _10_Half = 0x01, 231 _10_Full = 0x02, 232 _100_Half = 0x04, 233 _100_Full = 0x08, 234 _1000_Full = 0x10, 235 236 /*_TBICSRBit*/ 237 TBILinkOK = 0x02000000, 238 }; 239 240 static struct { 241 const char *name; 242 u8 version; /* depend on RTL8169 docs */ 243 u32 RxConfigMask; /* should clear the bits supported by this chip */ 244 } rtl_chip_info[] = { 245 {"RTL-8169", 0x00, 0xff7e1880,}, 246 {"RTL-8169", 0x04, 0xff7e1880,}, 247 {"RTL-8169", 0x00, 0xff7e1880,}, 248 {"RTL-8169s/8110s", 0x02, 0xff7e1880,}, 249 {"RTL-8169s/8110s", 0x04, 0xff7e1880,}, 250 {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,}, 251 {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,}, 252 {"RTL-8168b/8111sb", 0x30, 0xff7e1880,}, 253 {"RTL-8168b/8111sb", 0x38, 0xff7e1880,}, 254 {"RTL-8168d/8111d", 0x28, 0xff7e1880,}, 255 {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,}, 256 {"RTL-8101e", 0x34, 0xff7e1880,}, 257 {"RTL-8100e", 0x32, 0xff7e1880,}, 258 }; 259 260 enum _DescStatusBit { 261 OWNbit = 0x80000000, 262 EORbit = 0x40000000, 263 FSbit = 0x20000000, 264 LSbit = 0x10000000, 265 }; 266 267 struct TxDesc { 268 u32 status; 269 u32 vlan_tag; 270 u32 buf_addr; 271 u32 buf_Haddr; 272 }; 273 274 struct RxDesc { 275 u32 status; 276 u32 vlan_tag; 277 u32 buf_addr; 278 u32 buf_Haddr; 279 }; 280 281 #define RTL8169_DESC_SIZE 16 282 283 #if ARCH_DMA_MINALIGN > 256 284 # define RTL8169_ALIGN ARCH_DMA_MINALIGN 285 #else 286 # define RTL8169_ALIGN 256 287 #endif 288 289 /* 290 * Warn if the cache-line size is larger than the descriptor size. In such 291 * cases the driver will likely fail because the CPU needs to flush the cache 292 * when requeuing RX buffers, therefore descriptors written by the hardware 293 * may be discarded. 294 * 295 * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause 296 * the driver to allocate descriptors from a pool of non-cached memory. 297 */ 298 #if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN 299 #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && !defined(CONFIG_SYS_DCACHE_OFF) 300 #warning cache-line size is larger than descriptor size 301 #endif 302 #endif 303 304 /* 305 * Create a static buffer of size RX_BUF_SZ for each TX Descriptor. All 306 * descriptors point to a part of this buffer. 307 */ 308 DEFINE_ALIGN_BUFFER(u8, txb, NUM_TX_DESC * RX_BUF_SIZE, RTL8169_ALIGN); 309 310 /* 311 * Create a static buffer of size RX_BUF_SZ for each RX Descriptor. All 312 * descriptors point to a part of this buffer. 313 */ 314 DEFINE_ALIGN_BUFFER(u8, rxb, NUM_RX_DESC * RX_BUF_SIZE, RTL8169_ALIGN); 315 316 struct rtl8169_private { 317 void *mmio_addr; /* memory map physical address */ 318 int chipset; 319 unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 320 unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 321 unsigned long dirty_tx; 322 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */ 323 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */ 324 unsigned char *RxBufferRings; /* Index of Rx Buffer */ 325 unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */ 326 unsigned char *Tx_skbuff[NUM_TX_DESC]; 327 } tpx; 328 329 static struct rtl8169_private *tpc; 330 331 static const u16 rtl8169_intr_mask = 332 SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr | 333 TxOK | RxErr | RxOK; 334 static const unsigned int rtl8169_rx_config = 335 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); 336 337 static struct pci_device_id supported[] = { 338 {PCI_VENDOR_ID_REALTEK, 0x8167}, 339 {PCI_VENDOR_ID_REALTEK, 0x8168}, 340 {PCI_VENDOR_ID_REALTEK, 0x8169}, 341 {} 342 }; 343 344 void mdio_write(int RegAddr, int value) 345 { 346 int i; 347 348 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value); 349 udelay(1000); 350 351 for (i = 2000; i > 0; i--) { 352 /* Check if the RTL8169 has completed writing to the specified MII register */ 353 if (!(RTL_R32(PHYAR) & 0x80000000)) { 354 break; 355 } else { 356 udelay(100); 357 } 358 } 359 } 360 361 int mdio_read(int RegAddr) 362 { 363 int i, value = -1; 364 365 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16); 366 udelay(1000); 367 368 for (i = 2000; i > 0; i--) { 369 /* Check if the RTL8169 has completed retrieving data from the specified MII register */ 370 if (RTL_R32(PHYAR) & 0x80000000) { 371 value = (int) (RTL_R32(PHYAR) & 0xFFFF); 372 break; 373 } else { 374 udelay(100); 375 } 376 } 377 return value; 378 } 379 380 static int rtl8169_init_board(struct eth_device *dev) 381 { 382 int i; 383 u32 tmp; 384 385 #ifdef DEBUG_RTL8169 386 printf ("%s\n", __FUNCTION__); 387 #endif 388 ioaddr = dev->iobase; 389 390 /* Soft reset the chip. */ 391 RTL_W8(ChipCmd, CmdReset); 392 393 /* Check that the chip has finished the reset. */ 394 for (i = 1000; i > 0; i--) 395 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 396 break; 397 else 398 udelay(10); 399 400 /* identify chip attached to board */ 401 tmp = RTL_R32(TxConfig); 402 tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24; 403 404 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){ 405 if (tmp == rtl_chip_info[i].version) { 406 tpc->chipset = i; 407 goto match; 408 } 409 } 410 411 /* if unknown chip, assume array element #0, original RTL-8169 in this case */ 412 printf("PCI device %s: unknown chip version, assuming RTL-8169\n", dev->name); 413 printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig)); 414 tpc->chipset = 0; 415 416 match: 417 return 0; 418 } 419 420 /* 421 * TX and RX descriptors are 16 bytes. This causes problems with the cache 422 * maintenance on CPUs where the cache-line size exceeds the size of these 423 * descriptors. What will happen is that when the driver receives a packet 424 * it will be immediately requeued for the hardware to reuse. The CPU will 425 * therefore need to flush the cache-line containing the descriptor, which 426 * will cause all other descriptors in the same cache-line to be flushed 427 * along with it. If one of those descriptors had been written to by the 428 * device those changes (and the associated packet) will be lost. 429 * 430 * To work around this, we make use of non-cached memory if available. If 431 * descriptors are mapped uncached there's no need to manually flush them 432 * or invalidate them. 433 * 434 * Note that this only applies to descriptors. The packet data buffers do 435 * not have the same constraints since they are 1536 bytes large, so they 436 * are unlikely to share cache-lines. 437 */ 438 static void *rtl_alloc_descs(unsigned int num) 439 { 440 size_t size = num * RTL8169_DESC_SIZE; 441 442 #ifdef CONFIG_SYS_NONCACHED_MEMORY 443 return (void *)noncached_alloc(size, RTL8169_ALIGN); 444 #else 445 return memalign(RTL8169_ALIGN, size); 446 #endif 447 } 448 449 /* 450 * Cache maintenance functions. These are simple wrappers around the more 451 * general purpose flush_cache() and invalidate_dcache_range() functions. 452 */ 453 454 static void rtl_inval_rx_desc(struct RxDesc *desc) 455 { 456 #ifndef CONFIG_SYS_NONCACHED_MEMORY 457 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); 458 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN); 459 460 invalidate_dcache_range(start, end); 461 #endif 462 } 463 464 static void rtl_flush_rx_desc(struct RxDesc *desc) 465 { 466 #ifndef CONFIG_SYS_NONCACHED_MEMORY 467 flush_cache((unsigned long)desc, sizeof(*desc)); 468 #endif 469 } 470 471 static void rtl_inval_tx_desc(struct TxDesc *desc) 472 { 473 #ifndef CONFIG_SYS_NONCACHED_MEMORY 474 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); 475 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN); 476 477 invalidate_dcache_range(start, end); 478 #endif 479 } 480 481 static void rtl_flush_tx_desc(struct TxDesc *desc) 482 { 483 #ifndef CONFIG_SYS_NONCACHED_MEMORY 484 flush_cache((unsigned long)desc, sizeof(*desc)); 485 #endif 486 } 487 488 static void rtl_inval_buffer(void *buf, size_t size) 489 { 490 unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1); 491 unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN); 492 493 invalidate_dcache_range(start, end); 494 } 495 496 static void rtl_flush_buffer(void *buf, size_t size) 497 { 498 flush_cache((unsigned long)buf, size); 499 } 500 501 /************************************************************************** 502 RECV - Receive a frame 503 ***************************************************************************/ 504 static int rtl_recv(struct eth_device *dev) 505 { 506 /* return true if there's an ethernet packet ready to read */ 507 /* nic->packet should contain data on return */ 508 /* nic->packetlen should contain length of data */ 509 int cur_rx; 510 int length = 0; 511 512 #ifdef DEBUG_RTL8169_RX 513 printf ("%s\n", __FUNCTION__); 514 #endif 515 ioaddr = dev->iobase; 516 517 cur_rx = tpc->cur_rx; 518 519 rtl_inval_rx_desc(&tpc->RxDescArray[cur_rx]); 520 521 if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) { 522 if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) { 523 unsigned char rxdata[RX_BUF_LEN]; 524 length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx]. 525 status) & 0x00001FFF) - 4; 526 527 rtl_inval_buffer(tpc->RxBufferRing[cur_rx], length); 528 memcpy(rxdata, tpc->RxBufferRing[cur_rx], length); 529 530 if (cur_rx == NUM_RX_DESC - 1) 531 tpc->RxDescArray[cur_rx].status = 532 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); 533 else 534 tpc->RxDescArray[cur_rx].status = 535 cpu_to_le32(OWNbit + RX_BUF_SIZE); 536 tpc->RxDescArray[cur_rx].buf_addr = 537 cpu_to_le32(bus_to_phys(tpc->RxBufferRing[cur_rx])); 538 rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]); 539 540 NetReceive(rxdata, length); 541 } else { 542 puts("Error Rx"); 543 } 544 cur_rx = (cur_rx + 1) % NUM_RX_DESC; 545 tpc->cur_rx = cur_rx; 546 return 1; 547 548 } else { 549 ushort sts = RTL_R8(IntrStatus); 550 RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr)); 551 udelay(100); /* wait */ 552 } 553 tpc->cur_rx = cur_rx; 554 return (0); /* initially as this is called to flush the input */ 555 } 556 557 #define HZ 1000 558 /************************************************************************** 559 SEND - Transmit a frame 560 ***************************************************************************/ 561 static int rtl_send(struct eth_device *dev, void *packet, int length) 562 { 563 /* send the packet to destination */ 564 565 u32 to; 566 u8 *ptxb; 567 int entry = tpc->cur_tx % NUM_TX_DESC; 568 u32 len = length; 569 int ret; 570 571 #ifdef DEBUG_RTL8169_TX 572 int stime = currticks(); 573 printf ("%s\n", __FUNCTION__); 574 printf("sending %d bytes\n", len); 575 #endif 576 577 ioaddr = dev->iobase; 578 579 /* point to the current txb incase multiple tx_rings are used */ 580 ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE]; 581 memcpy(ptxb, (char *)packet, (int)length); 582 rtl_flush_buffer(ptxb, length); 583 584 while (len < ETH_ZLEN) 585 ptxb[len++] = '\0'; 586 587 tpc->TxDescArray[entry].buf_Haddr = 0; 588 tpc->TxDescArray[entry].buf_addr = cpu_to_le32(bus_to_phys(ptxb)); 589 if (entry != (NUM_TX_DESC - 1)) { 590 tpc->TxDescArray[entry].status = 591 cpu_to_le32((OWNbit | FSbit | LSbit) | 592 ((len > ETH_ZLEN) ? len : ETH_ZLEN)); 593 } else { 594 tpc->TxDescArray[entry].status = 595 cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) | 596 ((len > ETH_ZLEN) ? len : ETH_ZLEN)); 597 } 598 rtl_flush_tx_desc(&tpc->TxDescArray[entry]); 599 RTL_W8(TxPoll, 0x40); /* set polling bit */ 600 601 tpc->cur_tx++; 602 to = currticks() + TX_TIMEOUT; 603 do { 604 rtl_inval_tx_desc(&tpc->TxDescArray[entry]); 605 } while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit) 606 && (currticks() < to)); /* wait */ 607 608 if (currticks() >= to) { 609 #ifdef DEBUG_RTL8169_TX 610 puts("tx timeout/error\n"); 611 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 612 #endif 613 ret = 0; 614 } else { 615 #ifdef DEBUG_RTL8169_TX 616 puts("tx done\n"); 617 #endif 618 ret = length; 619 } 620 /* Delay to make net console (nc) work properly */ 621 udelay(20); 622 return ret; 623 } 624 625 static void rtl8169_set_rx_mode(struct eth_device *dev) 626 { 627 u32 mc_filter[2]; /* Multicast hash filter */ 628 int rx_mode; 629 u32 tmp = 0; 630 631 #ifdef DEBUG_RTL8169 632 printf ("%s\n", __FUNCTION__); 633 #endif 634 635 /* IFF_ALLMULTI */ 636 /* Too many to filter perfectly -- accept all multicasts. */ 637 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; 638 mc_filter[1] = mc_filter[0] = 0xffffffff; 639 640 tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) & 641 rtl_chip_info[tpc->chipset].RxConfigMask); 642 643 RTL_W32(RxConfig, tmp); 644 RTL_W32(MAR0 + 0, mc_filter[0]); 645 RTL_W32(MAR0 + 4, mc_filter[1]); 646 } 647 648 static void rtl8169_hw_start(struct eth_device *dev) 649 { 650 u32 i; 651 652 #ifdef DEBUG_RTL8169 653 int stime = currticks(); 654 printf ("%s\n", __FUNCTION__); 655 #endif 656 657 #if 0 658 /* Soft reset the chip. */ 659 RTL_W8(ChipCmd, CmdReset); 660 661 /* Check that the chip has finished the reset. */ 662 for (i = 1000; i > 0; i--) { 663 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 664 break; 665 else 666 udelay(10); 667 } 668 #endif 669 670 RTL_W8(Cfg9346, Cfg9346_Unlock); 671 672 /* RTL-8169sb/8110sb or previous version */ 673 if (tpc->chipset <= 5) 674 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 675 676 RTL_W8(EarlyTxThres, EarlyTxThld); 677 678 /* For gigabit rtl8169 */ 679 RTL_W16(RxMaxSize, RxPacketMaxSize); 680 681 /* Set Rx Config register */ 682 i = rtl8169_rx_config | (RTL_R32(RxConfig) & 683 rtl_chip_info[tpc->chipset].RxConfigMask); 684 RTL_W32(RxConfig, i); 685 686 /* Set DMA burst size and Interframe Gap Time */ 687 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | 688 (InterFrameGap << TxInterFrameGapShift)); 689 690 691 tpc->cur_rx = 0; 692 693 RTL_W32(TxDescStartAddrLow, bus_to_phys(tpc->TxDescArray)); 694 RTL_W32(TxDescStartAddrHigh, (unsigned long)0); 695 RTL_W32(RxDescStartAddrLow, bus_to_phys(tpc->RxDescArray)); 696 RTL_W32(RxDescStartAddrHigh, (unsigned long)0); 697 698 /* RTL-8169sc/8110sc or later version */ 699 if (tpc->chipset > 5) 700 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 701 702 RTL_W8(Cfg9346, Cfg9346_Lock); 703 udelay(10); 704 705 RTL_W32(RxMissed, 0); 706 707 rtl8169_set_rx_mode(dev); 708 709 /* no early-rx interrupts */ 710 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); 711 712 #ifdef DEBUG_RTL8169 713 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 714 #endif 715 } 716 717 static void rtl8169_init_ring(struct eth_device *dev) 718 { 719 int i; 720 721 #ifdef DEBUG_RTL8169 722 int stime = currticks(); 723 printf ("%s\n", __FUNCTION__); 724 #endif 725 726 tpc->cur_rx = 0; 727 tpc->cur_tx = 0; 728 tpc->dirty_tx = 0; 729 memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc)); 730 memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc)); 731 732 for (i = 0; i < NUM_TX_DESC; i++) { 733 tpc->Tx_skbuff[i] = &txb[i]; 734 } 735 736 for (i = 0; i < NUM_RX_DESC; i++) { 737 if (i == (NUM_RX_DESC - 1)) 738 tpc->RxDescArray[i].status = 739 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); 740 else 741 tpc->RxDescArray[i].status = 742 cpu_to_le32(OWNbit + RX_BUF_SIZE); 743 744 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE]; 745 tpc->RxDescArray[i].buf_addr = 746 cpu_to_le32(bus_to_phys(tpc->RxBufferRing[i])); 747 rtl_flush_rx_desc(&tpc->RxDescArray[i]); 748 } 749 750 #ifdef DEBUG_RTL8169 751 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 752 #endif 753 } 754 755 /************************************************************************** 756 RESET - Finish setting up the ethernet interface 757 ***************************************************************************/ 758 static int rtl_reset(struct eth_device *dev, bd_t *bis) 759 { 760 int i; 761 762 #ifdef DEBUG_RTL8169 763 int stime = currticks(); 764 printf ("%s\n", __FUNCTION__); 765 #endif 766 767 rtl8169_init_ring(dev); 768 rtl8169_hw_start(dev); 769 /* Construct a perfect filter frame with the mac address as first match 770 * and broadcast for all others */ 771 for (i = 0; i < 192; i++) 772 txb[i] = 0xFF; 773 774 txb[0] = dev->enetaddr[0]; 775 txb[1] = dev->enetaddr[1]; 776 txb[2] = dev->enetaddr[2]; 777 txb[3] = dev->enetaddr[3]; 778 txb[4] = dev->enetaddr[4]; 779 txb[5] = dev->enetaddr[5]; 780 781 #ifdef DEBUG_RTL8169 782 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 783 #endif 784 return 0; 785 } 786 787 /************************************************************************** 788 HALT - Turn off ethernet interface 789 ***************************************************************************/ 790 static void rtl_halt(struct eth_device *dev) 791 { 792 int i; 793 794 #ifdef DEBUG_RTL8169 795 printf ("%s\n", __FUNCTION__); 796 #endif 797 798 ioaddr = dev->iobase; 799 800 /* Stop the chip's Tx and Rx DMA processes. */ 801 RTL_W8(ChipCmd, 0x00); 802 803 /* Disable interrupts by clearing the interrupt mask. */ 804 RTL_W16(IntrMask, 0x0000); 805 806 RTL_W32(RxMissed, 0); 807 808 for (i = 0; i < NUM_RX_DESC; i++) { 809 tpc->RxBufferRing[i] = NULL; 810 } 811 } 812 813 /************************************************************************** 814 INIT - Look for an adapter, this routine's visible to the outside 815 ***************************************************************************/ 816 817 #define board_found 1 818 #define valid_link 0 819 static int rtl_init(struct eth_device *dev, bd_t *bis) 820 { 821 static int board_idx = -1; 822 int i, rc; 823 int option = -1, Cap10_100 = 0, Cap1000 = 0; 824 825 #ifdef DEBUG_RTL8169 826 printf ("%s\n", __FUNCTION__); 827 #endif 828 829 ioaddr = dev->iobase; 830 831 board_idx++; 832 833 /* point to private storage */ 834 tpc = &tpx; 835 836 rc = rtl8169_init_board(dev); 837 if (rc) 838 return rc; 839 840 /* Get MAC address. FIXME: read EEPROM */ 841 for (i = 0; i < MAC_ADDR_LEN; i++) 842 dev->enetaddr[i] = RTL_R8(MAC0 + i); 843 844 #ifdef DEBUG_RTL8169 845 printf("chipset = %d\n", tpc->chipset); 846 printf("MAC Address"); 847 for (i = 0; i < MAC_ADDR_LEN; i++) 848 printf(":%02x", dev->enetaddr[i]); 849 putc('\n'); 850 #endif 851 852 #ifdef DEBUG_RTL8169 853 /* Print out some hardware info */ 854 printf("%s: at ioaddr 0x%x\n", dev->name, ioaddr); 855 #endif 856 857 /* if TBI is not endbled */ 858 if (!(RTL_R8(PHYstatus) & TBI_Enable)) { 859 int val = mdio_read(PHY_AUTO_NEGO_REG); 860 861 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx]; 862 /* Force RTL8169 in 10/100/1000 Full/Half mode. */ 863 if (option > 0) { 864 #ifdef DEBUG_RTL8169 865 printf("%s: Force-mode Enabled.\n", dev->name); 866 #endif 867 Cap10_100 = 0, Cap1000 = 0; 868 switch (option) { 869 case _10_Half: 870 Cap10_100 = PHY_Cap_10_Half; 871 Cap1000 = PHY_Cap_Null; 872 break; 873 case _10_Full: 874 Cap10_100 = PHY_Cap_10_Full; 875 Cap1000 = PHY_Cap_Null; 876 break; 877 case _100_Half: 878 Cap10_100 = PHY_Cap_100_Half; 879 Cap1000 = PHY_Cap_Null; 880 break; 881 case _100_Full: 882 Cap10_100 = PHY_Cap_100_Full; 883 Cap1000 = PHY_Cap_Null; 884 break; 885 case _1000_Full: 886 Cap10_100 = PHY_Cap_Null; 887 Cap1000 = PHY_Cap_1000_Full; 888 break; 889 default: 890 break; 891 } 892 mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 893 mdio_write(PHY_1000_CTRL_REG, Cap1000); 894 } else { 895 #ifdef DEBUG_RTL8169 896 printf("%s: Auto-negotiation Enabled.\n", 897 dev->name); 898 #endif 899 /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 900 mdio_write(PHY_AUTO_NEGO_REG, 901 PHY_Cap_10_Half | PHY_Cap_10_Full | 902 PHY_Cap_100_Half | PHY_Cap_100_Full | 903 (val & 0x1F)); 904 905 /* enable 1000 Full Mode */ 906 mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full); 907 908 } 909 910 /* Enable auto-negotiation and restart auto-nigotiation */ 911 mdio_write(PHY_CTRL_REG, 912 PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego); 913 udelay(100); 914 915 /* wait for auto-negotiation process */ 916 for (i = 10000; i > 0; i--) { 917 /* check if auto-negotiation complete */ 918 if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) { 919 udelay(100); 920 option = RTL_R8(PHYstatus); 921 if (option & _1000bpsF) { 922 #ifdef DEBUG_RTL8169 923 printf("%s: 1000Mbps Full-duplex operation.\n", 924 dev->name); 925 #endif 926 } else { 927 #ifdef DEBUG_RTL8169 928 printf("%s: %sMbps %s-duplex operation.\n", 929 dev->name, 930 (option & _100bps) ? "100" : 931 "10", 932 (option & FullDup) ? "Full" : 933 "Half"); 934 #endif 935 } 936 break; 937 } else { 938 udelay(100); 939 } 940 } /* end for-loop to wait for auto-negotiation process */ 941 942 } else { 943 udelay(100); 944 #ifdef DEBUG_RTL8169 945 printf 946 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n", 947 dev->name, 948 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed"); 949 #endif 950 } 951 952 953 tpc->RxDescArray = rtl_alloc_descs(NUM_RX_DESC); 954 if (!tpc->RxDescArray) 955 return -ENOMEM; 956 957 tpc->TxDescArray = rtl_alloc_descs(NUM_TX_DESC); 958 if (!tpc->TxDescArray) 959 return -ENOMEM; 960 961 return 0; 962 } 963 964 int rtl8169_initialize(bd_t *bis) 965 { 966 pci_dev_t devno; 967 int card_number = 0; 968 struct eth_device *dev; 969 u32 iobase; 970 int idx=0; 971 972 while(1){ 973 unsigned int region; 974 u16 device; 975 int err; 976 977 /* Find RTL8169 */ 978 if ((devno = pci_find_devices(supported, idx++)) < 0) 979 break; 980 981 pci_read_config_word(devno, PCI_DEVICE_ID, &device); 982 switch (device) { 983 case 0x8168: 984 region = 2; 985 break; 986 987 default: 988 region = 1; 989 break; 990 } 991 992 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase); 993 iobase &= ~0xf; 994 995 debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); 996 997 dev = (struct eth_device *)malloc(sizeof *dev); 998 if (!dev) { 999 printf("Can not allocate memory of rtl8169\n"); 1000 break; 1001 } 1002 1003 memset(dev, 0, sizeof(*dev)); 1004 sprintf (dev->name, "RTL8169#%d", card_number); 1005 1006 dev->priv = (void *) devno; 1007 dev->iobase = (int)pci_mem_to_phys(devno, iobase); 1008 1009 dev->init = rtl_reset; 1010 dev->halt = rtl_halt; 1011 dev->send = rtl_send; 1012 dev->recv = rtl_recv; 1013 1014 err = rtl_init(dev, bis); 1015 if (err < 0) { 1016 printf(pr_fmt("failed to initialize card: %d\n"), err); 1017 free(dev); 1018 continue; 1019 } 1020 1021 eth_register (dev); 1022 1023 card_number++; 1024 } 1025 return card_number; 1026 } 1027