1 /* 2 * rtl8169.c : U-Boot driver for the RealTek RTL8169 3 * 4 * Masami Komiya (mkomiya@sonare.it) 5 * 6 * Most part is taken from r8169.c of etherboot 7 * 8 */ 9 10 /************************************************************************** 11 * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit 12 * Written 2003 by Timothy Legge <tlegge@rogers.com> 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 * 16 * Portions of this code based on: 17 * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver 18 * for Linux kernel 2.4.x. 19 * 20 * Written 2002 ShuChen <shuchen@realtek.com.tw> 21 * See Linux Driver for full information 22 * 23 * Linux Driver Version 1.27a, 10.02.2002 24 * 25 * Thanks to: 26 * Jean Chen of RealTek Semiconductor Corp. for 27 * providing the evaluation NIC used to develop 28 * this driver. RealTek's support for Etherboot 29 * is appreciated. 30 * 31 * REVISION HISTORY: 32 * ================ 33 * 34 * v1.0 11-26-2003 timlegge Initial port of Linux driver 35 * v1.5 01-17-2004 timlegge Initial driver output cleanup 36 * 37 * Indent Options: indent -kr -i8 38 ***************************************************************************/ 39 /* 40 * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk> 41 * Modified to use le32_to_cpu and cpu_to_le32 properly 42 */ 43 #include <common.h> 44 #include <malloc.h> 45 #include <net.h> 46 #include <netdev.h> 47 #include <asm/io.h> 48 #include <pci.h> 49 50 #undef DEBUG_RTL8169 51 #undef DEBUG_RTL8169_TX 52 #undef DEBUG_RTL8169_RX 53 54 #define drv_version "v1.5" 55 #define drv_date "01-17-2004" 56 57 static u32 ioaddr; 58 59 /* Condensed operations for readability. */ 60 #define currticks() get_timer(0) 61 62 /* media options */ 63 #define MAX_UNITS 8 64 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 }; 65 66 /* MAC address length*/ 67 #define MAC_ADDR_LEN 6 68 69 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/ 70 #define MAX_ETH_FRAME_SIZE 1536 71 72 #define TX_FIFO_THRESH 256 /* In bytes */ 73 74 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ 75 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 76 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 77 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ 78 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */ 79 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 80 81 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */ 82 #ifdef CONFIG_SYS_RX_ETH_BUFFER 83 #define NUM_RX_DESC CONFIG_SYS_RX_ETH_BUFFER 84 #else 85 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */ 86 #endif 87 #define RX_BUF_SIZE 1536 /* Rx Buffer size */ 88 #define RX_BUF_LEN 8192 89 90 #define RTL_MIN_IO_SIZE 0x80 91 #define TX_TIMEOUT (6*HZ) 92 93 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */ 94 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) 95 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) 96 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) 97 #define RTL_R8(reg) readb (ioaddr + (reg)) 98 #define RTL_R16(reg) readw (ioaddr + (reg)) 99 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) 100 101 #define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE 102 #define ETH_ALEN MAC_ADDR_LEN 103 #define ETH_ZLEN 60 104 105 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, (pci_addr_t)a) 106 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, (phys_addr_t)a) 107 108 enum RTL8169_registers { 109 MAC0 = 0, /* Ethernet hardware address. */ 110 MAR0 = 8, /* Multicast filter. */ 111 TxDescStartAddrLow = 0x20, 112 TxDescStartAddrHigh = 0x24, 113 TxHDescStartAddrLow = 0x28, 114 TxHDescStartAddrHigh = 0x2c, 115 FLASH = 0x30, 116 ERSR = 0x36, 117 ChipCmd = 0x37, 118 TxPoll = 0x38, 119 IntrMask = 0x3C, 120 IntrStatus = 0x3E, 121 TxConfig = 0x40, 122 RxConfig = 0x44, 123 RxMissed = 0x4C, 124 Cfg9346 = 0x50, 125 Config0 = 0x51, 126 Config1 = 0x52, 127 Config2 = 0x53, 128 Config3 = 0x54, 129 Config4 = 0x55, 130 Config5 = 0x56, 131 MultiIntr = 0x5C, 132 PHYAR = 0x60, 133 TBICSR = 0x64, 134 TBI_ANAR = 0x68, 135 TBI_LPAR = 0x6A, 136 PHYstatus = 0x6C, 137 RxMaxSize = 0xDA, 138 CPlusCmd = 0xE0, 139 RxDescStartAddrLow = 0xE4, 140 RxDescStartAddrHigh = 0xE8, 141 EarlyTxThres = 0xEC, 142 FuncEvent = 0xF0, 143 FuncEventMask = 0xF4, 144 FuncPresetState = 0xF8, 145 FuncForceEvent = 0xFC, 146 }; 147 148 enum RTL8169_register_content { 149 /*InterruptStatusBits */ 150 SYSErr = 0x8000, 151 PCSTimeout = 0x4000, 152 SWInt = 0x0100, 153 TxDescUnavail = 0x80, 154 RxFIFOOver = 0x40, 155 RxUnderrun = 0x20, 156 RxOverflow = 0x10, 157 TxErr = 0x08, 158 TxOK = 0x04, 159 RxErr = 0x02, 160 RxOK = 0x01, 161 162 /*RxStatusDesc */ 163 RxRES = 0x00200000, 164 RxCRC = 0x00080000, 165 RxRUNT = 0x00100000, 166 RxRWT = 0x00400000, 167 168 /*ChipCmdBits */ 169 CmdReset = 0x10, 170 CmdRxEnb = 0x08, 171 CmdTxEnb = 0x04, 172 RxBufEmpty = 0x01, 173 174 /*Cfg9346Bits */ 175 Cfg9346_Lock = 0x00, 176 Cfg9346_Unlock = 0xC0, 177 178 /*rx_mode_bits */ 179 AcceptErr = 0x20, 180 AcceptRunt = 0x10, 181 AcceptBroadcast = 0x08, 182 AcceptMulticast = 0x04, 183 AcceptMyPhys = 0x02, 184 AcceptAllPhys = 0x01, 185 186 /*RxConfigBits */ 187 RxCfgFIFOShift = 13, 188 RxCfgDMAShift = 8, 189 190 /*TxConfigBits */ 191 TxInterFrameGapShift = 24, 192 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 193 194 /*rtl8169_PHYstatus */ 195 TBI_Enable = 0x80, 196 TxFlowCtrl = 0x40, 197 RxFlowCtrl = 0x20, 198 _1000bpsF = 0x10, 199 _100bps = 0x08, 200 _10bps = 0x04, 201 LinkStatus = 0x02, 202 FullDup = 0x01, 203 204 /*GIGABIT_PHY_registers */ 205 PHY_CTRL_REG = 0, 206 PHY_STAT_REG = 1, 207 PHY_AUTO_NEGO_REG = 4, 208 PHY_1000_CTRL_REG = 9, 209 210 /*GIGABIT_PHY_REG_BIT */ 211 PHY_Restart_Auto_Nego = 0x0200, 212 PHY_Enable_Auto_Nego = 0x1000, 213 214 /* PHY_STAT_REG = 1; */ 215 PHY_Auto_Nego_Comp = 0x0020, 216 217 /* PHY_AUTO_NEGO_REG = 4; */ 218 PHY_Cap_10_Half = 0x0020, 219 PHY_Cap_10_Full = 0x0040, 220 PHY_Cap_100_Half = 0x0080, 221 PHY_Cap_100_Full = 0x0100, 222 223 /* PHY_1000_CTRL_REG = 9; */ 224 PHY_Cap_1000_Full = 0x0200, 225 226 PHY_Cap_Null = 0x0, 227 228 /*_MediaType*/ 229 _10_Half = 0x01, 230 _10_Full = 0x02, 231 _100_Half = 0x04, 232 _100_Full = 0x08, 233 _1000_Full = 0x10, 234 235 /*_TBICSRBit*/ 236 TBILinkOK = 0x02000000, 237 }; 238 239 static struct { 240 const char *name; 241 u8 version; /* depend on RTL8169 docs */ 242 u32 RxConfigMask; /* should clear the bits supported by this chip */ 243 } rtl_chip_info[] = { 244 {"RTL-8169", 0x00, 0xff7e1880,}, 245 {"RTL-8169", 0x04, 0xff7e1880,}, 246 {"RTL-8169", 0x00, 0xff7e1880,}, 247 {"RTL-8169s/8110s", 0x02, 0xff7e1880,}, 248 {"RTL-8169s/8110s", 0x04, 0xff7e1880,}, 249 {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,}, 250 {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,}, 251 {"RTL-8168b/8111sb", 0x30, 0xff7e1880,}, 252 {"RTL-8168b/8111sb", 0x38, 0xff7e1880,}, 253 {"RTL-8168d/8111d", 0x28, 0xff7e1880,}, 254 {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,}, 255 {"RTL-8101e", 0x34, 0xff7e1880,}, 256 {"RTL-8100e", 0x32, 0xff7e1880,}, 257 }; 258 259 enum _DescStatusBit { 260 OWNbit = 0x80000000, 261 EORbit = 0x40000000, 262 FSbit = 0x20000000, 263 LSbit = 0x10000000, 264 }; 265 266 struct TxDesc { 267 u32 status; 268 u32 vlan_tag; 269 u32 buf_addr; 270 u32 buf_Haddr; 271 }; 272 273 struct RxDesc { 274 u32 status; 275 u32 vlan_tag; 276 u32 buf_addr; 277 u32 buf_Haddr; 278 }; 279 280 /* Define the TX Descriptor */ 281 static u8 tx_ring[NUM_TX_DESC * sizeof(struct TxDesc) + 256]; 282 /* __attribute__ ((aligned(256))); */ 283 284 /* Create a static buffer of size RX_BUF_SZ for each 285 TX Descriptor. All descriptors point to a 286 part of this buffer */ 287 static unsigned char txb[NUM_TX_DESC * RX_BUF_SIZE]; 288 289 /* Define the RX Descriptor */ 290 static u8 rx_ring[NUM_RX_DESC * sizeof(struct TxDesc) + 256]; 291 /* __attribute__ ((aligned(256))); */ 292 293 /* Create a static buffer of size RX_BUF_SZ for each 294 RX Descriptor All descriptors point to a 295 part of this buffer */ 296 static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE]; 297 298 struct rtl8169_private { 299 void *mmio_addr; /* memory map physical address */ 300 int chipset; 301 unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 302 unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 303 unsigned long dirty_tx; 304 unsigned char *TxDescArrays; /* Index of Tx Descriptor buffer */ 305 unsigned char *RxDescArrays; /* Index of Rx Descriptor buffer */ 306 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */ 307 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */ 308 unsigned char *RxBufferRings; /* Index of Rx Buffer */ 309 unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */ 310 unsigned char *Tx_skbuff[NUM_TX_DESC]; 311 } tpx; 312 313 static struct rtl8169_private *tpc; 314 315 static const u16 rtl8169_intr_mask = 316 SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr | 317 TxOK | RxErr | RxOK; 318 static const unsigned int rtl8169_rx_config = 319 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); 320 321 static struct pci_device_id supported[] = { 322 {PCI_VENDOR_ID_REALTEK, 0x8167}, 323 {PCI_VENDOR_ID_REALTEK, 0x8168}, 324 {PCI_VENDOR_ID_REALTEK, 0x8169}, 325 {} 326 }; 327 328 void mdio_write(int RegAddr, int value) 329 { 330 int i; 331 332 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value); 333 udelay(1000); 334 335 for (i = 2000; i > 0; i--) { 336 /* Check if the RTL8169 has completed writing to the specified MII register */ 337 if (!(RTL_R32(PHYAR) & 0x80000000)) { 338 break; 339 } else { 340 udelay(100); 341 } 342 } 343 } 344 345 int mdio_read(int RegAddr) 346 { 347 int i, value = -1; 348 349 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16); 350 udelay(1000); 351 352 for (i = 2000; i > 0; i--) { 353 /* Check if the RTL8169 has completed retrieving data from the specified MII register */ 354 if (RTL_R32(PHYAR) & 0x80000000) { 355 value = (int) (RTL_R32(PHYAR) & 0xFFFF); 356 break; 357 } else { 358 udelay(100); 359 } 360 } 361 return value; 362 } 363 364 static int rtl8169_init_board(struct eth_device *dev) 365 { 366 int i; 367 u32 tmp; 368 369 #ifdef DEBUG_RTL8169 370 printf ("%s\n", __FUNCTION__); 371 #endif 372 ioaddr = dev->iobase; 373 374 /* Soft reset the chip. */ 375 RTL_W8(ChipCmd, CmdReset); 376 377 /* Check that the chip has finished the reset. */ 378 for (i = 1000; i > 0; i--) 379 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 380 break; 381 else 382 udelay(10); 383 384 /* identify chip attached to board */ 385 tmp = RTL_R32(TxConfig); 386 tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24; 387 388 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){ 389 if (tmp == rtl_chip_info[i].version) { 390 tpc->chipset = i; 391 goto match; 392 } 393 } 394 395 /* if unknown chip, assume array element #0, original RTL-8169 in this case */ 396 printf("PCI device %s: unknown chip version, assuming RTL-8169\n", dev->name); 397 printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig)); 398 tpc->chipset = 0; 399 400 match: 401 return 0; 402 } 403 404 /* 405 * Cache maintenance functions. These are simple wrappers around the more 406 * general purpose flush_cache() and invalidate_dcache_range() functions. 407 */ 408 409 static void rtl_inval_rx_desc(struct RxDesc *desc) 410 { 411 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); 412 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN); 413 414 invalidate_dcache_range(start, end); 415 } 416 417 static void rtl_flush_rx_desc(struct RxDesc *desc) 418 { 419 flush_cache((unsigned long)desc, sizeof(*desc)); 420 } 421 422 static void rtl_inval_tx_desc(struct TxDesc *desc) 423 { 424 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); 425 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN); 426 427 invalidate_dcache_range(start, end); 428 } 429 430 static void rtl_flush_tx_desc(struct TxDesc *desc) 431 { 432 flush_cache((unsigned long)desc, sizeof(*desc)); 433 } 434 435 static void rtl_inval_buffer(void *buf, size_t size) 436 { 437 unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1); 438 unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN); 439 440 invalidate_dcache_range(start, end); 441 } 442 443 static void rtl_flush_buffer(void *buf, size_t size) 444 { 445 flush_cache((unsigned long)buf, size); 446 } 447 448 /************************************************************************** 449 RECV - Receive a frame 450 ***************************************************************************/ 451 static int rtl_recv(struct eth_device *dev) 452 { 453 /* return true if there's an ethernet packet ready to read */ 454 /* nic->packet should contain data on return */ 455 /* nic->packetlen should contain length of data */ 456 int cur_rx; 457 int length = 0; 458 459 #ifdef DEBUG_RTL8169_RX 460 printf ("%s\n", __FUNCTION__); 461 #endif 462 ioaddr = dev->iobase; 463 464 cur_rx = tpc->cur_rx; 465 466 rtl_inval_rx_desc(&tpc->RxDescArray[cur_rx]); 467 468 if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) { 469 if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) { 470 unsigned char rxdata[RX_BUF_LEN]; 471 length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx]. 472 status) & 0x00001FFF) - 4; 473 474 rtl_inval_buffer(tpc->RxBufferRing[cur_rx], length); 475 memcpy(rxdata, tpc->RxBufferRing[cur_rx], length); 476 477 if (cur_rx == NUM_RX_DESC - 1) 478 tpc->RxDescArray[cur_rx].status = 479 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); 480 else 481 tpc->RxDescArray[cur_rx].status = 482 cpu_to_le32(OWNbit + RX_BUF_SIZE); 483 tpc->RxDescArray[cur_rx].buf_addr = 484 cpu_to_le32(bus_to_phys(tpc->RxBufferRing[cur_rx])); 485 rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]); 486 487 NetReceive(rxdata, length); 488 } else { 489 puts("Error Rx"); 490 } 491 cur_rx = (cur_rx + 1) % NUM_RX_DESC; 492 tpc->cur_rx = cur_rx; 493 return 1; 494 495 } else { 496 ushort sts = RTL_R8(IntrStatus); 497 RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr)); 498 udelay(100); /* wait */ 499 } 500 tpc->cur_rx = cur_rx; 501 return (0); /* initially as this is called to flush the input */ 502 } 503 504 #define HZ 1000 505 /************************************************************************** 506 SEND - Transmit a frame 507 ***************************************************************************/ 508 static int rtl_send(struct eth_device *dev, void *packet, int length) 509 { 510 /* send the packet to destination */ 511 512 u32 to; 513 u8 *ptxb; 514 int entry = tpc->cur_tx % NUM_TX_DESC; 515 u32 len = length; 516 int ret; 517 518 #ifdef DEBUG_RTL8169_TX 519 int stime = currticks(); 520 printf ("%s\n", __FUNCTION__); 521 printf("sending %d bytes\n", len); 522 #endif 523 524 ioaddr = dev->iobase; 525 526 /* point to the current txb incase multiple tx_rings are used */ 527 ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE]; 528 memcpy(ptxb, (char *)packet, (int)length); 529 rtl_flush_buffer(ptxb, length); 530 531 while (len < ETH_ZLEN) 532 ptxb[len++] = '\0'; 533 534 tpc->TxDescArray[entry].buf_Haddr = 0; 535 tpc->TxDescArray[entry].buf_addr = cpu_to_le32(bus_to_phys(ptxb)); 536 if (entry != (NUM_TX_DESC - 1)) { 537 tpc->TxDescArray[entry].status = 538 cpu_to_le32((OWNbit | FSbit | LSbit) | 539 ((len > ETH_ZLEN) ? len : ETH_ZLEN)); 540 } else { 541 tpc->TxDescArray[entry].status = 542 cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) | 543 ((len > ETH_ZLEN) ? len : ETH_ZLEN)); 544 } 545 rtl_flush_tx_desc(&tpc->TxDescArray[entry]); 546 RTL_W8(TxPoll, 0x40); /* set polling bit */ 547 548 tpc->cur_tx++; 549 to = currticks() + TX_TIMEOUT; 550 do { 551 rtl_inval_tx_desc(&tpc->TxDescArray[entry]); 552 } while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit) 553 && (currticks() < to)); /* wait */ 554 555 if (currticks() >= to) { 556 #ifdef DEBUG_RTL8169_TX 557 puts("tx timeout/error\n"); 558 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 559 #endif 560 ret = 0; 561 } else { 562 #ifdef DEBUG_RTL8169_TX 563 puts("tx done\n"); 564 #endif 565 ret = length; 566 } 567 /* Delay to make net console (nc) work properly */ 568 udelay(20); 569 return ret; 570 } 571 572 static void rtl8169_set_rx_mode(struct eth_device *dev) 573 { 574 u32 mc_filter[2]; /* Multicast hash filter */ 575 int rx_mode; 576 u32 tmp = 0; 577 578 #ifdef DEBUG_RTL8169 579 printf ("%s\n", __FUNCTION__); 580 #endif 581 582 /* IFF_ALLMULTI */ 583 /* Too many to filter perfectly -- accept all multicasts. */ 584 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; 585 mc_filter[1] = mc_filter[0] = 0xffffffff; 586 587 tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) & 588 rtl_chip_info[tpc->chipset].RxConfigMask); 589 590 RTL_W32(RxConfig, tmp); 591 RTL_W32(MAR0 + 0, mc_filter[0]); 592 RTL_W32(MAR0 + 4, mc_filter[1]); 593 } 594 595 static void rtl8169_hw_start(struct eth_device *dev) 596 { 597 u32 i; 598 599 #ifdef DEBUG_RTL8169 600 int stime = currticks(); 601 printf ("%s\n", __FUNCTION__); 602 #endif 603 604 #if 0 605 /* Soft reset the chip. */ 606 RTL_W8(ChipCmd, CmdReset); 607 608 /* Check that the chip has finished the reset. */ 609 for (i = 1000; i > 0; i--) { 610 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 611 break; 612 else 613 udelay(10); 614 } 615 #endif 616 617 RTL_W8(Cfg9346, Cfg9346_Unlock); 618 619 /* RTL-8169sb/8110sb or previous version */ 620 if (tpc->chipset <= 5) 621 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 622 623 RTL_W8(EarlyTxThres, EarlyTxThld); 624 625 /* For gigabit rtl8169 */ 626 RTL_W16(RxMaxSize, RxPacketMaxSize); 627 628 /* Set Rx Config register */ 629 i = rtl8169_rx_config | (RTL_R32(RxConfig) & 630 rtl_chip_info[tpc->chipset].RxConfigMask); 631 RTL_W32(RxConfig, i); 632 633 /* Set DMA burst size and Interframe Gap Time */ 634 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | 635 (InterFrameGap << TxInterFrameGapShift)); 636 637 638 tpc->cur_rx = 0; 639 640 RTL_W32(TxDescStartAddrLow, bus_to_phys(tpc->TxDescArray)); 641 RTL_W32(TxDescStartAddrHigh, (unsigned long)0); 642 RTL_W32(RxDescStartAddrLow, bus_to_phys(tpc->RxDescArray)); 643 RTL_W32(RxDescStartAddrHigh, (unsigned long)0); 644 645 /* RTL-8169sc/8110sc or later version */ 646 if (tpc->chipset > 5) 647 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 648 649 RTL_W8(Cfg9346, Cfg9346_Lock); 650 udelay(10); 651 652 RTL_W32(RxMissed, 0); 653 654 rtl8169_set_rx_mode(dev); 655 656 /* no early-rx interrupts */ 657 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); 658 659 #ifdef DEBUG_RTL8169 660 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 661 #endif 662 } 663 664 static void rtl8169_init_ring(struct eth_device *dev) 665 { 666 int i; 667 668 #ifdef DEBUG_RTL8169 669 int stime = currticks(); 670 printf ("%s\n", __FUNCTION__); 671 #endif 672 673 tpc->cur_rx = 0; 674 tpc->cur_tx = 0; 675 tpc->dirty_tx = 0; 676 memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc)); 677 memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc)); 678 679 for (i = 0; i < NUM_TX_DESC; i++) { 680 tpc->Tx_skbuff[i] = &txb[i]; 681 } 682 683 for (i = 0; i < NUM_RX_DESC; i++) { 684 if (i == (NUM_RX_DESC - 1)) 685 tpc->RxDescArray[i].status = 686 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); 687 else 688 tpc->RxDescArray[i].status = 689 cpu_to_le32(OWNbit + RX_BUF_SIZE); 690 691 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE]; 692 tpc->RxDescArray[i].buf_addr = 693 cpu_to_le32(bus_to_phys(tpc->RxBufferRing[i])); 694 rtl_flush_rx_desc(&tpc->RxDescArray[i]); 695 } 696 697 #ifdef DEBUG_RTL8169 698 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 699 #endif 700 } 701 702 /************************************************************************** 703 RESET - Finish setting up the ethernet interface 704 ***************************************************************************/ 705 static int rtl_reset(struct eth_device *dev, bd_t *bis) 706 { 707 int i; 708 709 #ifdef DEBUG_RTL8169 710 int stime = currticks(); 711 printf ("%s\n", __FUNCTION__); 712 #endif 713 714 tpc->TxDescArrays = tx_ring; 715 /* Tx Desscriptor needs 256 bytes alignment; */ 716 tpc->TxDescArray = (struct TxDesc *) ((unsigned long)(tpc->TxDescArrays + 717 255) & ~255); 718 719 tpc->RxDescArrays = rx_ring; 720 /* Rx Desscriptor needs 256 bytes alignment; */ 721 tpc->RxDescArray = (struct RxDesc *) ((unsigned long)(tpc->RxDescArrays + 722 255) & ~255); 723 724 rtl8169_init_ring(dev); 725 rtl8169_hw_start(dev); 726 /* Construct a perfect filter frame with the mac address as first match 727 * and broadcast for all others */ 728 for (i = 0; i < 192; i++) 729 txb[i] = 0xFF; 730 731 txb[0] = dev->enetaddr[0]; 732 txb[1] = dev->enetaddr[1]; 733 txb[2] = dev->enetaddr[2]; 734 txb[3] = dev->enetaddr[3]; 735 txb[4] = dev->enetaddr[4]; 736 txb[5] = dev->enetaddr[5]; 737 738 #ifdef DEBUG_RTL8169 739 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 740 #endif 741 return 0; 742 } 743 744 /************************************************************************** 745 HALT - Turn off ethernet interface 746 ***************************************************************************/ 747 static void rtl_halt(struct eth_device *dev) 748 { 749 int i; 750 751 #ifdef DEBUG_RTL8169 752 printf ("%s\n", __FUNCTION__); 753 #endif 754 755 ioaddr = dev->iobase; 756 757 /* Stop the chip's Tx and Rx DMA processes. */ 758 RTL_W8(ChipCmd, 0x00); 759 760 /* Disable interrupts by clearing the interrupt mask. */ 761 RTL_W16(IntrMask, 0x0000); 762 763 RTL_W32(RxMissed, 0); 764 765 tpc->TxDescArrays = NULL; 766 tpc->RxDescArrays = NULL; 767 tpc->TxDescArray = NULL; 768 tpc->RxDescArray = NULL; 769 for (i = 0; i < NUM_RX_DESC; i++) { 770 tpc->RxBufferRing[i] = NULL; 771 } 772 } 773 774 /************************************************************************** 775 INIT - Look for an adapter, this routine's visible to the outside 776 ***************************************************************************/ 777 778 #define board_found 1 779 #define valid_link 0 780 static int rtl_init(struct eth_device *dev, bd_t *bis) 781 { 782 static int board_idx = -1; 783 int i, rc; 784 int option = -1, Cap10_100 = 0, Cap1000 = 0; 785 786 #ifdef DEBUG_RTL8169 787 printf ("%s\n", __FUNCTION__); 788 #endif 789 790 ioaddr = dev->iobase; 791 792 board_idx++; 793 794 /* point to private storage */ 795 tpc = &tpx; 796 797 rc = rtl8169_init_board(dev); 798 if (rc) 799 return rc; 800 801 /* Get MAC address. FIXME: read EEPROM */ 802 for (i = 0; i < MAC_ADDR_LEN; i++) 803 dev->enetaddr[i] = RTL_R8(MAC0 + i); 804 805 #ifdef DEBUG_RTL8169 806 printf("chipset = %d\n", tpc->chipset); 807 printf("MAC Address"); 808 for (i = 0; i < MAC_ADDR_LEN; i++) 809 printf(":%02x", dev->enetaddr[i]); 810 putc('\n'); 811 #endif 812 813 #ifdef DEBUG_RTL8169 814 /* Print out some hardware info */ 815 printf("%s: at ioaddr 0x%x\n", dev->name, ioaddr); 816 #endif 817 818 /* if TBI is not endbled */ 819 if (!(RTL_R8(PHYstatus) & TBI_Enable)) { 820 int val = mdio_read(PHY_AUTO_NEGO_REG); 821 822 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx]; 823 /* Force RTL8169 in 10/100/1000 Full/Half mode. */ 824 if (option > 0) { 825 #ifdef DEBUG_RTL8169 826 printf("%s: Force-mode Enabled.\n", dev->name); 827 #endif 828 Cap10_100 = 0, Cap1000 = 0; 829 switch (option) { 830 case _10_Half: 831 Cap10_100 = PHY_Cap_10_Half; 832 Cap1000 = PHY_Cap_Null; 833 break; 834 case _10_Full: 835 Cap10_100 = PHY_Cap_10_Full; 836 Cap1000 = PHY_Cap_Null; 837 break; 838 case _100_Half: 839 Cap10_100 = PHY_Cap_100_Half; 840 Cap1000 = PHY_Cap_Null; 841 break; 842 case _100_Full: 843 Cap10_100 = PHY_Cap_100_Full; 844 Cap1000 = PHY_Cap_Null; 845 break; 846 case _1000_Full: 847 Cap10_100 = PHY_Cap_Null; 848 Cap1000 = PHY_Cap_1000_Full; 849 break; 850 default: 851 break; 852 } 853 mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 854 mdio_write(PHY_1000_CTRL_REG, Cap1000); 855 } else { 856 #ifdef DEBUG_RTL8169 857 printf("%s: Auto-negotiation Enabled.\n", 858 dev->name); 859 #endif 860 /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 861 mdio_write(PHY_AUTO_NEGO_REG, 862 PHY_Cap_10_Half | PHY_Cap_10_Full | 863 PHY_Cap_100_Half | PHY_Cap_100_Full | 864 (val & 0x1F)); 865 866 /* enable 1000 Full Mode */ 867 mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full); 868 869 } 870 871 /* Enable auto-negotiation and restart auto-nigotiation */ 872 mdio_write(PHY_CTRL_REG, 873 PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego); 874 udelay(100); 875 876 /* wait for auto-negotiation process */ 877 for (i = 10000; i > 0; i--) { 878 /* check if auto-negotiation complete */ 879 if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) { 880 udelay(100); 881 option = RTL_R8(PHYstatus); 882 if (option & _1000bpsF) { 883 #ifdef DEBUG_RTL8169 884 printf("%s: 1000Mbps Full-duplex operation.\n", 885 dev->name); 886 #endif 887 } else { 888 #ifdef DEBUG_RTL8169 889 printf("%s: %sMbps %s-duplex operation.\n", 890 dev->name, 891 (option & _100bps) ? "100" : 892 "10", 893 (option & FullDup) ? "Full" : 894 "Half"); 895 #endif 896 } 897 break; 898 } else { 899 udelay(100); 900 } 901 } /* end for-loop to wait for auto-negotiation process */ 902 903 } else { 904 udelay(100); 905 #ifdef DEBUG_RTL8169 906 printf 907 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n", 908 dev->name, 909 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed"); 910 #endif 911 } 912 913 return 1; 914 } 915 916 int rtl8169_initialize(bd_t *bis) 917 { 918 pci_dev_t devno; 919 int card_number = 0; 920 struct eth_device *dev; 921 u32 iobase; 922 int idx=0; 923 924 while(1){ 925 unsigned int region; 926 u16 device; 927 928 /* Find RTL8169 */ 929 if ((devno = pci_find_devices(supported, idx++)) < 0) 930 break; 931 932 pci_read_config_word(devno, PCI_DEVICE_ID, &device); 933 switch (device) { 934 case 0x8168: 935 region = 2; 936 break; 937 938 default: 939 region = 1; 940 break; 941 } 942 943 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase); 944 iobase &= ~0xf; 945 946 debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); 947 948 dev = (struct eth_device *)malloc(sizeof *dev); 949 if (!dev) { 950 printf("Can not allocate memory of rtl8169\n"); 951 break; 952 } 953 954 memset(dev, 0, sizeof(*dev)); 955 sprintf (dev->name, "RTL8169#%d", card_number); 956 957 dev->priv = (void *) devno; 958 dev->iobase = (int)pci_mem_to_phys(devno, iobase); 959 960 dev->init = rtl_reset; 961 dev->halt = rtl_halt; 962 dev->send = rtl_send; 963 dev->recv = rtl_recv; 964 965 eth_register (dev); 966 967 rtl_init(dev, bis); 968 969 card_number++; 970 } 971 return card_number; 972 } 973