xref: /rk3399_rockchip-uboot/drivers/net/phy/atheros.c (revision 2ec4d10b65d1f7d45098606e9a6857d587c3027c)
1 /*
2  * Atheros PHY drivers
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  *
6  * Copyright 2011, 2013 Freescale Semiconductor, Inc.
7  * author Andy Fleming
8  */
9 #include <phy.h>
10 
11 static int ar8021_config(struct phy_device *phydev)
12 {
13 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
14 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
15 
16 	phydev->supported = phydev->drv->features;
17 	return 0;
18 }
19 
20 static int ar8035_config(struct phy_device *phydev)
21 {
22 	int regval;
23 
24 	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x0007);
25 	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
26 	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
27 	regval = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
28 	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, (regval|0x0018));
29 
30 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
31 	regval = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
32 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, (regval|0x0100));
33 
34 	if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
35 	    (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
36 		/* select debug reg 5 */
37 		phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x5);
38 		/* enable tx delay */
39 		phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x0100);
40 	}
41 
42 	if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
43 	    (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)) {
44 		/* select debug reg 0 */
45 		phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x0);
46 		/* enable rx delay */
47 		phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x8000);
48 	}
49 
50 	phydev->supported = phydev->drv->features;
51 
52 	genphy_config_aneg(phydev);
53 	genphy_restart_aneg(phydev);
54 
55 	return 0;
56 }
57 
58 static struct phy_driver AR8021_driver =  {
59 	.name = "AR8021",
60 	.uid = 0x4dd040,
61 	.mask = 0x4ffff0,
62 	.features = PHY_GBIT_FEATURES,
63 	.config = ar8021_config,
64 	.startup = genphy_startup,
65 	.shutdown = genphy_shutdown,
66 };
67 
68 static struct phy_driver AR8031_driver =  {
69 	.name = "AR8031/AR8033",
70 	.uid = 0x4dd074,
71 	.mask = 0xffffffef,
72 	.features = PHY_GBIT_FEATURES,
73 	.config = ar8035_config,
74 	.startup = genphy_startup,
75 	.shutdown = genphy_shutdown,
76 };
77 
78 static struct phy_driver AR8035_driver =  {
79 	.name = "AR8035",
80 	.uid = 0x4dd072,
81 	.mask = 0xffffffef,
82 	.features = PHY_GBIT_FEATURES,
83 	.config = ar8035_config,
84 	.startup = genphy_startup,
85 	.shutdown = genphy_shutdown,
86 };
87 
88 int phy_atheros_init(void)
89 {
90 	phy_register(&AR8021_driver);
91 	phy_register(&AR8031_driver);
92 	phy_register(&AR8035_driver);
93 
94 	return 0;
95 }
96