1 /* 2 * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de. 3 * 4 * This driver for AMD PCnet network controllers is derived from the 5 * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <malloc.h> 28 #include <net.h> 29 #include <asm/io.h> 30 #include <pci.h> 31 32 #if 0 33 #define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */ 34 #endif 35 36 #if PCNET_DEBUG_LEVEL > 0 37 #define PCNET_DEBUG1(fmt,args...) printf (fmt ,##args) 38 #if PCNET_DEBUG_LEVEL > 1 39 #define PCNET_DEBUG2(fmt,args...) printf (fmt ,##args) 40 #else 41 #define PCNET_DEBUG2(fmt,args...) 42 #endif 43 #else 44 #define PCNET_DEBUG1(fmt,args...) 45 #define PCNET_DEBUG2(fmt,args...) 46 #endif 47 48 #if defined(CONFIG_CMD_NET) \ 49 && defined(CONFIG_NET_MULTI) && defined(CONFIG_PCNET) 50 51 #if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975) 52 #error "Macro for PCnet chip version is not defined!" 53 #endif 54 55 /* 56 * Set the number of Tx and Rx buffers, using Log_2(# buffers). 57 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers. 58 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4). 59 */ 60 #define PCNET_LOG_TX_BUFFERS 0 61 #define PCNET_LOG_RX_BUFFERS 2 62 63 #define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS)) 64 #define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12) 65 66 #define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS)) 67 #define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4) 68 69 #define PKT_BUF_SZ 1544 70 71 /* The PCNET Rx and Tx ring descriptors. */ 72 struct pcnet_rx_head { 73 u32 base; 74 s16 buf_length; 75 s16 status; 76 u32 msg_length; 77 u32 reserved; 78 }; 79 80 struct pcnet_tx_head { 81 u32 base; 82 s16 length; 83 s16 status; 84 u32 misc; 85 u32 reserved; 86 }; 87 88 /* The PCNET 32-Bit initialization block, described in databook. */ 89 struct pcnet_init_block { 90 u16 mode; 91 u16 tlen_rlen; 92 u8 phys_addr[6]; 93 u16 reserved; 94 u32 filter[2]; 95 /* Receive and transmit ring base, along with extra bits. */ 96 u32 rx_ring; 97 u32 tx_ring; 98 u32 reserved2; 99 }; 100 101 typedef struct pcnet_priv { 102 struct pcnet_rx_head rx_ring[RX_RING_SIZE]; 103 struct pcnet_tx_head tx_ring[TX_RING_SIZE]; 104 struct pcnet_init_block init_block; 105 /* Receive Buffer space */ 106 unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4]; 107 int cur_rx; 108 int cur_tx; 109 } pcnet_priv_t; 110 111 static pcnet_priv_t *lp; 112 113 /* Offsets from base I/O address for WIO mode */ 114 #define PCNET_RDP 0x10 115 #define PCNET_RAP 0x12 116 #define PCNET_RESET 0x14 117 #define PCNET_BDP 0x16 118 119 static u16 pcnet_read_csr (struct eth_device *dev, int index) 120 { 121 outw (index, dev->iobase+PCNET_RAP); 122 return inw (dev->iobase+PCNET_RDP); 123 } 124 125 static void pcnet_write_csr (struct eth_device *dev, int index, u16 val) 126 { 127 outw (index, dev->iobase+PCNET_RAP); 128 outw (val, dev->iobase+PCNET_RDP); 129 } 130 131 static u16 pcnet_read_bcr (struct eth_device *dev, int index) 132 { 133 outw (index, dev->iobase+PCNET_RAP); 134 return inw (dev->iobase+PCNET_BDP); 135 } 136 137 static void pcnet_write_bcr (struct eth_device *dev, int index, u16 val) 138 { 139 outw (index, dev->iobase+PCNET_RAP); 140 outw (val, dev->iobase+PCNET_BDP); 141 } 142 143 static void pcnet_reset (struct eth_device *dev) 144 { 145 inw (dev->iobase+PCNET_RESET); 146 } 147 148 static int pcnet_check (struct eth_device *dev) 149 { 150 outw (88, dev->iobase+PCNET_RAP); 151 return (inw (dev->iobase+PCNET_RAP) == 88); 152 } 153 154 static int pcnet_init( struct eth_device* dev, bd_t *bis); 155 static int pcnet_send (struct eth_device* dev, volatile void *packet, 156 int length); 157 static int pcnet_recv (struct eth_device* dev); 158 static void pcnet_halt (struct eth_device* dev); 159 static int pcnet_probe(struct eth_device* dev, bd_t *bis, int dev_num); 160 161 #define PCI_TO_MEM(d,a) pci_phys_to_mem((pci_dev_t)d->priv, (u_long)(a)) 162 #define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a))) 163 164 static struct pci_device_id supported[] = { 165 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE }, 166 { } 167 }; 168 169 170 int pcnet_initialize(bd_t *bis) 171 { 172 pci_dev_t devbusfn; 173 struct eth_device* dev; 174 u16 command, status; 175 int dev_nr = 0; 176 177 PCNET_DEBUG1("\npcnet_initialize...\n"); 178 179 for (dev_nr = 0; ; dev_nr++) { 180 181 /* 182 * Find the PCnet PCI device(s). 183 */ 184 if ((devbusfn = pci_find_devices(supported, dev_nr)) < 0) { 185 break; 186 } 187 188 /* 189 * Allocate and pre-fill the device structure. 190 */ 191 dev = (struct eth_device*) malloc(sizeof *dev); 192 dev->priv = (void *)devbusfn; 193 sprintf(dev->name, "pcnet#%d", dev_nr); 194 195 /* 196 * Setup the PCI device. 197 */ 198 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (unsigned int *)&dev->iobase); 199 dev->iobase &= ~0xf; 200 201 PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%x: ", 202 dev->name, devbusfn, dev->iobase); 203 204 command = PCI_COMMAND_IO | PCI_COMMAND_MASTER; 205 pci_write_config_word(devbusfn, PCI_COMMAND, command); 206 pci_read_config_word(devbusfn, PCI_COMMAND, &status); 207 if ((status & command) != command) { 208 printf("%s: Couldn't enable IO access or Bus Mastering\n", 209 dev->name); 210 free(dev); 211 continue; 212 } 213 214 pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40); 215 216 /* 217 * Probe the PCnet chip. 218 */ 219 if (pcnet_probe(dev, bis, dev_nr) < 0) { 220 free(dev); 221 continue; 222 } 223 224 /* 225 * Setup device structure and register the driver. 226 */ 227 dev->init = pcnet_init; 228 dev->halt = pcnet_halt; 229 dev->send = pcnet_send; 230 dev->recv = pcnet_recv; 231 232 eth_register(dev); 233 } 234 235 udelay(10 * 1000); 236 237 return dev_nr; 238 } 239 240 static int pcnet_probe(struct eth_device* dev, bd_t *bis, int dev_nr) 241 { 242 int chip_version; 243 char *chipname; 244 #ifdef PCNET_HAS_PROM 245 int i; 246 #endif 247 248 /* Reset the PCnet controller */ 249 pcnet_reset(dev); 250 251 /* Check if register access is working */ 252 if (pcnet_read_csr(dev, 0) != 4 || !pcnet_check(dev)) { 253 printf("%s: CSR register access check failed\n", dev->name); 254 return -1; 255 } 256 257 /* Identify the chip */ 258 chip_version = pcnet_read_csr(dev, 88) | (pcnet_read_csr(dev,89) << 16); 259 if ((chip_version & 0xfff) != 0x003) 260 return -1; 261 chip_version = (chip_version >> 12) & 0xffff; 262 switch (chip_version) { 263 case 0x2621: 264 chipname = "PCnet/PCI II 79C970A"; /* PCI */ 265 break; 266 #ifdef CONFIG_PCNET_79C973 267 case 0x2625: 268 chipname = "PCnet/FAST III 79C973"; /* PCI */ 269 break; 270 #endif 271 #ifdef CONFIG_PCNET_79C975 272 case 0x2627: 273 chipname = "PCnet/FAST III 79C975"; /* PCI */ 274 break; 275 #endif 276 default: 277 printf("%s: PCnet version %#x not supported\n", 278 dev->name, chip_version); 279 return -1; 280 } 281 282 PCNET_DEBUG1("AMD %s\n", chipname); 283 284 #ifdef PCNET_HAS_PROM 285 /* 286 * In most chips, after a chip reset, the ethernet address is read from 287 * the station address PROM at the base address and programmed into the 288 * "Physical Address Registers" CSR12-14. 289 */ 290 for (i = 0; i < 3; i++) { 291 unsigned int val; 292 val = pcnet_read_csr(dev, i+12) & 0x0ffff; 293 /* There may be endianness issues here. */ 294 dev->enetaddr[2*i ] = val & 0x0ff; 295 dev->enetaddr[2*i+1] = (val >> 8) & 0x0ff; 296 } 297 #endif /* PCNET_HAS_PROM */ 298 299 return 0; 300 } 301 302 static int pcnet_init(struct eth_device* dev, bd_t *bis) 303 { 304 int i, val; 305 u32 addr; 306 307 PCNET_DEBUG1("%s: pcnet_init...\n", dev->name); 308 309 /* Switch pcnet to 32bit mode */ 310 pcnet_write_bcr (dev, 20, 2); 311 312 #ifdef CONFIG_PN62 313 /* Setup LED registers */ 314 val = pcnet_read_bcr (dev, 2) | 0x1000; 315 pcnet_write_bcr (dev, 2, val); /* enable LEDPE */ 316 pcnet_write_bcr (dev, 4, 0x5080); /* 100MBit */ 317 pcnet_write_bcr (dev, 5, 0x40c0); /* LNKSE */ 318 pcnet_write_bcr (dev, 6, 0x4090); /* TX Activity */ 319 pcnet_write_bcr (dev, 7, 0x4084); /* RX Activity */ 320 #endif 321 322 /* Set/reset autoselect bit */ 323 val = pcnet_read_bcr (dev, 2) & ~2; 324 val |= 2; 325 pcnet_write_bcr (dev, 2, val); 326 327 /* Enable auto negotiate, setup, disable fd */ 328 val = pcnet_read_bcr(dev, 32) & ~0x98; 329 val |= 0x20; 330 pcnet_write_bcr(dev, 32, val); 331 332 /* 333 * We only maintain one structure because the drivers will never 334 * be used concurrently. In 32bit mode the RX and TX ring entries 335 * must be aligned on 16-byte boundaries. 336 */ 337 if (lp == NULL) { 338 addr = (u32)malloc(sizeof(pcnet_priv_t) + 0x10); 339 addr = (addr + 0xf) & ~0xf; 340 lp = (pcnet_priv_t *)addr; 341 } 342 343 lp->init_block.mode = cpu_to_le16(0x0000); 344 lp->init_block.filter[0] = 0x00000000; 345 lp->init_block.filter[1] = 0x00000000; 346 347 /* 348 * Initialize the Rx ring. 349 */ 350 lp->cur_rx = 0; 351 for (i = 0; i < RX_RING_SIZE; i++) { 352 lp->rx_ring[i].base = PCI_TO_MEM_LE(dev, lp->rx_buf[i]); 353 lp->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ); 354 lp->rx_ring[i].status = cpu_to_le16(0x8000); 355 PCNET_DEBUG1("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", 356 i, lp->rx_ring[i].base, lp->rx_ring[i].buf_length, 357 lp->rx_ring[i].status); 358 } 359 360 /* 361 * Initialize the Tx ring. The Tx buffer address is filled in as 362 * needed, but we do need to clear the upper ownership bit. 363 */ 364 lp->cur_tx = 0; 365 for (i = 0; i < TX_RING_SIZE; i++) { 366 lp->tx_ring[i].base = 0; 367 lp->tx_ring[i].status = 0; 368 } 369 370 /* 371 * Setup Init Block. 372 */ 373 PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->init_block); 374 375 for (i = 0; i < 6; i++) { 376 lp->init_block.phys_addr[i] = dev->enetaddr[i]; 377 PCNET_DEBUG1(" %02x", lp->init_block.phys_addr[i]); 378 } 379 380 lp->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS | 381 RX_RING_LEN_BITS); 382 lp->init_block.rx_ring = PCI_TO_MEM_LE(dev, lp->rx_ring); 383 lp->init_block.tx_ring = PCI_TO_MEM_LE(dev, lp->tx_ring); 384 385 PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n", 386 lp->init_block.tlen_rlen, 387 lp->init_block.rx_ring, lp->init_block.tx_ring); 388 389 /* 390 * Tell the controller where the Init Block is located. 391 */ 392 addr = PCI_TO_MEM(dev, &lp->init_block); 393 pcnet_write_csr(dev, 1, addr & 0xffff); 394 pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff); 395 396 pcnet_write_csr (dev, 4, 0x0915); 397 pcnet_write_csr (dev, 0, 0x0001); /* start */ 398 399 /* Wait for Init Done bit */ 400 for (i = 10000; i > 0; i--) { 401 if (pcnet_read_csr (dev, 0) & 0x0100) 402 break; 403 udelay(10); 404 } 405 if (i <= 0) { 406 printf("%s: TIMEOUT: controller init failed\n", dev->name); 407 pcnet_reset (dev); 408 return -1; 409 } 410 411 /* 412 * Finally start network controller operation. 413 */ 414 pcnet_write_csr (dev, 0, 0x0002); 415 416 return 0; 417 } 418 419 static int pcnet_send(struct eth_device* dev, volatile void *packet, int pkt_len) 420 { 421 int i, status; 422 struct pcnet_tx_head *entry = &lp->tx_ring[lp->cur_tx]; 423 424 PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len, packet); 425 426 /* Wait for completion by testing the OWN bit */ 427 for (i = 1000; i > 0; i--) { 428 status = le16_to_cpu(entry->status); 429 if ((status & 0x8000) == 0) 430 break; 431 udelay(100); 432 PCNET_DEBUG2("."); 433 } 434 if (i <= 0) { 435 printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n", 436 dev->name, lp->cur_tx, status); 437 pkt_len = 0; 438 goto failure; 439 } 440 441 /* 442 * Setup Tx ring. Caution: the write order is important here, 443 * set the status with the "ownership" bits last. 444 */ 445 status = 0x8300; 446 entry->length = le16_to_cpu(-pkt_len); 447 entry->misc = 0x00000000; 448 entry->base = PCI_TO_MEM_LE(dev, packet); 449 entry->status = le16_to_cpu(status); 450 451 /* Trigger an immediate send poll. */ 452 pcnet_write_csr (dev, 0, 0x0008); 453 454 failure: 455 if (++lp->cur_tx >= TX_RING_SIZE) 456 lp->cur_tx = 0; 457 458 PCNET_DEBUG2("done\n"); 459 return pkt_len; 460 } 461 462 static int pcnet_recv(struct eth_device* dev) 463 { 464 struct pcnet_rx_head *entry; 465 int pkt_len = 0; 466 u16 status; 467 468 while (1) { 469 entry = &lp->rx_ring[lp->cur_rx]; 470 /* 471 * If we own the next entry, it's a new packet. Send it up. 472 */ 473 if (((status = le16_to_cpu(entry->status)) & 0x8000) != 0) { 474 break; 475 } 476 status >>= 8; 477 478 if (status != 0x03) { /* There was an error. */ 479 480 printf("%s: Rx%d", dev->name, lp->cur_rx); 481 PCNET_DEBUG1(" (status=0x%x)", status); 482 if (status & 0x20) printf(" Frame"); 483 if (status & 0x10) printf(" Overflow"); 484 if (status & 0x08) printf(" CRC"); 485 if (status & 0x04) printf(" Fifo"); 486 printf(" Error\n"); 487 entry->status &= le16_to_cpu(0x03ff); 488 489 } else { 490 491 pkt_len = (le32_to_cpu(entry->msg_length) & 0xfff) - 4; 492 if (pkt_len < 60) { 493 printf("%s: Rx%d: invalid packet length %d\n", 494 dev->name, lp->cur_rx, pkt_len); 495 } else { 496 NetReceive(lp->rx_buf[lp->cur_rx], pkt_len); 497 PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n", 498 lp->cur_rx, pkt_len, lp->rx_buf[lp->cur_rx]); 499 } 500 } 501 entry->status |= cpu_to_le16(0x8000); 502 503 if (++lp->cur_rx >= RX_RING_SIZE) 504 lp->cur_rx = 0; 505 } 506 return pkt_len; 507 } 508 509 static void pcnet_halt(struct eth_device* dev) 510 { 511 int i; 512 513 PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name); 514 515 /* Reset the PCnet controller */ 516 pcnet_reset (dev); 517 518 /* Wait for Stop bit */ 519 for (i = 1000; i > 0; i--) { 520 if (pcnet_read_csr (dev, 0) & 0x4) 521 break; 522 udelay(10); 523 } 524 if (i <= 0) { 525 printf("%s: TIMEOUT: controller reset failed\n", dev->name); 526 } 527 } 528 529 #endif 530