1 /* 2 * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de. 3 * 4 * This driver for AMD PCnet network controllers is derived from the 5 * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <malloc.h> 12 #include <net.h> 13 #include <netdev.h> 14 #include <asm/io.h> 15 #include <pci.h> 16 17 #define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */ 18 19 #define PCNET_DEBUG1(fmt,args...) \ 20 debug_cond(PCNET_DEBUG_LEVEL > 0, fmt ,##args) 21 #define PCNET_DEBUG2(fmt,args...) \ 22 debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args) 23 24 #if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975) 25 #error "Macro for PCnet chip version is not defined!" 26 #endif 27 28 /* 29 * Set the number of Tx and Rx buffers, using Log_2(# buffers). 30 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers. 31 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4). 32 */ 33 #define PCNET_LOG_TX_BUFFERS 0 34 #define PCNET_LOG_RX_BUFFERS 2 35 36 #define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS)) 37 #define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12) 38 39 #define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS)) 40 #define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4) 41 42 #define PKT_BUF_SZ 1544 43 44 /* The PCNET Rx and Tx ring descriptors. */ 45 struct pcnet_rx_head { 46 u32 base; 47 s16 buf_length; 48 s16 status; 49 u32 msg_length; 50 u32 reserved; 51 }; 52 53 struct pcnet_tx_head { 54 u32 base; 55 s16 length; 56 s16 status; 57 u32 misc; 58 u32 reserved; 59 }; 60 61 /* The PCNET 32-Bit initialization block, described in databook. */ 62 struct pcnet_init_block { 63 u16 mode; 64 u16 tlen_rlen; 65 u8 phys_addr[6]; 66 u16 reserved; 67 u32 filter[2]; 68 /* Receive and transmit ring base, along with extra bits. */ 69 u32 rx_ring; 70 u32 tx_ring; 71 u32 reserved2; 72 }; 73 74 typedef struct pcnet_priv { 75 struct pcnet_rx_head rx_ring[RX_RING_SIZE]; 76 struct pcnet_tx_head tx_ring[TX_RING_SIZE]; 77 struct pcnet_init_block init_block; 78 /* Receive Buffer space */ 79 unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4]; 80 int cur_rx; 81 int cur_tx; 82 } pcnet_priv_t; 83 84 static pcnet_priv_t *lp; 85 86 /* Offsets from base I/O address for WIO mode */ 87 #define PCNET_RDP 0x10 88 #define PCNET_RAP 0x12 89 #define PCNET_RESET 0x14 90 #define PCNET_BDP 0x16 91 92 static u16 pcnet_read_csr(struct eth_device *dev, int index) 93 { 94 outw(index, dev->iobase + PCNET_RAP); 95 return inw(dev->iobase + PCNET_RDP); 96 } 97 98 static void pcnet_write_csr(struct eth_device *dev, int index, u16 val) 99 { 100 outw(index, dev->iobase + PCNET_RAP); 101 outw(val, dev->iobase + PCNET_RDP); 102 } 103 104 static u16 pcnet_read_bcr(struct eth_device *dev, int index) 105 { 106 outw(index, dev->iobase + PCNET_RAP); 107 return inw(dev->iobase + PCNET_BDP); 108 } 109 110 static void pcnet_write_bcr(struct eth_device *dev, int index, u16 val) 111 { 112 outw(index, dev->iobase + PCNET_RAP); 113 outw(val, dev->iobase + PCNET_BDP); 114 } 115 116 static void pcnet_reset(struct eth_device *dev) 117 { 118 inw(dev->iobase + PCNET_RESET); 119 } 120 121 static int pcnet_check(struct eth_device *dev) 122 { 123 outw(88, dev->iobase + PCNET_RAP); 124 return inw(dev->iobase + PCNET_RAP) == 88; 125 } 126 127 static int pcnet_init (struct eth_device *dev, bd_t * bis); 128 static int pcnet_send(struct eth_device *dev, void *packet, int length); 129 static int pcnet_recv (struct eth_device *dev); 130 static void pcnet_halt (struct eth_device *dev); 131 static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num); 132 133 #define PCI_TO_MEM(d, a) pci_virt_to_mem((pci_dev_t)d->priv, (a)) 134 #define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a))) 135 136 static struct pci_device_id supported[] = { 137 {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE}, 138 {} 139 }; 140 141 142 int pcnet_initialize(bd_t *bis) 143 { 144 pci_dev_t devbusfn; 145 struct eth_device *dev; 146 u16 command, status; 147 int dev_nr = 0; 148 149 PCNET_DEBUG1("\npcnet_initialize...\n"); 150 151 for (dev_nr = 0;; dev_nr++) { 152 153 /* 154 * Find the PCnet PCI device(s). 155 */ 156 devbusfn = pci_find_devices(supported, dev_nr); 157 if (devbusfn < 0) 158 break; 159 160 /* 161 * Allocate and pre-fill the device structure. 162 */ 163 dev = (struct eth_device *)malloc(sizeof(*dev)); 164 if (!dev) { 165 printf("pcnet: Can not allocate memory\n"); 166 break; 167 } 168 memset(dev, 0, sizeof(*dev)); 169 dev->priv = (void *)devbusfn; 170 sprintf(dev->name, "pcnet#%d", dev_nr); 171 172 /* 173 * Setup the PCI device. 174 */ 175 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, 176 (unsigned int *)&dev->iobase); 177 dev->iobase = pci_io_to_phys(devbusfn, dev->iobase); 178 dev->iobase &= ~0xf; 179 180 PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%x: ", 181 dev->name, devbusfn, dev->iobase); 182 183 command = PCI_COMMAND_IO | PCI_COMMAND_MASTER; 184 pci_write_config_word(devbusfn, PCI_COMMAND, command); 185 pci_read_config_word(devbusfn, PCI_COMMAND, &status); 186 if ((status & command) != command) { 187 printf("%s: Couldn't enable IO access or Bus Mastering\n", 188 dev->name); 189 free(dev); 190 continue; 191 } 192 193 pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40); 194 195 /* 196 * Probe the PCnet chip. 197 */ 198 if (pcnet_probe(dev, bis, dev_nr) < 0) { 199 free(dev); 200 continue; 201 } 202 203 /* 204 * Setup device structure and register the driver. 205 */ 206 dev->init = pcnet_init; 207 dev->halt = pcnet_halt; 208 dev->send = pcnet_send; 209 dev->recv = pcnet_recv; 210 211 eth_register(dev); 212 } 213 214 udelay(10 * 1000); 215 216 return dev_nr; 217 } 218 219 static int pcnet_probe(struct eth_device *dev, bd_t *bis, int dev_nr) 220 { 221 int chip_version; 222 char *chipname; 223 224 #ifdef PCNET_HAS_PROM 225 int i; 226 #endif 227 228 /* Reset the PCnet controller */ 229 pcnet_reset(dev); 230 231 /* Check if register access is working */ 232 if (pcnet_read_csr(dev, 0) != 4 || !pcnet_check(dev)) { 233 printf("%s: CSR register access check failed\n", dev->name); 234 return -1; 235 } 236 237 /* Identify the chip */ 238 chip_version = 239 pcnet_read_csr(dev, 88) | (pcnet_read_csr(dev, 89) << 16); 240 if ((chip_version & 0xfff) != 0x003) 241 return -1; 242 chip_version = (chip_version >> 12) & 0xffff; 243 switch (chip_version) { 244 case 0x2621: 245 chipname = "PCnet/PCI II 79C970A"; /* PCI */ 246 break; 247 #ifdef CONFIG_PCNET_79C973 248 case 0x2625: 249 chipname = "PCnet/FAST III 79C973"; /* PCI */ 250 break; 251 #endif 252 #ifdef CONFIG_PCNET_79C975 253 case 0x2627: 254 chipname = "PCnet/FAST III 79C975"; /* PCI */ 255 break; 256 #endif 257 default: 258 printf("%s: PCnet version %#x not supported\n", 259 dev->name, chip_version); 260 return -1; 261 } 262 263 PCNET_DEBUG1("AMD %s\n", chipname); 264 265 #ifdef PCNET_HAS_PROM 266 /* 267 * In most chips, after a chip reset, the ethernet address is read from 268 * the station address PROM at the base address and programmed into the 269 * "Physical Address Registers" CSR12-14. 270 */ 271 for (i = 0; i < 3; i++) { 272 unsigned int val; 273 274 val = pcnet_read_csr(dev, i + 12) & 0x0ffff; 275 /* There may be endianness issues here. */ 276 dev->enetaddr[2 * i] = val & 0x0ff; 277 dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff; 278 } 279 #endif /* PCNET_HAS_PROM */ 280 281 return 0; 282 } 283 284 static int pcnet_init(struct eth_device *dev, bd_t *bis) 285 { 286 int i, val; 287 u32 addr; 288 289 PCNET_DEBUG1("%s: pcnet_init...\n", dev->name); 290 291 /* Switch pcnet to 32bit mode */ 292 pcnet_write_bcr(dev, 20, 2); 293 294 #ifdef CONFIG_PN62 295 /* Setup LED registers */ 296 val = pcnet_read_bcr(dev, 2) | 0x1000; 297 pcnet_write_bcr(dev, 2, val); /* enable LEDPE */ 298 pcnet_write_bcr(dev, 4, 0x5080); /* 100MBit */ 299 pcnet_write_bcr(dev, 5, 0x40c0); /* LNKSE */ 300 pcnet_write_bcr(dev, 6, 0x4090); /* TX Activity */ 301 pcnet_write_bcr(dev, 7, 0x4084); /* RX Activity */ 302 #endif 303 304 /* Set/reset autoselect bit */ 305 val = pcnet_read_bcr(dev, 2) & ~2; 306 val |= 2; 307 pcnet_write_bcr(dev, 2, val); 308 309 /* Enable auto negotiate, setup, disable fd */ 310 val = pcnet_read_bcr(dev, 32) & ~0x98; 311 val |= 0x20; 312 pcnet_write_bcr(dev, 32, val); 313 314 /* 315 * We only maintain one structure because the drivers will never 316 * be used concurrently. In 32bit mode the RX and TX ring entries 317 * must be aligned on 16-byte boundaries. 318 */ 319 if (lp == NULL) { 320 addr = (u32)malloc(sizeof(pcnet_priv_t) + 0x10); 321 addr = (addr + 0xf) & ~0xf; 322 lp = (pcnet_priv_t *)addr; 323 } 324 325 lp->init_block.mode = cpu_to_le16(0x0000); 326 lp->init_block.filter[0] = 0x00000000; 327 lp->init_block.filter[1] = 0x00000000; 328 329 /* 330 * Initialize the Rx ring. 331 */ 332 lp->cur_rx = 0; 333 for (i = 0; i < RX_RING_SIZE; i++) { 334 lp->rx_ring[i].base = PCI_TO_MEM_LE(dev, lp->rx_buf[i]); 335 lp->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ); 336 lp->rx_ring[i].status = cpu_to_le16(0x8000); 337 PCNET_DEBUG1 338 ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i, 339 lp->rx_ring[i].base, lp->rx_ring[i].buf_length, 340 lp->rx_ring[i].status); 341 } 342 343 /* 344 * Initialize the Tx ring. The Tx buffer address is filled in as 345 * needed, but we do need to clear the upper ownership bit. 346 */ 347 lp->cur_tx = 0; 348 for (i = 0; i < TX_RING_SIZE; i++) { 349 lp->tx_ring[i].base = 0; 350 lp->tx_ring[i].status = 0; 351 } 352 353 /* 354 * Setup Init Block. 355 */ 356 PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->init_block); 357 358 for (i = 0; i < 6; i++) { 359 lp->init_block.phys_addr[i] = dev->enetaddr[i]; 360 PCNET_DEBUG1(" %02x", lp->init_block.phys_addr[i]); 361 } 362 363 lp->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS | 364 RX_RING_LEN_BITS); 365 lp->init_block.rx_ring = PCI_TO_MEM_LE(dev, lp->rx_ring); 366 lp->init_block.tx_ring = PCI_TO_MEM_LE(dev, lp->tx_ring); 367 368 PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n", 369 lp->init_block.tlen_rlen, 370 lp->init_block.rx_ring, lp->init_block.tx_ring); 371 372 /* 373 * Tell the controller where the Init Block is located. 374 */ 375 addr = PCI_TO_MEM(dev, &lp->init_block); 376 pcnet_write_csr(dev, 1, addr & 0xffff); 377 pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff); 378 379 pcnet_write_csr(dev, 4, 0x0915); 380 pcnet_write_csr(dev, 0, 0x0001); /* start */ 381 382 /* Wait for Init Done bit */ 383 for (i = 10000; i > 0; i--) { 384 if (pcnet_read_csr(dev, 0) & 0x0100) 385 break; 386 udelay(10); 387 } 388 if (i <= 0) { 389 printf("%s: TIMEOUT: controller init failed\n", dev->name); 390 pcnet_reset(dev); 391 return -1; 392 } 393 394 /* 395 * Finally start network controller operation. 396 */ 397 pcnet_write_csr(dev, 0, 0x0002); 398 399 return 0; 400 } 401 402 static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len) 403 { 404 int i, status; 405 struct pcnet_tx_head *entry = &lp->tx_ring[lp->cur_tx]; 406 407 PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len, 408 packet); 409 410 /* Wait for completion by testing the OWN bit */ 411 for (i = 1000; i > 0; i--) { 412 status = le16_to_cpu(entry->status); 413 if ((status & 0x8000) == 0) 414 break; 415 udelay(100); 416 PCNET_DEBUG2("."); 417 } 418 if (i <= 0) { 419 printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n", 420 dev->name, lp->cur_tx, status); 421 pkt_len = 0; 422 goto failure; 423 } 424 425 /* 426 * Setup Tx ring. Caution: the write order is important here, 427 * set the status with the "ownership" bits last. 428 */ 429 status = 0x8300; 430 entry->length = le16_to_cpu(-pkt_len); 431 entry->misc = 0x00000000; 432 entry->base = PCI_TO_MEM_LE(dev, packet); 433 entry->status = le16_to_cpu(status); 434 435 /* Trigger an immediate send poll. */ 436 pcnet_write_csr(dev, 0, 0x0008); 437 438 failure: 439 if (++lp->cur_tx >= TX_RING_SIZE) 440 lp->cur_tx = 0; 441 442 PCNET_DEBUG2("done\n"); 443 return pkt_len; 444 } 445 446 static int pcnet_recv (struct eth_device *dev) 447 { 448 struct pcnet_rx_head *entry; 449 int pkt_len = 0; 450 u16 status; 451 452 while (1) { 453 entry = &lp->rx_ring[lp->cur_rx]; 454 /* 455 * If we own the next entry, it's a new packet. Send it up. 456 */ 457 status = le16_to_cpu(entry->status); 458 if ((status & 0x8000) != 0) 459 break; 460 status >>= 8; 461 462 if (status != 0x03) { /* There was an error. */ 463 printf("%s: Rx%d", dev->name, lp->cur_rx); 464 PCNET_DEBUG1(" (status=0x%x)", status); 465 if (status & 0x20) 466 printf(" Frame"); 467 if (status & 0x10) 468 printf(" Overflow"); 469 if (status & 0x08) 470 printf(" CRC"); 471 if (status & 0x04) 472 printf(" Fifo"); 473 printf(" Error\n"); 474 entry->status &= le16_to_cpu(0x03ff); 475 476 } else { 477 pkt_len = (le32_to_cpu(entry->msg_length) & 0xfff) - 4; 478 if (pkt_len < 60) { 479 printf("%s: Rx%d: invalid packet length %d\n", 480 dev->name, lp->cur_rx, pkt_len); 481 } else { 482 NetReceive(lp->rx_buf[lp->cur_rx], pkt_len); 483 PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n", 484 lp->cur_rx, pkt_len, 485 lp->rx_buf[lp->cur_rx]); 486 } 487 } 488 entry->status |= cpu_to_le16(0x8000); 489 490 if (++lp->cur_rx >= RX_RING_SIZE) 491 lp->cur_rx = 0; 492 } 493 return pkt_len; 494 } 495 496 static void pcnet_halt(struct eth_device *dev) 497 { 498 int i; 499 500 PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name); 501 502 /* Reset the PCnet controller */ 503 pcnet_reset(dev); 504 505 /* Wait for Stop bit */ 506 for (i = 1000; i > 0; i--) { 507 if (pcnet_read_csr(dev, 0) & 0x4) 508 break; 509 udelay(10); 510 } 511 if (i <= 0) 512 printf("%s: TIMEOUT: controller reset failed\n", dev->name); 513 } 514