1 /* 2 * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de. 3 * 4 * This driver for AMD PCnet network controllers is derived from the 5 * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <malloc.h> 28 #include <net.h> 29 #include <asm/io.h> 30 #include <pci.h> 31 32 #if 0 33 #define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */ 34 #endif 35 36 #if PCNET_DEBUG_LEVEL > 0 37 #define PCNET_DEBUG1(fmt,args...) printf (fmt ,##args) 38 #if PCNET_DEBUG_LEVEL > 1 39 #define PCNET_DEBUG2(fmt,args...) printf (fmt ,##args) 40 #else 41 #define PCNET_DEBUG2(fmt,args...) 42 #endif 43 #else 44 #define PCNET_DEBUG1(fmt,args...) 45 #define PCNET_DEBUG2(fmt,args...) 46 #endif 47 48 #if defined(CONFIG_CMD_NET) \ 49 && defined(CONFIG_NET_MULTI) && defined(CONFIG_PCNET) 50 51 #if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975) 52 #error "Macro for PCnet chip version is not defined!" 53 #endif 54 55 /* 56 * Set the number of Tx and Rx buffers, using Log_2(# buffers). 57 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers. 58 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4). 59 */ 60 #define PCNET_LOG_TX_BUFFERS 0 61 #define PCNET_LOG_RX_BUFFERS 2 62 63 #define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS)) 64 #define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12) 65 66 #define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS)) 67 #define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4) 68 69 #define PKT_BUF_SZ 1544 70 71 /* The PCNET Rx and Tx ring descriptors. */ 72 struct pcnet_rx_head { 73 u32 base; 74 s16 buf_length; 75 s16 status; 76 u32 msg_length; 77 u32 reserved; 78 }; 79 80 struct pcnet_tx_head { 81 u32 base; 82 s16 length; 83 s16 status; 84 u32 misc; 85 u32 reserved; 86 }; 87 88 /* The PCNET 32-Bit initialization block, described in databook. */ 89 struct pcnet_init_block { 90 u16 mode; 91 u16 tlen_rlen; 92 u8 phys_addr[6]; 93 u16 reserved; 94 u32 filter[2]; 95 /* Receive and transmit ring base, along with extra bits. */ 96 u32 rx_ring; 97 u32 tx_ring; 98 u32 reserved2; 99 }; 100 101 typedef struct pcnet_priv { 102 struct pcnet_rx_head rx_ring[RX_RING_SIZE]; 103 struct pcnet_tx_head tx_ring[TX_RING_SIZE]; 104 struct pcnet_init_block init_block; 105 /* Receive Buffer space */ 106 unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4]; 107 int cur_rx; 108 int cur_tx; 109 } pcnet_priv_t; 110 111 static pcnet_priv_t *lp; 112 113 /* Offsets from base I/O address for WIO mode */ 114 #define PCNET_RDP 0x10 115 #define PCNET_RAP 0x12 116 #define PCNET_RESET 0x14 117 #define PCNET_BDP 0x16 118 119 static u16 pcnet_read_csr (struct eth_device *dev, int index) 120 { 121 outw (index, dev->iobase + PCNET_RAP); 122 return inw (dev->iobase + PCNET_RDP); 123 } 124 125 static void pcnet_write_csr (struct eth_device *dev, int index, u16 val) 126 { 127 outw (index, dev->iobase + PCNET_RAP); 128 outw (val, dev->iobase + PCNET_RDP); 129 } 130 131 static u16 pcnet_read_bcr (struct eth_device *dev, int index) 132 { 133 outw (index, dev->iobase + PCNET_RAP); 134 return inw (dev->iobase + PCNET_BDP); 135 } 136 137 static void pcnet_write_bcr (struct eth_device *dev, int index, u16 val) 138 { 139 outw (index, dev->iobase + PCNET_RAP); 140 outw (val, dev->iobase + PCNET_BDP); 141 } 142 143 static void pcnet_reset (struct eth_device *dev) 144 { 145 inw (dev->iobase + PCNET_RESET); 146 } 147 148 static int pcnet_check (struct eth_device *dev) 149 { 150 outw (88, dev->iobase + PCNET_RAP); 151 return (inw (dev->iobase + PCNET_RAP) == 88); 152 } 153 154 static int pcnet_init (struct eth_device *dev, bd_t * bis); 155 static int pcnet_send (struct eth_device *dev, volatile void *packet, 156 int length); 157 static int pcnet_recv (struct eth_device *dev); 158 static void pcnet_halt (struct eth_device *dev); 159 static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num); 160 161 #define PCI_TO_MEM(d,a) pci_phys_to_mem((pci_dev_t)d->priv, (u_long)(a)) 162 #define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a))) 163 164 static struct pci_device_id supported[] = { 165 {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE}, 166 {} 167 }; 168 169 170 int pcnet_initialize (bd_t * bis) 171 { 172 pci_dev_t devbusfn; 173 struct eth_device *dev; 174 u16 command, status; 175 int dev_nr = 0; 176 177 PCNET_DEBUG1 ("\npcnet_initialize...\n"); 178 179 for (dev_nr = 0;; dev_nr++) { 180 181 /* 182 * Find the PCnet PCI device(s). 183 */ 184 if ((devbusfn = pci_find_devices (supported, dev_nr)) < 0) { 185 break; 186 } 187 188 /* 189 * Allocate and pre-fill the device structure. 190 */ 191 dev = (struct eth_device *) malloc (sizeof *dev); 192 dev->priv = (void *) devbusfn; 193 sprintf (dev->name, "pcnet#%d", dev_nr); 194 195 /* 196 * Setup the PCI device. 197 */ 198 pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, 199 (unsigned int *) &dev->iobase); 200 dev->iobase &= ~0xf; 201 202 PCNET_DEBUG1 ("%s: devbusfn=0x%x iobase=0x%x: ", 203 dev->name, devbusfn, dev->iobase); 204 205 command = PCI_COMMAND_IO | PCI_COMMAND_MASTER; 206 pci_write_config_word (devbusfn, PCI_COMMAND, command); 207 pci_read_config_word (devbusfn, PCI_COMMAND, &status); 208 if ((status & command) != command) { 209 printf ("%s: Couldn't enable IO access or Bus Mastering\n", dev->name); 210 free (dev); 211 continue; 212 } 213 214 pci_write_config_byte (devbusfn, PCI_LATENCY_TIMER, 0x40); 215 216 /* 217 * Probe the PCnet chip. 218 */ 219 if (pcnet_probe (dev, bis, dev_nr) < 0) { 220 free (dev); 221 continue; 222 } 223 224 /* 225 * Setup device structure and register the driver. 226 */ 227 dev->init = pcnet_init; 228 dev->halt = pcnet_halt; 229 dev->send = pcnet_send; 230 dev->recv = pcnet_recv; 231 232 eth_register (dev); 233 } 234 235 udelay (10 * 1000); 236 237 return dev_nr; 238 } 239 240 static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_nr) 241 { 242 int chip_version; 243 char *chipname; 244 245 #ifdef PCNET_HAS_PROM 246 int i; 247 #endif 248 249 /* Reset the PCnet controller */ 250 pcnet_reset (dev); 251 252 /* Check if register access is working */ 253 if (pcnet_read_csr (dev, 0) != 4 || !pcnet_check (dev)) { 254 printf ("%s: CSR register access check failed\n", dev->name); 255 return -1; 256 } 257 258 /* Identify the chip */ 259 chip_version = 260 pcnet_read_csr (dev, 88) | (pcnet_read_csr (dev, 89) << 16); 261 if ((chip_version & 0xfff) != 0x003) 262 return -1; 263 chip_version = (chip_version >> 12) & 0xffff; 264 switch (chip_version) { 265 case 0x2621: 266 chipname = "PCnet/PCI II 79C970A"; /* PCI */ 267 break; 268 #ifdef CONFIG_PCNET_79C973 269 case 0x2625: 270 chipname = "PCnet/FAST III 79C973"; /* PCI */ 271 break; 272 #endif 273 #ifdef CONFIG_PCNET_79C975 274 case 0x2627: 275 chipname = "PCnet/FAST III 79C975"; /* PCI */ 276 break; 277 #endif 278 default: 279 printf ("%s: PCnet version %#x not supported\n", 280 dev->name, chip_version); 281 return -1; 282 } 283 284 PCNET_DEBUG1 ("AMD %s\n", chipname); 285 286 #ifdef PCNET_HAS_PROM 287 /* 288 * In most chips, after a chip reset, the ethernet address is read from 289 * the station address PROM at the base address and programmed into the 290 * "Physical Address Registers" CSR12-14. 291 */ 292 for (i = 0; i < 3; i++) { 293 unsigned int val; 294 295 val = pcnet_read_csr (dev, i + 12) & 0x0ffff; 296 /* There may be endianness issues here. */ 297 dev->enetaddr[2 * i] = val & 0x0ff; 298 dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff; 299 } 300 #endif /* PCNET_HAS_PROM */ 301 302 return 0; 303 } 304 305 static int pcnet_init (struct eth_device *dev, bd_t * bis) 306 { 307 int i, val; 308 u32 addr; 309 310 PCNET_DEBUG1 ("%s: pcnet_init...\n", dev->name); 311 312 /* Switch pcnet to 32bit mode */ 313 pcnet_write_bcr (dev, 20, 2); 314 315 #ifdef CONFIG_PN62 316 /* Setup LED registers */ 317 val = pcnet_read_bcr (dev, 2) | 0x1000; 318 pcnet_write_bcr (dev, 2, val); /* enable LEDPE */ 319 pcnet_write_bcr (dev, 4, 0x5080); /* 100MBit */ 320 pcnet_write_bcr (dev, 5, 0x40c0); /* LNKSE */ 321 pcnet_write_bcr (dev, 6, 0x4090); /* TX Activity */ 322 pcnet_write_bcr (dev, 7, 0x4084); /* RX Activity */ 323 #endif 324 325 /* Set/reset autoselect bit */ 326 val = pcnet_read_bcr (dev, 2) & ~2; 327 val |= 2; 328 pcnet_write_bcr (dev, 2, val); 329 330 /* Enable auto negotiate, setup, disable fd */ 331 val = pcnet_read_bcr (dev, 32) & ~0x98; 332 val |= 0x20; 333 pcnet_write_bcr (dev, 32, val); 334 335 /* 336 * We only maintain one structure because the drivers will never 337 * be used concurrently. In 32bit mode the RX and TX ring entries 338 * must be aligned on 16-byte boundaries. 339 */ 340 if (lp == NULL) { 341 addr = (u32) malloc (sizeof (pcnet_priv_t) + 0x10); 342 addr = (addr + 0xf) & ~0xf; 343 lp = (pcnet_priv_t *) addr; 344 } 345 346 lp->init_block.mode = cpu_to_le16 (0x0000); 347 lp->init_block.filter[0] = 0x00000000; 348 lp->init_block.filter[1] = 0x00000000; 349 350 /* 351 * Initialize the Rx ring. 352 */ 353 lp->cur_rx = 0; 354 for (i = 0; i < RX_RING_SIZE; i++) { 355 lp->rx_ring[i].base = PCI_TO_MEM_LE (dev, lp->rx_buf[i]); 356 lp->rx_ring[i].buf_length = cpu_to_le16 (-PKT_BUF_SZ); 357 lp->rx_ring[i].status = cpu_to_le16 (0x8000); 358 PCNET_DEBUG1 359 ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i, 360 lp->rx_ring[i].base, lp->rx_ring[i].buf_length, 361 lp->rx_ring[i].status); 362 } 363 364 /* 365 * Initialize the Tx ring. The Tx buffer address is filled in as 366 * needed, but we do need to clear the upper ownership bit. 367 */ 368 lp->cur_tx = 0; 369 for (i = 0; i < TX_RING_SIZE; i++) { 370 lp->tx_ring[i].base = 0; 371 lp->tx_ring[i].status = 0; 372 } 373 374 /* 375 * Setup Init Block. 376 */ 377 PCNET_DEBUG1 ("Init block at 0x%p: MAC", &lp->init_block); 378 379 for (i = 0; i < 6; i++) { 380 lp->init_block.phys_addr[i] = dev->enetaddr[i]; 381 PCNET_DEBUG1 (" %02x", lp->init_block.phys_addr[i]); 382 } 383 384 lp->init_block.tlen_rlen = cpu_to_le16 (TX_RING_LEN_BITS | 385 RX_RING_LEN_BITS); 386 lp->init_block.rx_ring = PCI_TO_MEM_LE (dev, lp->rx_ring); 387 lp->init_block.tx_ring = PCI_TO_MEM_LE (dev, lp->tx_ring); 388 389 PCNET_DEBUG1 ("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n", 390 lp->init_block.tlen_rlen, 391 lp->init_block.rx_ring, lp->init_block.tx_ring); 392 393 /* 394 * Tell the controller where the Init Block is located. 395 */ 396 addr = PCI_TO_MEM (dev, &lp->init_block); 397 pcnet_write_csr (dev, 1, addr & 0xffff); 398 pcnet_write_csr (dev, 2, (addr >> 16) & 0xffff); 399 400 pcnet_write_csr (dev, 4, 0x0915); 401 pcnet_write_csr (dev, 0, 0x0001); /* start */ 402 403 /* Wait for Init Done bit */ 404 for (i = 10000; i > 0; i--) { 405 if (pcnet_read_csr (dev, 0) & 0x0100) 406 break; 407 udelay (10); 408 } 409 if (i <= 0) { 410 printf ("%s: TIMEOUT: controller init failed\n", dev->name); 411 pcnet_reset (dev); 412 return -1; 413 } 414 415 /* 416 * Finally start network controller operation. 417 */ 418 pcnet_write_csr (dev, 0, 0x0002); 419 420 return 0; 421 } 422 423 static int pcnet_send (struct eth_device *dev, volatile void *packet, 424 int pkt_len) 425 { 426 int i, status; 427 struct pcnet_tx_head *entry = &lp->tx_ring[lp->cur_tx]; 428 429 PCNET_DEBUG2 ("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len, 430 packet); 431 432 /* Wait for completion by testing the OWN bit */ 433 for (i = 1000; i > 0; i--) { 434 status = le16_to_cpu (entry->status); 435 if ((status & 0x8000) == 0) 436 break; 437 udelay (100); 438 PCNET_DEBUG2 ("."); 439 } 440 if (i <= 0) { 441 printf ("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n", 442 dev->name, lp->cur_tx, status); 443 pkt_len = 0; 444 goto failure; 445 } 446 447 /* 448 * Setup Tx ring. Caution: the write order is important here, 449 * set the status with the "ownership" bits last. 450 */ 451 status = 0x8300; 452 entry->length = le16_to_cpu (-pkt_len); 453 entry->misc = 0x00000000; 454 entry->base = PCI_TO_MEM_LE (dev, packet); 455 entry->status = le16_to_cpu (status); 456 457 /* Trigger an immediate send poll. */ 458 pcnet_write_csr (dev, 0, 0x0008); 459 460 failure: 461 if (++lp->cur_tx >= TX_RING_SIZE) 462 lp->cur_tx = 0; 463 464 PCNET_DEBUG2 ("done\n"); 465 return pkt_len; 466 } 467 468 static int pcnet_recv (struct eth_device *dev) 469 { 470 struct pcnet_rx_head *entry; 471 int pkt_len = 0; 472 u16 status; 473 474 while (1) { 475 entry = &lp->rx_ring[lp->cur_rx]; 476 /* 477 * If we own the next entry, it's a new packet. Send it up. 478 */ 479 if (((status = le16_to_cpu (entry->status)) & 0x8000) != 0) { 480 break; 481 } 482 status >>= 8; 483 484 if (status != 0x03) { /* There was an error. */ 485 486 printf ("%s: Rx%d", dev->name, lp->cur_rx); 487 PCNET_DEBUG1 (" (status=0x%x)", status); 488 if (status & 0x20) 489 printf (" Frame"); 490 if (status & 0x10) 491 printf (" Overflow"); 492 if (status & 0x08) 493 printf (" CRC"); 494 if (status & 0x04) 495 printf (" Fifo"); 496 printf (" Error\n"); 497 entry->status &= le16_to_cpu (0x03ff); 498 499 } else { 500 501 pkt_len = 502 (le32_to_cpu (entry->msg_length) & 0xfff) - 4; 503 if (pkt_len < 60) { 504 printf ("%s: Rx%d: invalid packet length %d\n", dev->name, lp->cur_rx, pkt_len); 505 } else { 506 NetReceive (lp->rx_buf[lp->cur_rx], pkt_len); 507 PCNET_DEBUG2 ("Rx%d: %d bytes from 0x%p\n", 508 lp->cur_rx, pkt_len, 509 lp->rx_buf[lp->cur_rx]); 510 } 511 } 512 entry->status |= cpu_to_le16 (0x8000); 513 514 if (++lp->cur_rx >= RX_RING_SIZE) 515 lp->cur_rx = 0; 516 } 517 return pkt_len; 518 } 519 520 static void pcnet_halt (struct eth_device *dev) 521 { 522 int i; 523 524 PCNET_DEBUG1 ("%s: pcnet_halt...\n", dev->name); 525 526 /* Reset the PCnet controller */ 527 pcnet_reset (dev); 528 529 /* Wait for Stop bit */ 530 for (i = 1000; i > 0; i--) { 531 if (pcnet_read_csr (dev, 0) & 0x4) 532 break; 533 udelay (10); 534 } 535 if (i <= 0) { 536 printf ("%s: TIMEOUT: controller reset failed\n", dev->name); 537 } 538 } 539 #endif 540