1 /* 2 * (C) Copyright 2009 3 * Marvell Semiconductor <www.marvell.com> 4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 5 * 6 * (C) Copyright 2003 7 * Ingo Assmus <ingo.assmus@keymile.com> 8 * 9 * based on - Driver for MV64360X ethernet ports 10 * Copyright (C) 2002 rabeeh@galileo.co.il 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 28 * MA 02110-1301 USA 29 */ 30 31 #include <common.h> 32 #include <net.h> 33 #include <malloc.h> 34 #include <miiphy.h> 35 #include <asm/errno.h> 36 #include <asm/types.h> 37 #include <asm/byteorder.h> 38 #include <asm/arch/kirkwood.h> 39 #include "mvgbe.h" 40 41 DECLARE_GLOBAL_DATA_PTR; 42 43 #define KIRKWOOD_PHY_ADR_REQUEST 0xee 44 #define KWGBE_SMI_REG (((struct kwgbe_registers *)KW_EGIGA0_BASE)->smi) 45 46 /* 47 * smi_reg_read - miiphy_read callback function. 48 * 49 * Returns 16bit phy register value, or 0xffff on error 50 */ 51 static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data) 52 { 53 struct eth_device *dev = eth_get_dev_by_name(devname); 54 struct kwgbe_device *dkwgbe = to_dkwgbe(dev); 55 struct kwgbe_registers *regs = dkwgbe->regs; 56 u32 smi_reg; 57 u32 timeout; 58 59 /* Phyadr read request */ 60 if (phy_adr == KIRKWOOD_PHY_ADR_REQUEST && 61 reg_ofs == KIRKWOOD_PHY_ADR_REQUEST) { 62 /* */ 63 *data = (u16) (KWGBEREG_RD(regs->phyadr) & PHYADR_MASK); 64 return 0; 65 } 66 /* check parameters */ 67 if (phy_adr > PHYADR_MASK) { 68 printf("Err..(%s) Invalid PHY address %d\n", 69 __FUNCTION__, phy_adr); 70 return -EFAULT; 71 } 72 if (reg_ofs > PHYREG_MASK) { 73 printf("Err..(%s) Invalid register offset %d\n", 74 __FUNCTION__, reg_ofs); 75 return -EFAULT; 76 } 77 78 timeout = KWGBE_PHY_SMI_TIMEOUT; 79 /* wait till the SMI is not busy */ 80 do { 81 /* read smi register */ 82 smi_reg = KWGBEREG_RD(KWGBE_SMI_REG); 83 if (timeout-- == 0) { 84 printf("Err..(%s) SMI busy timeout\n", __FUNCTION__); 85 return -EFAULT; 86 } 87 } while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK); 88 89 /* fill the phy address and regiser offset and read opcode */ 90 smi_reg = (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS) 91 | (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS) 92 | KWGBE_PHY_SMI_OPCODE_READ; 93 94 /* write the smi register */ 95 KWGBEREG_WR(KWGBE_SMI_REG, smi_reg); 96 97 /*wait till read value is ready */ 98 timeout = KWGBE_PHY_SMI_TIMEOUT; 99 100 do { 101 /* read smi register */ 102 smi_reg = KWGBEREG_RD(KWGBE_SMI_REG); 103 if (timeout-- == 0) { 104 printf("Err..(%s) SMI read ready timeout\n", 105 __FUNCTION__); 106 return -EFAULT; 107 } 108 } while (!(smi_reg & KWGBE_PHY_SMI_READ_VALID_MASK)); 109 110 /* Wait for the data to update in the SMI register */ 111 for (timeout = 0; timeout < KWGBE_PHY_SMI_TIMEOUT; timeout++) ; 112 113 *data = (u16) (KWGBEREG_RD(KWGBE_SMI_REG) & KWGBE_PHY_SMI_DATA_MASK); 114 115 debug("%s:(adr %d, off %d) value= %04x\n", __FUNCTION__, phy_adr, 116 reg_ofs, *data); 117 118 return 0; 119 } 120 121 /* 122 * smi_reg_write - imiiphy_write callback function. 123 * 124 * Returns 0 if write succeed, -EINVAL on bad parameters 125 * -ETIME on timeout 126 */ 127 static int smi_reg_write(char *devname, u8 phy_adr, u8 reg_ofs, u16 data) 128 { 129 struct eth_device *dev = eth_get_dev_by_name(devname); 130 struct kwgbe_device *dkwgbe = to_dkwgbe(dev); 131 struct kwgbe_registers *regs = dkwgbe->regs; 132 u32 smi_reg; 133 u32 timeout; 134 135 /* Phyadr write request*/ 136 if (phy_adr == KIRKWOOD_PHY_ADR_REQUEST && 137 reg_ofs == KIRKWOOD_PHY_ADR_REQUEST) { 138 KWGBEREG_WR(regs->phyadr, data); 139 return 0; 140 } 141 142 /* check parameters */ 143 if (phy_adr > PHYADR_MASK) { 144 printf("Err..(%s) Invalid phy address\n", __FUNCTION__); 145 return -EINVAL; 146 } 147 if (reg_ofs > PHYREG_MASK) { 148 printf("Err..(%s) Invalid register offset\n", __FUNCTION__); 149 return -EINVAL; 150 } 151 152 /* wait till the SMI is not busy */ 153 timeout = KWGBE_PHY_SMI_TIMEOUT; 154 do { 155 /* read smi register */ 156 smi_reg = KWGBEREG_RD(KWGBE_SMI_REG); 157 if (timeout-- == 0) { 158 printf("Err..(%s) SMI busy timeout\n", __FUNCTION__); 159 return -ETIME; 160 } 161 } while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK); 162 163 /* fill the phy addr and reg offset and write opcode and data */ 164 smi_reg = (data << KWGBE_PHY_SMI_DATA_OFFS); 165 smi_reg |= (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS) 166 | (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS); 167 smi_reg &= ~KWGBE_PHY_SMI_OPCODE_READ; 168 169 /* write the smi register */ 170 KWGBEREG_WR(KWGBE_SMI_REG, smi_reg); 171 172 return 0; 173 } 174 175 /* Stop and checks all queues */ 176 static void stop_queue(u32 * qreg) 177 { 178 u32 reg_data; 179 180 reg_data = readl(qreg); 181 182 if (reg_data & 0xFF) { 183 /* Issue stop command for active channels only */ 184 writel((reg_data << 8), qreg); 185 186 /* Wait for all queue activity to terminate. */ 187 do { 188 /* 189 * Check port cause register that all queues 190 * are stopped 191 */ 192 reg_data = readl(qreg); 193 } 194 while (reg_data & 0xFF); 195 } 196 } 197 198 /* 199 * set_access_control - Config address decode parameters for Ethernet unit 200 * 201 * This function configures the address decode parameters for the Gigabit 202 * Ethernet Controller according the given parameters struct. 203 * 204 * @regs Register struct pointer. 205 * @param Address decode parameter struct. 206 */ 207 static void set_access_control(struct kwgbe_registers *regs, 208 struct kwgbe_winparam *param) 209 { 210 u32 access_prot_reg; 211 212 /* Set access control register */ 213 access_prot_reg = KWGBEREG_RD(regs->epap); 214 /* clear window permission */ 215 access_prot_reg &= (~(3 << (param->win * 2))); 216 access_prot_reg |= (param->access_ctrl << (param->win * 2)); 217 KWGBEREG_WR(regs->epap, access_prot_reg); 218 219 /* Set window Size reg (SR) */ 220 KWGBEREG_WR(regs->barsz[param->win].size, 221 (((param->size / 0x10000) - 1) << 16)); 222 223 /* Set window Base address reg (BA) */ 224 KWGBEREG_WR(regs->barsz[param->win].bar, 225 (param->target | param->attrib | param->base_addr)); 226 /* High address remap reg (HARR) */ 227 if (param->win < 4) 228 KWGBEREG_WR(regs->ha_remap[param->win], param->high_addr); 229 230 /* Base address enable reg (BARER) */ 231 if (param->enable == 1) 232 KWGBEREG_BITS_RESET(regs->bare, (1 << param->win)); 233 else 234 KWGBEREG_BITS_SET(regs->bare, (1 << param->win)); 235 } 236 237 static void set_dram_access(struct kwgbe_registers *regs) 238 { 239 struct kwgbe_winparam win_param; 240 int i; 241 242 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 243 /* Set access parameters for DRAM bank i */ 244 win_param.win = i; /* Use Ethernet window i */ 245 /* Window target - DDR */ 246 win_param.target = KWGBE_TARGET_DRAM; 247 /* Enable full access */ 248 win_param.access_ctrl = EWIN_ACCESS_FULL; 249 win_param.high_addr = 0; 250 /* Get bank base and size */ 251 win_param.base_addr = gd->bd->bi_dram[i].start; 252 win_param.size = gd->bd->bi_dram[i].size; 253 if (win_param.size == 0) 254 win_param.enable = 0; 255 else 256 win_param.enable = 1; /* Enable the access */ 257 258 /* Enable DRAM bank */ 259 switch (i) { 260 case 0: 261 win_param.attrib = EBAR_DRAM_CS0; 262 break; 263 case 1: 264 win_param.attrib = EBAR_DRAM_CS1; 265 break; 266 case 2: 267 win_param.attrib = EBAR_DRAM_CS2; 268 break; 269 case 3: 270 win_param.attrib = EBAR_DRAM_CS3; 271 break; 272 default: 273 /* invalid bank, disable access */ 274 win_param.enable = 0; 275 win_param.attrib = 0; 276 break; 277 } 278 /* Set the access control for address window(EPAPR) RD/WR */ 279 set_access_control(regs, &win_param); 280 } 281 } 282 283 /* 284 * port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables 285 * 286 * Go through all the DA filter tables (Unicast, Special Multicast & Other 287 * Multicast) and set each entry to 0. 288 */ 289 static void port_init_mac_tables(struct kwgbe_registers *regs) 290 { 291 int table_index; 292 293 /* Clear DA filter unicast table (Ex_dFUT) */ 294 for (table_index = 0; table_index < 4; ++table_index) 295 KWGBEREG_WR(regs->dfut[table_index], 0); 296 297 for (table_index = 0; table_index < 64; ++table_index) { 298 /* Clear DA filter special multicast table (Ex_dFSMT) */ 299 KWGBEREG_WR(regs->dfsmt[table_index], 0); 300 /* Clear DA filter other multicast table (Ex_dFOMT) */ 301 KWGBEREG_WR(regs->dfomt[table_index], 0); 302 } 303 } 304 305 /* 306 * port_uc_addr - This function Set the port unicast address table 307 * 308 * This function locates the proper entry in the Unicast table for the 309 * specified MAC nibble and sets its properties according to function 310 * parameters. 311 * This function add/removes MAC addresses from the port unicast address 312 * table. 313 * 314 * @uc_nibble Unicast MAC Address last nibble. 315 * @option 0 = Add, 1 = remove address. 316 * 317 * RETURN: 1 if output succeeded. 0 if option parameter is invalid. 318 */ 319 static int port_uc_addr(struct kwgbe_registers *regs, u8 uc_nibble, 320 int option) 321 { 322 u32 unicast_reg; 323 u32 tbl_offset; 324 u32 reg_offset; 325 326 /* Locate the Unicast table entry */ 327 uc_nibble = (0xf & uc_nibble); 328 /* Register offset from unicast table base */ 329 tbl_offset = (uc_nibble / 4); 330 /* Entry offset within the above register */ 331 reg_offset = uc_nibble % 4; 332 333 switch (option) { 334 case REJECT_MAC_ADDR: 335 /* 336 * Clear accepts frame bit at specified unicast 337 * DA table entry 338 */ 339 unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]); 340 unicast_reg &= (0xFF << (8 * reg_offset)); 341 KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg); 342 break; 343 case ACCEPT_MAC_ADDR: 344 /* Set accepts frame bit at unicast DA filter table entry */ 345 unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]); 346 unicast_reg &= (0xFF << (8 * reg_offset)); 347 unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset)); 348 KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg); 349 break; 350 default: 351 return 0; 352 } 353 return 1; 354 } 355 356 /* 357 * port_uc_addr_set - This function Set the port Unicast address. 358 */ 359 static void port_uc_addr_set(struct kwgbe_registers *regs, u8 * p_addr) 360 { 361 u32 mac_h; 362 u32 mac_l; 363 364 mac_l = (p_addr[4] << 8) | (p_addr[5]); 365 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) | 366 (p_addr[3] << 0); 367 368 KWGBEREG_WR(regs->macal, mac_l); 369 KWGBEREG_WR(regs->macah, mac_h); 370 371 /* Accept frames of this address */ 372 port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR); 373 } 374 375 /* 376 * kwgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. 377 */ 378 static void kwgbe_init_rx_desc_ring(struct kwgbe_device *dkwgbe) 379 { 380 struct kwgbe_rxdesc *p_rx_desc; 381 int i; 382 383 /* initialize the Rx descriptors ring */ 384 p_rx_desc = dkwgbe->p_rxdesc; 385 for (i = 0; i < RINGSZ; i++) { 386 p_rx_desc->cmd_sts = 387 KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT; 388 p_rx_desc->buf_size = PKTSIZE_ALIGN; 389 p_rx_desc->byte_cnt = 0; 390 p_rx_desc->buf_ptr = dkwgbe->p_rxbuf + i * PKTSIZE_ALIGN; 391 if (i == (RINGSZ - 1)) 392 p_rx_desc->nxtdesc_p = dkwgbe->p_rxdesc; 393 else { 394 p_rx_desc->nxtdesc_p = (struct kwgbe_rxdesc *) 395 ((u32) p_rx_desc + KW_RXQ_DESC_ALIGNED_SIZE); 396 p_rx_desc = p_rx_desc->nxtdesc_p; 397 } 398 } 399 dkwgbe->p_rxdesc_curr = dkwgbe->p_rxdesc; 400 } 401 402 static int kwgbe_init(struct eth_device *dev) 403 { 404 struct kwgbe_device *dkwgbe = to_dkwgbe(dev); 405 struct kwgbe_registers *regs = dkwgbe->regs; 406 #if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \ 407 && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN) 408 int i; 409 #endif 410 /* setup RX rings */ 411 kwgbe_init_rx_desc_ring(dkwgbe); 412 413 /* Clear the ethernet port interrupts */ 414 KWGBEREG_WR(regs->ic, 0); 415 KWGBEREG_WR(regs->ice, 0); 416 /* Unmask RX buffer and TX end interrupt */ 417 KWGBEREG_WR(regs->pim, INT_CAUSE_UNMASK_ALL); 418 /* Unmask phy and link status changes interrupts */ 419 KWGBEREG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT); 420 421 set_dram_access(regs); 422 port_init_mac_tables(regs); 423 port_uc_addr_set(regs, dkwgbe->dev.enetaddr); 424 425 /* Assign port configuration and command. */ 426 KWGBEREG_WR(regs->pxc, PRT_CFG_VAL); 427 KWGBEREG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE); 428 KWGBEREG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE); 429 430 /* Assign port SDMA configuration */ 431 KWGBEREG_WR(regs->sdc, PORT_SDMA_CFG_VALUE); 432 KWGBEREG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL); 433 KWGBEREG_WR(regs->tqx[0].tqxtbc, (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL); 434 /* Turn off the port/RXUQ bandwidth limitation */ 435 KWGBEREG_WR(regs->pmtu, 0); 436 437 /* Set maximum receive buffer to 9700 bytes */ 438 KWGBEREG_WR(regs->psc0, KWGBE_MAX_RX_PACKET_9700BYTE 439 | (KWGBEREG_RD(regs->psc0) & MRU_MASK)); 440 441 /* Enable port initially */ 442 KWGBEREG_BITS_SET(regs->psc0, KWGBE_SERIAL_PORT_EN); 443 444 /* 445 * Set ethernet MTU for leaky bucket mechanism to 0 - this will 446 * disable the leaky bucket mechanism . 447 */ 448 KWGBEREG_WR(regs->pmtu, 0); 449 450 /* Assignment of Rx CRDB of given RXUQ */ 451 KWGBEREG_WR(regs->rxcdp[RXUQ], (u32) dkwgbe->p_rxdesc_curr); 452 /* ensure previous write is done before enabling Rx DMA */ 453 isb(); 454 /* Enable port Rx. */ 455 KWGBEREG_WR(regs->rqc, (1 << RXUQ)); 456 457 #if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \ 458 && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN) 459 /* Wait up to 5s for the link status */ 460 for (i = 0; i < 5; i++) { 461 u16 phyadr; 462 463 miiphy_read(dev->name, KIRKWOOD_PHY_ADR_REQUEST, 464 KIRKWOOD_PHY_ADR_REQUEST, &phyadr); 465 /* Return if we get link up */ 466 if (miiphy_link(dev->name, phyadr)) 467 return 0; 468 udelay(1000000); 469 } 470 471 printf("No link on %s\n", dev->name); 472 return -1; 473 #endif 474 return 0; 475 } 476 477 static int kwgbe_halt(struct eth_device *dev) 478 { 479 struct kwgbe_device *dkwgbe = to_dkwgbe(dev); 480 struct kwgbe_registers *regs = dkwgbe->regs; 481 482 /* Disable all gigE address decoder */ 483 KWGBEREG_WR(regs->bare, 0x3f); 484 485 stop_queue(®s->tqc); 486 stop_queue(®s->rqc); 487 488 /* Disable port */ 489 KWGBEREG_BITS_RESET(regs->psc0, KWGBE_SERIAL_PORT_EN); 490 /* Set port is not reset */ 491 KWGBEREG_BITS_RESET(regs->psc1, 1 << 4); 492 #ifdef CONFIG_SYS_MII_MODE 493 /* Set MMI interface up */ 494 KWGBEREG_BITS_RESET(regs->psc1, 1 << 3); 495 #endif 496 /* Disable & mask ethernet port interrupts */ 497 KWGBEREG_WR(regs->ic, 0); 498 KWGBEREG_WR(regs->ice, 0); 499 KWGBEREG_WR(regs->pim, 0); 500 KWGBEREG_WR(regs->peim, 0); 501 502 return 0; 503 } 504 505 static int kwgbe_write_hwaddr(struct eth_device *dev) 506 { 507 struct kwgbe_device *dkwgbe = to_dkwgbe(dev); 508 struct kwgbe_registers *regs = dkwgbe->regs; 509 510 /* Programs net device MAC address after initialization */ 511 port_uc_addr_set(regs, dkwgbe->dev.enetaddr); 512 return 0; 513 } 514 515 static int kwgbe_send(struct eth_device *dev, volatile void *dataptr, 516 int datasize) 517 { 518 struct kwgbe_device *dkwgbe = to_dkwgbe(dev); 519 struct kwgbe_registers *regs = dkwgbe->regs; 520 struct kwgbe_txdesc *p_txdesc = dkwgbe->p_txdesc; 521 void *p = (void *)dataptr; 522 u32 cmd_sts; 523 524 /* Copy buffer if it's misaligned */ 525 if ((u32) dataptr & 0x07) { 526 if (datasize > PKTSIZE_ALIGN) { 527 printf("Non-aligned data too large (%d)\n", 528 datasize); 529 return -1; 530 } 531 532 memcpy(dkwgbe->p_aligned_txbuf, p, datasize); 533 p = dkwgbe->p_aligned_txbuf; 534 } 535 536 p_txdesc->cmd_sts = KWGBE_ZERO_PADDING | KWGBE_GEN_CRC; 537 p_txdesc->cmd_sts |= KWGBE_TX_FIRST_DESC | KWGBE_TX_LAST_DESC; 538 p_txdesc->cmd_sts |= KWGBE_BUFFER_OWNED_BY_DMA; 539 p_txdesc->cmd_sts |= KWGBE_TX_EN_INTERRUPT; 540 p_txdesc->buf_ptr = (u8 *) p; 541 p_txdesc->byte_cnt = datasize; 542 543 /* Set this tc desc as zeroth TXUQ */ 544 KWGBEREG_WR(regs->tcqdp[TXUQ], (u32) p_txdesc); 545 546 /* ensure tx desc writes above are performed before we start Tx DMA */ 547 isb(); 548 549 /* Apply send command using zeroth TXUQ */ 550 KWGBEREG_WR(regs->tqc, (1 << TXUQ)); 551 552 /* 553 * wait for packet xmit completion 554 */ 555 cmd_sts = readl(&p_txdesc->cmd_sts); 556 while (cmd_sts & KWGBE_BUFFER_OWNED_BY_DMA) { 557 /* return fail if error is detected */ 558 if ((cmd_sts & (KWGBE_ERROR_SUMMARY | KWGBE_TX_LAST_FRAME)) == 559 (KWGBE_ERROR_SUMMARY | KWGBE_TX_LAST_FRAME) && 560 cmd_sts & (KWGBE_UR_ERROR | KWGBE_RL_ERROR)) { 561 printf("Err..(%s) in xmit packet\n", __FUNCTION__); 562 return -1; 563 } 564 cmd_sts = readl(&p_txdesc->cmd_sts); 565 }; 566 return 0; 567 } 568 569 static int kwgbe_recv(struct eth_device *dev) 570 { 571 struct kwgbe_device *dkwgbe = to_dkwgbe(dev); 572 struct kwgbe_rxdesc *p_rxdesc_curr = dkwgbe->p_rxdesc_curr; 573 u32 cmd_sts; 574 u32 timeout = 0; 575 576 /* wait untill rx packet available or timeout */ 577 do { 578 if (timeout < KWGBE_PHY_SMI_TIMEOUT) 579 timeout++; 580 else { 581 debug("%s time out...\n", __FUNCTION__); 582 return -1; 583 } 584 } while (readl(&p_rxdesc_curr->cmd_sts) & KWGBE_BUFFER_OWNED_BY_DMA); 585 586 if (p_rxdesc_curr->byte_cnt != 0) { 587 debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n", 588 __FUNCTION__, (u32) p_rxdesc_curr->byte_cnt, 589 (u32) p_rxdesc_curr->buf_ptr, 590 (u32) p_rxdesc_curr->cmd_sts); 591 } 592 593 /* 594 * In case received a packet without first/last bits on 595 * OR the error summary bit is on, 596 * the packets needs to be dropeed. 597 */ 598 cmd_sts = readl(&p_rxdesc_curr->cmd_sts); 599 600 if ((cmd_sts & 601 (KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC)) 602 != (KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC)) { 603 604 printf("Err..(%s) Dropping packet spread on" 605 " multiple descriptors\n", __FUNCTION__); 606 607 } else if (cmd_sts & KWGBE_ERROR_SUMMARY) { 608 609 printf("Err..(%s) Dropping packet with errors\n", 610 __FUNCTION__); 611 612 } else { 613 /* !!! call higher layer processing */ 614 debug("%s: Sending Received packet to" 615 " upper layer (NetReceive)\n", __FUNCTION__); 616 617 /* let the upper layer handle the packet */ 618 NetReceive((p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET), 619 (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET)); 620 } 621 /* 622 * free these descriptors and point next in the ring 623 */ 624 p_rxdesc_curr->cmd_sts = 625 KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT; 626 p_rxdesc_curr->buf_size = PKTSIZE_ALIGN; 627 p_rxdesc_curr->byte_cnt = 0; 628 629 writel((unsigned)p_rxdesc_curr->nxtdesc_p, (u32) &dkwgbe->p_rxdesc_curr); 630 631 return 0; 632 } 633 634 int kirkwood_egiga_initialize(bd_t * bis) 635 { 636 struct kwgbe_device *dkwgbe; 637 struct eth_device *dev; 638 int devnum; 639 char *s; 640 u8 used_ports[MAX_KWGBE_DEVS] = CONFIG_KIRKWOOD_EGIGA_PORTS; 641 642 for (devnum = 0; devnum < MAX_KWGBE_DEVS; devnum++) { 643 /*skip if port is configured not to use */ 644 if (used_ports[devnum] == 0) 645 continue; 646 647 if (!(dkwgbe = malloc(sizeof(struct kwgbe_device)))) 648 goto error1; 649 650 memset(dkwgbe, 0, sizeof(struct kwgbe_device)); 651 652 if (!(dkwgbe->p_rxdesc = 653 (struct kwgbe_rxdesc *)memalign(PKTALIGN, 654 KW_RXQ_DESC_ALIGNED_SIZE 655 * RINGSZ + 1))) 656 goto error2; 657 658 if (!(dkwgbe->p_rxbuf = (u8 *) memalign(PKTALIGN, RINGSZ 659 * PKTSIZE_ALIGN + 1))) 660 goto error3; 661 662 if (!(dkwgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN))) 663 goto error4; 664 665 if (!(dkwgbe->p_txdesc = (struct kwgbe_txdesc *) 666 memalign(PKTALIGN, sizeof(struct kwgbe_txdesc) + 1))) { 667 free(dkwgbe->p_aligned_txbuf); 668 error4: 669 free(dkwgbe->p_rxbuf); 670 error3: 671 free(dkwgbe->p_rxdesc); 672 error2: 673 free(dkwgbe); 674 error1: 675 printf("Err.. %s Failed to allocate memory\n", 676 __FUNCTION__); 677 return -1; 678 } 679 680 dev = &dkwgbe->dev; 681 682 /* must be less than NAMESIZE (16) */ 683 sprintf(dev->name, "egiga%d", devnum); 684 685 /* Extract the MAC address from the environment */ 686 switch (devnum) { 687 case 0: 688 dkwgbe->regs = (void *)KW_EGIGA0_BASE; 689 s = "ethaddr"; 690 break; 691 case 1: 692 dkwgbe->regs = (void *)KW_EGIGA1_BASE; 693 s = "eth1addr"; 694 break; 695 default: /* this should never happen */ 696 printf("Err..(%s) Invalid device number %d\n", 697 __FUNCTION__, devnum); 698 return -1; 699 } 700 701 while (!eth_getenv_enetaddr(s, dev->enetaddr)) { 702 /* Generate Private MAC addr if not set */ 703 dev->enetaddr[0] = 0x02; 704 dev->enetaddr[1] = 0x50; 705 dev->enetaddr[2] = 0x43; 706 #if defined (CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION) 707 /* Generate fixed lower MAC half using devnum */ 708 dev->enetaddr[3] = 0; 709 dev->enetaddr[4] = 0; 710 dev->enetaddr[5] = devnum; 711 #else 712 /* Generate random lower MAC half */ 713 dev->enetaddr[3] = get_random_hex(); 714 dev->enetaddr[4] = get_random_hex(); 715 dev->enetaddr[5] = get_random_hex(); 716 #endif 717 eth_setenv_enetaddr(s, dev->enetaddr); 718 } 719 720 dev->init = (void *)kwgbe_init; 721 dev->halt = (void *)kwgbe_halt; 722 dev->send = (void *)kwgbe_send; 723 dev->recv = (void *)kwgbe_recv; 724 dev->write_hwaddr = (void *)kwgbe_write_hwaddr; 725 726 eth_register(dev); 727 728 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 729 miiphy_register(dev->name, smi_reg_read, smi_reg_write); 730 /* Set phy address of the port */ 731 miiphy_write(dev->name, KIRKWOOD_PHY_ADR_REQUEST, 732 KIRKWOOD_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum); 733 #endif 734 } 735 return 0; 736 } 737