1 /* 2 * (C) Copyright 2000-2004 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * (C) Copyright 2007 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27 #include <common.h> 28 #include <malloc.h> 29 30 #include <asm/fec.h> 31 #include <asm/immap.h> 32 33 #include <command.h> 34 #include <config.h> 35 #include <net.h> 36 #include <miiphy.h> 37 38 #ifdef CONFIG_MCFFEC 39 #undef ET_DEBUG 40 #undef MII_DEBUG 41 42 /* Ethernet Transmit and Receive Buffers */ 43 #define DBUF_LENGTH 1520 44 #define TX_BUF_CNT 2 45 #define PKT_MAXBUF_SIZE 1518 46 #define PKT_MINBUF_SIZE 64 47 #define PKT_MAXBLR_SIZE 1520 48 #define LAST_PKTBUFSRX PKTBUFSRX - 1 49 #define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY) 50 #define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST) 51 52 DECLARE_GLOBAL_DATA_PTR; 53 54 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) 55 56 struct fec_info_s fec_info[] = { 57 #ifdef CFG_FEC0_IOBASE 58 { 59 0, /* index */ 60 CFG_FEC0_IOBASE, /* io base */ 61 CFG_FEC0_PINMUX, /* gpio pin muxing */ 62 CFG_FEC0_MIIBASE, /* mii base */ 63 -1, /* phy_addr */ 64 0, /* duplex and speed */ 65 0, /* phy name */ 66 0, /* phyname init */ 67 0, /* RX BD */ 68 0, /* TX BD */ 69 0, /* rx Index */ 70 0, /* tx Index */ 71 0, /* tx buffer */ 72 0, /* initialized flag */ 73 }, 74 #endif 75 #ifdef CFG_FEC1_IOBASE 76 { 77 1, /* index */ 78 CFG_FEC1_IOBASE, /* io base */ 79 CFG_FEC1_PINMUX, /* gpio pin muxing */ 80 CFG_FEC1_MIIBASE, /* mii base */ 81 -1, /* phy_addr */ 82 0, /* duplex and speed */ 83 0, /* phy name */ 84 0, /* phy name init */ 85 0, /* RX BD */ 86 0, /* TX BD */ 87 0, /* rx Index */ 88 0, /* tx Index */ 89 0, /* tx buffer */ 90 0, /* initialized flag */ 91 } 92 #endif 93 }; 94 95 int fec_send(struct eth_device *dev, volatile void *packet, int length); 96 int fec_recv(struct eth_device *dev); 97 int fec_init(struct eth_device *dev, bd_t * bd); 98 void fec_halt(struct eth_device *dev); 99 void fec_reset(struct eth_device *dev); 100 101 extern int fecpin_setclear(struct eth_device *dev, int setclear); 102 103 #ifdef CFG_DISCOVER_PHY 104 extern void mii_init(void); 105 extern uint mii_send(uint mii_cmd); 106 extern int mii_discover_phy(struct eth_device *dev); 107 extern int mcffec_miiphy_read(char *devname, unsigned char addr, 108 unsigned char reg, unsigned short *value); 109 extern int mcffec_miiphy_write(char *devname, unsigned char addr, 110 unsigned char reg, unsigned short value); 111 #endif 112 113 void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd) 114 { 115 if ((dup_spd >> 16) == FULL) { 116 /* Set maximum frame length */ 117 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE | 118 FEC_RCR_PROM | 0x100; 119 fecp->tcr = FEC_TCR_FDEN; 120 } else { 121 /* Half duplex mode */ 122 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | 123 FEC_RCR_MII_MODE | FEC_RCR_DRT; 124 fecp->tcr &= ~FEC_TCR_FDEN; 125 } 126 127 if ((dup_spd & 0xFFFF) == _100BASET) { 128 #ifdef MII_DEBUG 129 printf("100Mbps\n"); 130 #endif 131 bd->bi_ethspeed = 100; 132 } else { 133 #ifdef MII_DEBUG 134 printf("10Mbps\n"); 135 #endif 136 bd->bi_ethspeed = 10; 137 } 138 } 139 140 int fec_send(struct eth_device *dev, volatile void *packet, int length) 141 { 142 struct fec_info_s *info = dev->priv; 143 volatile fec_t *fecp = (fec_t *) (info->iobase); 144 int j, rc; 145 u16 phyStatus; 146 147 miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &phyStatus); 148 149 /* section 16.9.23.3 150 * Wait for ready 151 */ 152 j = 0; 153 #if (CONFIG_COMMANDS & CFG_CMD_CACHE) 154 icache_invalid(); 155 #endif 156 while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) && 157 (j < MCFFEC_TOUT_LOOP)) { 158 udelay(1); 159 j++; 160 #if (CONFIG_COMMANDS & CFG_CMD_CACHE) 161 icache_invalid(); 162 #endif 163 } 164 if (j >= MCFFEC_TOUT_LOOP) { 165 printf("TX not ready\n"); 166 } 167 #if (CONFIG_COMMANDS & CFG_CMD_CACHE) 168 icache_invalid(); 169 #endif 170 info->txbd[info->txIdx].cbd_bufaddr = (uint) packet; 171 info->txbd[info->txIdx].cbd_datlen = length; 172 info->txbd[info->txIdx].cbd_sc |= BD_ENET_TX_RDY_LST; 173 174 /* Activate transmit Buffer Descriptor polling */ 175 fecp->tdar = 0x01000000; /* Descriptor polling active */ 176 177 j = 0; 178 #if (CONFIG_COMMANDS & CFG_CMD_CACHE) 179 icache_invalid(); 180 #endif 181 while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) && 182 (j < MCFFEC_TOUT_LOOP)) { 183 udelay(1); 184 j++; 185 #if (CONFIG_COMMANDS & CFG_CMD_CACHE) 186 icache_invalid(); 187 #endif 188 } 189 if (j >= MCFFEC_TOUT_LOOP) { 190 printf("TX timeout\n"); 191 } 192 #ifdef ET_DEBUG 193 printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n", 194 __FILE__, __LINE__, __FUNCTION__, j, 195 info->txbd[info->txIdx].cbd_sc, 196 (info->txbd[info->txIdx].cbd_sc & 0x003C) >> 2); 197 #endif 198 199 /* return only status bits */ ; 200 #if (CONFIG_COMMANDS & CFG_CMD_CACHE) 201 icache_invalid(); 202 #endif 203 rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS); 204 info->txIdx = (info->txIdx + 1) % TX_BUF_CNT; 205 206 return rc; 207 } 208 209 int fec_recv(struct eth_device *dev) 210 { 211 struct fec_info_s *info = dev->priv; 212 volatile fec_t *fecp = (fec_t *) (info->iobase); 213 int length; 214 215 for (;;) { 216 /* section 16.9.23.2 */ 217 if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { 218 length = -1; 219 break; /* nothing received - leave for() loop */ 220 } 221 222 length = info->rxbd[info->rxIdx].cbd_datlen; 223 224 if (info->rxbd[info->rxIdx].cbd_sc & 0x003f) { 225 printf("%s[%d] err: %x\n", 226 __FUNCTION__, __LINE__, 227 info->rxbd[info->rxIdx].cbd_sc); 228 #ifdef ET_DEBUG 229 printf("%s[%d] err: %x\n", 230 __FUNCTION__, __LINE__, 231 info->rxbd[info->rxIdx].cbd_sc); 232 #endif 233 } else { 234 235 length -= 4; 236 /* Pass the packet up to the protocol layers. */ 237 NetReceive(NetRxPackets[info->rxIdx], length); 238 239 fecp->eir |= FEC_EIR_RXF; 240 } 241 242 /* Give the buffer back to the FEC. */ 243 info->rxbd[info->rxIdx].cbd_datlen = 0; 244 245 /* wrap around buffer index when necessary */ 246 if (info->rxIdx == LAST_PKTBUFSRX) { 247 info->rxbd[PKTBUFSRX - 1].cbd_sc = BD_ENET_RX_W_E; 248 info->rxIdx = 0; 249 } else { 250 info->rxbd[info->rxIdx].cbd_sc = BD_ENET_RX_EMPTY; 251 info->rxIdx++; 252 } 253 254 /* Try to fill Buffer Descriptors */ 255 fecp->rdar = 0x01000000; /* Descriptor polling active */ 256 } 257 258 return length; 259 } 260 261 #ifdef ET_DEBUG 262 void dbgFecRegs(struct eth_device *dev) 263 { 264 struct fec_info_s *info = dev->priv; 265 volatile fec_t *fecp = (fec_t *) (info->iobase); 266 267 printf("=====\n"); 268 printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir); 269 printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr); 270 printf("r_des_active %x - %x\n", (int)&fecp->rdar, fecp->rdar); 271 printf("x_des_active %x - %x\n", (int)&fecp->tdar, fecp->tdar); 272 printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr); 273 printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr); 274 printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr); 275 printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc); 276 printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr); 277 printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr); 278 printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr); 279 printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur); 280 printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd); 281 printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur); 282 printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr); 283 printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur); 284 printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr); 285 printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr); 286 printf("r_bound %x - %x\n", (int)&fecp->frbr, fecp->frbr); 287 printf("r_fstart %x - %x\n", (int)&fecp->frsr, fecp->frsr); 288 printf("r_drng %x - %x\n", (int)&fecp->erdsr, fecp->erdsr); 289 printf("x_drng %x - %x\n", (int)&fecp->etdsr, fecp->etdsr); 290 printf("r_bufsz %x - %x\n", (int)&fecp->emrbr, fecp->emrbr); 291 292 printf("\n"); 293 printf("rmon_t_drop %x - %x\n", (int)&fecp->rmon_t_drop, 294 fecp->rmon_t_drop); 295 printf("rmon_t_packets %x - %x\n", (int)&fecp->rmon_t_packets, 296 fecp->rmon_t_packets); 297 printf("rmon_t_bc_pkt %x - %x\n", (int)&fecp->rmon_t_bc_pkt, 298 fecp->rmon_t_bc_pkt); 299 printf("rmon_t_mc_pkt %x - %x\n", (int)&fecp->rmon_t_mc_pkt, 300 fecp->rmon_t_mc_pkt); 301 printf("rmon_t_crc_align %x - %x\n", (int)&fecp->rmon_t_crc_align, 302 fecp->rmon_t_crc_align); 303 printf("rmon_t_undersize %x - %x\n", (int)&fecp->rmon_t_undersize, 304 fecp->rmon_t_undersize); 305 printf("rmon_t_oversize %x - %x\n", (int)&fecp->rmon_t_oversize, 306 fecp->rmon_t_oversize); 307 printf("rmon_t_frag %x - %x\n", (int)&fecp->rmon_t_frag, 308 fecp->rmon_t_frag); 309 printf("rmon_t_jab %x - %x\n", (int)&fecp->rmon_t_jab, 310 fecp->rmon_t_jab); 311 printf("rmon_t_col %x - %x\n", (int)&fecp->rmon_t_col, 312 fecp->rmon_t_col); 313 printf("rmon_t_p64 %x - %x\n", (int)&fecp->rmon_t_p64, 314 fecp->rmon_t_p64); 315 printf("rmon_t_p65to127 %x - %x\n", (int)&fecp->rmon_t_p65to127, 316 fecp->rmon_t_p65to127); 317 printf("rmon_t_p128to255 %x - %x\n", (int)&fecp->rmon_t_p128to255, 318 fecp->rmon_t_p128to255); 319 printf("rmon_t_p256to511 %x - %x\n", (int)&fecp->rmon_t_p256to511, 320 fecp->rmon_t_p256to511); 321 printf("rmon_t_p512to1023 %x - %x\n", (int)&fecp->rmon_t_p512to1023, 322 fecp->rmon_t_p512to1023); 323 printf("rmon_t_p1024to2047 %x - %x\n", (int)&fecp->rmon_t_p1024to2047, 324 fecp->rmon_t_p1024to2047); 325 printf("rmon_t_p_gte2048 %x - %x\n", (int)&fecp->rmon_t_p_gte2048, 326 fecp->rmon_t_p_gte2048); 327 printf("rmon_t_octets %x - %x\n", (int)&fecp->rmon_t_octets, 328 fecp->rmon_t_octets); 329 330 printf("\n"); 331 printf("ieee_t_drop %x - %x\n", (int)&fecp->ieee_t_drop, 332 fecp->ieee_t_drop); 333 printf("ieee_t_frame_ok %x - %x\n", (int)&fecp->ieee_t_frame_ok, 334 fecp->ieee_t_frame_ok); 335 printf("ieee_t_1col %x - %x\n", (int)&fecp->ieee_t_1col, 336 fecp->ieee_t_1col); 337 printf("ieee_t_mcol %x - %x\n", (int)&fecp->ieee_t_mcol, 338 fecp->ieee_t_mcol); 339 printf("ieee_t_def %x - %x\n", (int)&fecp->ieee_t_def, 340 fecp->ieee_t_def); 341 printf("ieee_t_lcol %x - %x\n", (int)&fecp->ieee_t_lcol, 342 fecp->ieee_t_lcol); 343 printf("ieee_t_excol %x - %x\n", (int)&fecp->ieee_t_excol, 344 fecp->ieee_t_excol); 345 printf("ieee_t_macerr %x - %x\n", (int)&fecp->ieee_t_macerr, 346 fecp->ieee_t_macerr); 347 printf("ieee_t_cserr %x - %x\n", (int)&fecp->ieee_t_cserr, 348 fecp->ieee_t_cserr); 349 printf("ieee_t_sqe %x - %x\n", (int)&fecp->ieee_t_sqe, 350 fecp->ieee_t_sqe); 351 printf("ieee_t_fdxfc %x - %x\n", (int)&fecp->ieee_t_fdxfc, 352 fecp->ieee_t_fdxfc); 353 printf("ieee_t_octets_ok %x - %x\n", (int)&fecp->ieee_t_octets_ok, 354 fecp->ieee_t_octets_ok); 355 356 printf("\n"); 357 printf("rmon_r_drop %x - %x\n", (int)&fecp->rmon_r_drop, 358 fecp->rmon_r_drop); 359 printf("rmon_r_packets %x - %x\n", (int)&fecp->rmon_r_packets, 360 fecp->rmon_r_packets); 361 printf("rmon_r_bc_pkt %x - %x\n", (int)&fecp->rmon_r_bc_pkt, 362 fecp->rmon_r_bc_pkt); 363 printf("rmon_r_mc_pkt %x - %x\n", (int)&fecp->rmon_r_mc_pkt, 364 fecp->rmon_r_mc_pkt); 365 printf("rmon_r_crc_align %x - %x\n", (int)&fecp->rmon_r_crc_align, 366 fecp->rmon_r_crc_align); 367 printf("rmon_r_undersize %x - %x\n", (int)&fecp->rmon_r_undersize, 368 fecp->rmon_r_undersize); 369 printf("rmon_r_oversize %x - %x\n", (int)&fecp->rmon_r_oversize, 370 fecp->rmon_r_oversize); 371 printf("rmon_r_frag %x - %x\n", (int)&fecp->rmon_r_frag, 372 fecp->rmon_r_frag); 373 printf("rmon_r_jab %x - %x\n", (int)&fecp->rmon_r_jab, 374 fecp->rmon_r_jab); 375 printf("rmon_r_p64 %x - %x\n", (int)&fecp->rmon_r_p64, 376 fecp->rmon_r_p64); 377 printf("rmon_r_p65to127 %x - %x\n", (int)&fecp->rmon_r_p65to127, 378 fecp->rmon_r_p65to127); 379 printf("rmon_r_p128to255 %x - %x\n", (int)&fecp->rmon_r_p128to255, 380 fecp->rmon_r_p128to255); 381 printf("rmon_r_p256to511 %x - %x\n", (int)&fecp->rmon_r_p256to511, 382 fecp->rmon_r_p256to511); 383 printf("rmon_r_p512to1023 %x - %x\n", (int)&fecp->rmon_r_p512to1023, 384 fecp->rmon_r_p512to1023); 385 printf("rmon_r_p1024to2047 %x - %x\n", (int)&fecp->rmon_r_p1024to2047, 386 fecp->rmon_r_p1024to2047); 387 printf("rmon_r_p_gte2048 %x - %x\n", (int)&fecp->rmon_r_p_gte2048, 388 fecp->rmon_r_p_gte2048); 389 printf("rmon_r_octets %x - %x\n", (int)&fecp->rmon_r_octets, 390 fecp->rmon_r_octets); 391 392 printf("\n"); 393 printf("ieee_r_drop %x - %x\n", (int)&fecp->ieee_r_drop, 394 fecp->ieee_r_drop); 395 printf("ieee_r_frame_ok %x - %x\n", (int)&fecp->ieee_r_frame_ok, 396 fecp->ieee_r_frame_ok); 397 printf("ieee_r_crc %x - %x\n", (int)&fecp->ieee_r_crc, 398 fecp->ieee_r_crc); 399 printf("ieee_r_align %x - %x\n", (int)&fecp->ieee_r_align, 400 fecp->ieee_r_align); 401 printf("ieee_r_macerr %x - %x\n", (int)&fecp->ieee_r_macerr, 402 fecp->ieee_r_macerr); 403 printf("ieee_r_fdxfc %x - %x\n", (int)&fecp->ieee_r_fdxfc, 404 fecp->ieee_r_fdxfc); 405 printf("ieee_r_octets_ok %x - %x\n", (int)&fecp->ieee_r_octets_ok, 406 fecp->ieee_r_octets_ok); 407 408 printf("\n\n\n"); 409 } 410 #endif 411 412 int fec_init(struct eth_device *dev, bd_t * bd) 413 { 414 struct fec_info_s *info = dev->priv; 415 volatile fec_t *fecp = (fec_t *) (info->iobase); 416 int i; 417 u8 *ea = NULL; 418 419 fecpin_setclear(dev, 1); 420 421 fec_reset(dev); 422 423 #if (CONFIG_COMMANDS & CFG_CMD_MII) || defined (CONFIG_MII) || \ 424 defined (CFG_DISCOVER_PHY) 425 426 mii_init(); 427 428 setFecDuplexSpeed(fecp, bd, info->dup_spd); 429 #else 430 #ifndef CFG_DISCOVER_PHY 431 setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED); 432 #endif /* ifndef CFG_DISCOVER_PHY */ 433 #endif /* CFG_CMD_MII || CONFIG_MII */ 434 435 /* We use strictly polling mode only */ 436 fecp->eimr = 0; 437 438 /* Clear any pending interrupt */ 439 fecp->eir = 0xffffffff; 440 441 /* Set station address */ 442 if ((u32) fecp == CFG_FEC0_IOBASE) { 443 ea = &bd->bi_enetaddr[0]; 444 } else { 445 #ifdef CFG_FEC1_IOBASE 446 ea = &bd->bi_enet1addr[0]; 447 #endif 448 } 449 450 fecp->palr = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); 451 fecp->paur = (ea[4] << 24) | (ea[5] << 16); 452 #ifdef ET_DEBUG 453 printf("Eth Addrs: %02x:%02x:%02x:%02x:%02x:%02x\n", 454 ea[0], ea[1], ea[2], ea[3], ea[4], ea[5]); 455 #endif 456 457 /* Clear unicast address hash table */ 458 fecp->iaur = 0; 459 fecp->ialr = 0; 460 461 /* Clear multicast address hash table */ 462 fecp->gaur = 0; 463 fecp->galr = 0; 464 465 /* Set maximum receive buffer size. */ 466 fecp->emrbr = PKT_MAXBLR_SIZE; 467 468 /* 469 * Setup Buffers and Buffer Desriptors 470 */ 471 info->rxIdx = 0; 472 info->txIdx = 0; 473 474 /* 475 * Setup Receiver Buffer Descriptors (13.14.24.18) 476 * Settings: 477 * Empty, Wrap 478 */ 479 for (i = 0; i < PKTBUFSRX; i++) { 480 info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; 481 info->rxbd[i].cbd_datlen = 0; /* Reset */ 482 info->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i]; 483 } 484 info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; 485 486 /* 487 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) 488 * Settings: 489 * Last, Tx CRC 490 */ 491 for (i = 0; i < TX_BUF_CNT; i++) { 492 info->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC; 493 info->txbd[i].cbd_datlen = 0; /* Reset */ 494 info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]); 495 } 496 info->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; 497 498 /* Set receive and transmit descriptor base */ 499 fecp->erdsr = (unsigned int)(&info->rxbd[0]); 500 fecp->etdsr = (unsigned int)(&info->txbd[0]); 501 502 /* Now enable the transmit and receive processing */ 503 fecp->ecr |= FEC_ECR_ETHER_EN; 504 505 /* And last, try to fill Rx Buffer Descriptors */ 506 fecp->rdar = 0x01000000; /* Descriptor polling active */ 507 508 return 1; 509 } 510 511 void fec_reset(struct eth_device *dev) 512 { 513 struct fec_info_s *info = dev->priv; 514 volatile fec_t *fecp = (fec_t *) (info->iobase); 515 int i; 516 517 fecp->ecr = FEC_ECR_RESET; 518 for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { 519 udelay(1); 520 } 521 if (i == FEC_RESET_DELAY) { 522 printf("FEC_RESET_DELAY timeout\n"); 523 } 524 } 525 526 void fec_halt(struct eth_device *dev) 527 { 528 struct fec_info_s *info = dev->priv; 529 530 fec_reset(dev); 531 532 fecpin_setclear(dev, 0); 533 534 info->rxIdx = info->txIdx = 0; 535 memset(info->rxbd, 0, PKTBUFSRX * sizeof(cbd_t)); 536 memset(info->txbd, 0, TX_BUF_CNT * sizeof(cbd_t)); 537 memset(info->txbuf, 0, DBUF_LENGTH); 538 } 539 540 int mcffec_initialize(bd_t * bis) 541 { 542 struct eth_device *dev; 543 int i; 544 545 for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) { 546 547 dev = 548 (struct eth_device *)memalign(CFG_CACHELINE_SIZE, 549 sizeof *dev); 550 if (dev == NULL) 551 hang(); 552 553 memset(dev, 0, sizeof(*dev)); 554 555 sprintf(dev->name, "FEC%d", fec_info[i].index); 556 557 dev->priv = &fec_info[i]; 558 dev->init = fec_init; 559 dev->halt = fec_halt; 560 dev->send = fec_send; 561 dev->recv = fec_recv; 562 563 /* setup Receive and Transmit buffer descriptor */ 564 fec_info[i].rxbd = 565 (cbd_t *) memalign(CFG_CACHELINE_SIZE, 566 (PKTBUFSRX * sizeof(cbd_t))); 567 fec_info[i].txbd = 568 (cbd_t *) memalign(CFG_CACHELINE_SIZE, 569 (TX_BUF_CNT * sizeof(cbd_t))); 570 fec_info[i].txbuf = 571 (char *)memalign(CFG_CACHELINE_SIZE, DBUF_LENGTH); 572 #ifdef ET_DEBUG 573 printf("rxbd %x txbd %x\n", 574 (int)fec_info[i].rxbd, (int)fec_info[i].txbd); 575 #endif 576 577 fec_info[i].phy_name = (char *)memalign(CFG_CACHELINE_SIZE, 32); 578 579 eth_register(dev); 580 581 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) 582 miiphy_register(dev->name, 583 mcffec_miiphy_read, mcffec_miiphy_write); 584 #endif 585 } 586 587 /* default speed */ 588 bis->bi_ethspeed = 10; 589 590 return 1; 591 } 592 593 #endif /* CFG_CMD_NET, FEC_ENET & NET_MULTI */ 594 #endif /* CONFIG_MCFFEC */ 595