1 /* 2 * (C) Copyright 2000-2004 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * (C) Copyright 2007 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27 #include <common.h> 28 #include <malloc.h> 29 30 #include <asm/fec.h> 31 #include <asm/m5329.h> 32 #include <asm/immap_5329.h> 33 34 #include <command.h> 35 #include <config.h> 36 #include <net.h> 37 #include <miiphy.h> 38 39 #ifdef CONFIG_MCFFEC 40 #undef ET_DEBUG 41 #undef MII_DEBUG 42 43 /* Ethernet Transmit and Receive Buffers */ 44 #define DBUF_LENGTH 1520 45 46 #define TX_BUF_CNT 2 47 48 /* 49 NOTE: PKT_MAXBUF_SIZE must be larger or equal to PKT_MAXBLR_SIZE, 50 see M54455 User Manual for MAX_FL of Receive Control Register for more 51 description. If PKT_MAXBUF_SIZE set to 1518, the FEC bandwidth will 52 reduce to about 20~40% of normal bandwidth. Changing PKT_MAXBLR_SIZE 53 will not make any improvement on speed 54 */ 55 #define PKT_MAXBUF_SIZE 1518 56 #define PKT_MINBUF_SIZE 64 57 #define PKT_MAXBLR_SIZE 1520 58 #define LAST_PKTBUFSRX PKTBUFSRX - 1 59 #define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY) 60 #define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST) 61 62 DECLARE_GLOBAL_DATA_PTR; 63 64 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) 65 66 struct fec_info_s fec_info[] = { 67 #ifdef CFG_FEC0_IOBASE 68 { 69 0, /* index */ 70 CFG_FEC0_IOBASE, /* io base */ 71 CFG_FEC0_PINMUX, /* gpio pin muxing */ 72 CFG_FEC0_MIIBASE, /* mii base */ 73 -1, /* phy_addr */ 74 0, /* duplex and speed */ 75 0, /* phy name */ 76 0, /* phyname init */ 77 0, /* RX BD */ 78 0, /* TX BD */ 79 0, /* rx Index */ 80 0, /* tx Index */ 81 0, /* tx buffer */ 82 0, /* initialized flag */ 83 }, 84 #endif 85 #ifdef CFG_FEC1_IOBASE 86 { 87 1, /* index */ 88 CFG_FEC1_IOBASE, /* io base */ 89 CFG_FEC1_PINMUX, /* gpio pin muxing */ 90 CFG_FEC1_MIIBASE, /* mii base */ 91 -1, /* phy_addr */ 92 0, /* duplex and speed */ 93 0, /* phy name */ 94 0, /* phy name init */ 95 0, /* RX BD */ 96 0, /* TX BD */ 97 0, /* rx Index */ 98 0, /* tx Index */ 99 0, /* tx buffer */ 100 0, /* initialized flag */ 101 } 102 #endif 103 }; 104 105 /* 106 * FEC Ethernet Tx and Rx buffer descriptors allocated at the 107 * immr->udata_bd address on Dual-Port RAM 108 * Provide for Double Buffering 109 */ 110 111 int fec_send(struct eth_device *dev, volatile void *packet, int length); 112 int fec_recv(struct eth_device *dev); 113 int fec_init(struct eth_device *dev, bd_t * bd); 114 void fec_halt(struct eth_device *dev); 115 void fec_reset(struct eth_device *dev); 116 117 extern int fecpin_setclear(struct eth_device *dev, int setclear); 118 119 #ifdef CFG_DISCOVER_PHY 120 extern void mii_init(void); 121 extern uint mii_send(uint mii_cmd); 122 extern int mii_discover_phy(struct eth_device *dev); 123 extern int mcffec_miiphy_read(char *devname, unsigned char addr, 124 unsigned char reg, unsigned short *value); 125 extern int mcffec_miiphy_write(char *devname, unsigned char addr, 126 unsigned char reg, unsigned short value); 127 #endif 128 129 void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd) 130 { 131 if ((dup_spd >> 16) == FULL) { 132 /* Set maximum frame length */ 133 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE | 134 FEC_RCR_PROM | 0x100; 135 fecp->tcr = FEC_TCR_FDEN; 136 } else { 137 /* Half duplex mode */ 138 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | 139 FEC_RCR_MII_MODE | FEC_RCR_DRT; 140 fecp->tcr &= ~FEC_TCR_FDEN; 141 } 142 143 if ((dup_spd & 0xFFFF) == _100BASET) { 144 #ifdef MII_DEBUG 145 printf("100Mbps\n"); 146 #endif 147 bd->bi_ethspeed = 100; 148 } else { 149 #ifdef MII_DEBUG 150 printf("10Mbps\n"); 151 #endif 152 bd->bi_ethspeed = 10; 153 } 154 } 155 156 int fec_send(struct eth_device *dev, volatile void *packet, int length) 157 { 158 struct fec_info_s *info = dev->priv; 159 volatile fec_t *fecp = (fec_t *) (info->iobase); 160 int j, rc; 161 u16 phyStatus; 162 163 miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &phyStatus); 164 165 /* section 16.9.23.3 166 * Wait for ready 167 */ 168 j = 0; 169 while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) && 170 (j < MCFFEC_TOUT_LOOP)) { 171 udelay(1); 172 j++; 173 } 174 if (j >= MCFFEC_TOUT_LOOP) { 175 printf("TX not ready\n"); 176 } 177 178 info->txbd[info->txIdx].cbd_bufaddr = (uint) packet; 179 info->txbd[info->txIdx].cbd_datlen = length; 180 info->txbd[info->txIdx].cbd_sc |= BD_ENET_TX_RDY_LST; 181 182 /* Activate transmit Buffer Descriptor polling */ 183 fecp->tdar = 0x01000000; /* Descriptor polling active */ 184 185 j = 0; 186 while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) && 187 (j < MCFFEC_TOUT_LOOP)) { 188 udelay(1); 189 j++; 190 } 191 if (j >= MCFFEC_TOUT_LOOP) { 192 printf("TX timeout\n"); 193 } 194 #ifdef ET_DEBUG 195 printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n", 196 __FILE__, __LINE__, __FUNCTION__, j, 197 info->txbd[info->txIdx].cbd_sc, 198 (info->txbd[info->txIdx].cbd_sc & 0x003C) >> 2); 199 #endif 200 201 /* return only status bits */ ; 202 rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS); 203 info->txIdx = (info->txIdx + 1) % TX_BUF_CNT; 204 205 return rc; 206 } 207 208 int fec_recv(struct eth_device *dev) 209 { 210 struct fec_info_s *info = dev->priv; 211 volatile fec_t *fecp = (fec_t *) (info->iobase); 212 int length; 213 214 for (;;) { 215 /* section 16.9.23.2 */ 216 if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { 217 length = -1; 218 break; /* nothing received - leave for() loop */ 219 } 220 221 length = info->rxbd[info->rxIdx].cbd_datlen; 222 223 if (info->rxbd[info->rxIdx].cbd_sc & 0x003f) { 224 printf("%s[%d] err: %x\n", 225 __FUNCTION__, __LINE__, 226 info->rxbd[info->rxIdx].cbd_sc); 227 #ifdef ET_DEBUG 228 printf("%s[%d] err: %x\n", 229 __FUNCTION__, __LINE__, 230 info->rxbd[info->rxIdx].cbd_sc); 231 #endif 232 } else { 233 234 length -= 4; 235 /* Pass the packet up to the protocol layers. */ 236 NetReceive(NetRxPackets[info->rxIdx], length); 237 238 fecp->eir |= FEC_EIR_RXF; 239 } 240 241 /* Give the buffer back to the FEC. */ 242 info->rxbd[info->rxIdx].cbd_datlen = 0; 243 244 /* wrap around buffer index when necessary */ 245 if (info->rxIdx == LAST_PKTBUFSRX) { 246 info->rxbd[PKTBUFSRX - 1].cbd_sc = BD_ENET_RX_W_E; 247 info->rxIdx = 0; 248 } else { 249 info->rxbd[info->rxIdx].cbd_sc = BD_ENET_RX_EMPTY; 250 info->rxIdx++; 251 } 252 253 /* Try to fill Buffer Descriptors */ 254 fecp->rdar = 0x01000000; /* Descriptor polling active */ 255 } 256 257 return length; 258 } 259 260 /************************************************************** 261 * 262 * FEC Ethernet Initialization Routine 263 * 264 *************************************************************/ 265 266 #ifdef ET_DEBUG 267 void dbgFecRegs(struct eth_device *dev) 268 { 269 struct fec_info_s *info = dev->priv; 270 volatile fec_t *fecp = (fec_t *) (info->iobase); 271 272 printf("=====\n"); 273 printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir); 274 printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr); 275 printf("r_des_active %x - %x\n", (int)&fecp->rdar, fecp->rdar); 276 printf("x_des_active %x - %x\n", (int)&fecp->tdar, fecp->tdar); 277 printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr); 278 printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr); 279 printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr); 280 printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc); 281 printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr); 282 printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr); 283 printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr); 284 printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur); 285 printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd); 286 printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur); 287 printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr); 288 printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur); 289 printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr); 290 printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr); 291 printf("r_bound %x - %x\n", (int)&fecp->frbr, fecp->frbr); 292 printf("r_fstart %x - %x\n", (int)&fecp->frsr, fecp->frsr); 293 printf("r_drng %x - %x\n", (int)&fecp->erdsr, fecp->erdsr); 294 printf("x_drng %x - %x\n", (int)&fecp->etdsr, fecp->etdsr); 295 printf("r_bufsz %x - %x\n", (int)&fecp->emrbr, fecp->emrbr); 296 297 printf("\n"); 298 printf("rmon_t_drop %x - %x\n", (int)&fecp->rmon_t_drop, 299 fecp->rmon_t_drop); 300 printf("rmon_t_packets %x - %x\n", (int)&fecp->rmon_t_packets, 301 fecp->rmon_t_packets); 302 printf("rmon_t_bc_pkt %x - %x\n", (int)&fecp->rmon_t_bc_pkt, 303 fecp->rmon_t_bc_pkt); 304 printf("rmon_t_mc_pkt %x - %x\n", (int)&fecp->rmon_t_mc_pkt, 305 fecp->rmon_t_mc_pkt); 306 printf("rmon_t_crc_align %x - %x\n", (int)&fecp->rmon_t_crc_align, 307 fecp->rmon_t_crc_align); 308 printf("rmon_t_undersize %x - %x\n", (int)&fecp->rmon_t_undersize, 309 fecp->rmon_t_undersize); 310 printf("rmon_t_oversize %x - %x\n", (int)&fecp->rmon_t_oversize, 311 fecp->rmon_t_oversize); 312 printf("rmon_t_frag %x - %x\n", (int)&fecp->rmon_t_frag, 313 fecp->rmon_t_frag); 314 printf("rmon_t_jab %x - %x\n", (int)&fecp->rmon_t_jab, 315 fecp->rmon_t_jab); 316 printf("rmon_t_col %x - %x\n", (int)&fecp->rmon_t_col, 317 fecp->rmon_t_col); 318 printf("rmon_t_p64 %x - %x\n", (int)&fecp->rmon_t_p64, 319 fecp->rmon_t_p64); 320 printf("rmon_t_p65to127 %x - %x\n", (int)&fecp->rmon_t_p65to127, 321 fecp->rmon_t_p65to127); 322 printf("rmon_t_p128to255 %x - %x\n", (int)&fecp->rmon_t_p128to255, 323 fecp->rmon_t_p128to255); 324 printf("rmon_t_p256to511 %x - %x\n", (int)&fecp->rmon_t_p256to511, 325 fecp->rmon_t_p256to511); 326 printf("rmon_t_p512to1023 %x - %x\n", (int)&fecp->rmon_t_p512to1023, 327 fecp->rmon_t_p512to1023); 328 printf("rmon_t_p1024to2047 %x - %x\n", (int)&fecp->rmon_t_p1024to2047, 329 fecp->rmon_t_p1024to2047); 330 printf("rmon_t_p_gte2048 %x - %x\n", (int)&fecp->rmon_t_p_gte2048, 331 fecp->rmon_t_p_gte2048); 332 printf("rmon_t_octets %x - %x\n", (int)&fecp->rmon_t_octets, 333 fecp->rmon_t_octets); 334 335 printf("\n"); 336 printf("ieee_t_drop %x - %x\n", (int)&fecp->ieee_t_drop, 337 fecp->ieee_t_drop); 338 printf("ieee_t_frame_ok %x - %x\n", (int)&fecp->ieee_t_frame_ok, 339 fecp->ieee_t_frame_ok); 340 printf("ieee_t_1col %x - %x\n", (int)&fecp->ieee_t_1col, 341 fecp->ieee_t_1col); 342 printf("ieee_t_mcol %x - %x\n", (int)&fecp->ieee_t_mcol, 343 fecp->ieee_t_mcol); 344 printf("ieee_t_def %x - %x\n", (int)&fecp->ieee_t_def, 345 fecp->ieee_t_def); 346 printf("ieee_t_lcol %x - %x\n", (int)&fecp->ieee_t_lcol, 347 fecp->ieee_t_lcol); 348 printf("ieee_t_excol %x - %x\n", (int)&fecp->ieee_t_excol, 349 fecp->ieee_t_excol); 350 printf("ieee_t_macerr %x - %x\n", (int)&fecp->ieee_t_macerr, 351 fecp->ieee_t_macerr); 352 printf("ieee_t_cserr %x - %x\n", (int)&fecp->ieee_t_cserr, 353 fecp->ieee_t_cserr); 354 printf("ieee_t_sqe %x - %x\n", (int)&fecp->ieee_t_sqe, 355 fecp->ieee_t_sqe); 356 printf("ieee_t_fdxfc %x - %x\n", (int)&fecp->ieee_t_fdxfc, 357 fecp->ieee_t_fdxfc); 358 printf("ieee_t_octets_ok %x - %x\n", (int)&fecp->ieee_t_octets_ok, 359 fecp->ieee_t_octets_ok); 360 361 printf("\n"); 362 printf("rmon_r_drop %x - %x\n", (int)&fecp->rmon_r_drop, 363 fecp->rmon_r_drop); 364 printf("rmon_r_packets %x - %x\n", (int)&fecp->rmon_r_packets, 365 fecp->rmon_r_packets); 366 printf("rmon_r_bc_pkt %x - %x\n", (int)&fecp->rmon_r_bc_pkt, 367 fecp->rmon_r_bc_pkt); 368 printf("rmon_r_mc_pkt %x - %x\n", (int)&fecp->rmon_r_mc_pkt, 369 fecp->rmon_r_mc_pkt); 370 printf("rmon_r_crc_align %x - %x\n", (int)&fecp->rmon_r_crc_align, 371 fecp->rmon_r_crc_align); 372 printf("rmon_r_undersize %x - %x\n", (int)&fecp->rmon_r_undersize, 373 fecp->rmon_r_undersize); 374 printf("rmon_r_oversize %x - %x\n", (int)&fecp->rmon_r_oversize, 375 fecp->rmon_r_oversize); 376 printf("rmon_r_frag %x - %x\n", (int)&fecp->rmon_r_frag, 377 fecp->rmon_r_frag); 378 printf("rmon_r_jab %x - %x\n", (int)&fecp->rmon_r_jab, 379 fecp->rmon_r_jab); 380 printf("rmon_r_p64 %x - %x\n", (int)&fecp->rmon_r_p64, 381 fecp->rmon_r_p64); 382 printf("rmon_r_p65to127 %x - %x\n", (int)&fecp->rmon_r_p65to127, 383 fecp->rmon_r_p65to127); 384 printf("rmon_r_p128to255 %x - %x\n", (int)&fecp->rmon_r_p128to255, 385 fecp->rmon_r_p128to255); 386 printf("rmon_r_p256to511 %x - %x\n", (int)&fecp->rmon_r_p256to511, 387 fecp->rmon_r_p256to511); 388 printf("rmon_r_p512to1023 %x - %x\n", (int)&fecp->rmon_r_p512to1023, 389 fecp->rmon_r_p512to1023); 390 printf("rmon_r_p1024to2047 %x - %x\n", (int)&fecp->rmon_r_p1024to2047, 391 fecp->rmon_r_p1024to2047); 392 printf("rmon_r_p_gte2048 %x - %x\n", (int)&fecp->rmon_r_p_gte2048, 393 fecp->rmon_r_p_gte2048); 394 printf("rmon_r_octets %x - %x\n", (int)&fecp->rmon_r_octets, 395 fecp->rmon_r_octets); 396 397 printf("\n"); 398 printf("ieee_r_drop %x - %x\n", (int)&fecp->ieee_r_drop, 399 fecp->ieee_r_drop); 400 printf("ieee_r_frame_ok %x - %x\n", (int)&fecp->ieee_r_frame_ok, 401 fecp->ieee_r_frame_ok); 402 printf("ieee_r_crc %x - %x\n", (int)&fecp->ieee_r_crc, 403 fecp->ieee_r_crc); 404 printf("ieee_r_align %x - %x\n", (int)&fecp->ieee_r_align, 405 fecp->ieee_r_align); 406 printf("ieee_r_macerr %x - %x\n", (int)&fecp->ieee_r_macerr, 407 fecp->ieee_r_macerr); 408 printf("ieee_r_fdxfc %x - %x\n", (int)&fecp->ieee_r_fdxfc, 409 fecp->ieee_r_fdxfc); 410 printf("ieee_r_octets_ok %x - %x\n", (int)&fecp->ieee_r_octets_ok, 411 fecp->ieee_r_octets_ok); 412 413 printf("\n\n\n"); 414 } 415 #endif 416 417 int fec_init(struct eth_device *dev, bd_t * bd) 418 { 419 struct fec_info_s *info = dev->priv; 420 volatile fec_t *fecp = (fec_t *) (info->iobase); 421 int i; 422 u8 *ea; 423 424 fecpin_setclear(dev, 1); 425 426 fec_reset(dev); 427 428 #if (CONFIG_COMMANDS & CFG_CMD_MII) || defined (CONFIG_MII) || \ 429 defined (CFG_DISCOVER_PHY) 430 431 mii_init(); 432 433 setFecDuplexSpeed(fecp, bd, info->dup_spd); 434 #else 435 #ifndef CFG_DISCOVER_PHY 436 setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED); 437 #endif /* ifndef CFG_DISCOVER_PHY */ 438 #endif /* CFG_CMD_MII || CONFIG_MII */ 439 440 /* We use strictly polling mode only */ 441 fecp->eimr = 0; 442 443 /* Clear any pending interrupt */ 444 fecp->eir = 0xffffffff; 445 446 /* Set station address */ 447 if ((u32) fecp == CFG_FEC0_IOBASE) { 448 ea = &bd->bi_enetaddr[0]; 449 } else { 450 #ifdef CFG_FEC1_IOBASE 451 ea = &bd->bi_enet1addr[0]; 452 #endif 453 } 454 455 fecp->palr = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); 456 fecp->paur = (ea[4] << 24) | (ea[5] << 16); 457 #ifdef ET_DEBUG 458 printf("Eth Addrs: %02x:%02x:%02x:%02x:%02x:%02x\n", 459 ea[0], ea[1], ea[2], ea[3], ea[4], ea[5]); 460 #endif 461 462 /* Clear unicast address hash table */ 463 fecp->iaur = 0; 464 fecp->ialr = 0; 465 466 /* Clear multicast address hash table */ 467 fecp->gaur = 0; 468 fecp->galr = 0; 469 470 /* Set maximum receive buffer size. */ 471 fecp->emrbr = PKT_MAXBLR_SIZE; 472 473 /* 474 * Setup Buffers and Buffer Desriptors 475 */ 476 info->rxIdx = 0; 477 info->txIdx = 0; 478 479 /* 480 * Setup Receiver Buffer Descriptors (13.14.24.18) 481 * Settings: 482 * Empty, Wrap 483 */ 484 for (i = 0; i < PKTBUFSRX; i++) { 485 info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; 486 info->rxbd[i].cbd_datlen = 0; /* Reset */ 487 info->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i]; 488 } 489 info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; 490 491 /* 492 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) 493 * Settings: 494 * Last, Tx CRC 495 */ 496 for (i = 0; i < TX_BUF_CNT; i++) { 497 info->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC; 498 info->txbd[i].cbd_datlen = 0; /* Reset */ 499 info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]); 500 } 501 info->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; 502 503 /* Set receive and transmit descriptor base */ 504 fecp->erdsr = (unsigned int)(&info->rxbd[0]); 505 fecp->etdsr = (unsigned int)(&info->txbd[0]); 506 507 /* Now enable the transmit and receive processing */ 508 fecp->ecr |= FEC_ECR_ETHER_EN; 509 510 /* And last, try to fill Rx Buffer Descriptors */ 511 fecp->rdar = 0x01000000; /* Descriptor polling active */ 512 513 return 1; 514 } 515 516 void fec_reset(struct eth_device *dev) 517 { 518 struct fec_info_s *info = dev->priv; 519 volatile fec_t *fecp = (fec_t *) (info->iobase); 520 int i; 521 522 fecp->ecr = FEC_ECR_RESET; 523 for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { 524 udelay(1); 525 } 526 if (i == FEC_RESET_DELAY) { 527 printf("FEC_RESET_DELAY timeout\n"); 528 } 529 } 530 531 void fec_halt(struct eth_device *dev) 532 { 533 struct fec_info_s *info = dev->priv; 534 535 fec_reset(dev); 536 537 fecpin_setclear(dev, 0); 538 539 info->rxIdx = info->txIdx = 0; 540 memset(info->rxbd, 0, PKTBUFSRX * sizeof(cbd_t)); 541 memset(info->txbd, 0, TX_BUF_CNT * sizeof(cbd_t)); 542 memset(info->txbuf, 0, DBUF_LENGTH); 543 } 544 545 int mcffec_initialize(bd_t * bis) 546 { 547 struct eth_device *dev; 548 int i; 549 550 for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) { 551 552 dev = (struct eth_device *)malloc(sizeof *dev); 553 if (dev == NULL) 554 hang(); 555 556 memset(dev, 0, sizeof(*dev)); 557 558 sprintf(dev->name, "FEC%d", fec_info[i].index); 559 560 dev->priv = &fec_info[i]; 561 dev->init = fec_init; 562 dev->halt = fec_halt; 563 dev->send = fec_send; 564 dev->recv = fec_recv; 565 566 /* setup Receive and Transmit buffer descriptor */ 567 fec_info[i].rxbd = 568 (cbd_t *) memalign(32, (PKTBUFSRX * sizeof(cbd_t) + 31)); 569 fec_info[i].txbd = 570 (cbd_t *) memalign(32, (TX_BUF_CNT * sizeof(cbd_t) + 31)); 571 fec_info[i].txbuf = (char *)memalign(32, DBUF_LENGTH + 31); 572 #ifdef ET_DEBUG 573 printf("rxbd %x txbd %x\n", 574 (int)fec_info[i].rxbd, (int)fec_info[i].txbd); 575 #endif 576 577 fec_info[i].phy_name = (char *)malloc(32); 578 579 eth_register(dev); 580 581 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) 582 miiphy_register(dev->name, 583 mcffec_miiphy_read, mcffec_miiphy_write); 584 #endif 585 } 586 587 /* default speed */ 588 bis->bi_ethspeed = 10; 589 590 return 1; 591 } 592 593 #endif /* CFG_CMD_NET, FEC_ENET & NET_MULTI */ 594 #endif /* CONFIG_MCFFEC */ 595