1 /* 2 * Copyright (C) 2005-2006 Atmel Corporation 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 8 /* 9 * The u-boot networking stack is a little weird. It seems like the 10 * networking core allocates receive buffers up front without any 11 * regard to the hardware that's supposed to actually receive those 12 * packets. 13 * 14 * The MACB receives packets into 128-byte receive buffers, so the 15 * buffers allocated by the core isn't very practical to use. We'll 16 * allocate our own, but we need one such buffer in case a packet 17 * wraps around the DMA ring so that we have to copy it. 18 * 19 * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific 20 * configuration header. This way, the core allocates one RX buffer 21 * and one TX buffer, each of which can hold a ethernet packet of 22 * maximum size. 23 * 24 * For some reason, the networking core unconditionally specifies a 25 * 32-byte packet "alignment" (which really should be called 26 * "padding"). MACB shouldn't need that, but we'll refrain from any 27 * core modifications here... 28 */ 29 30 #include <net.h> 31 #include <netdev.h> 32 #include <malloc.h> 33 #include <miiphy.h> 34 35 #include <linux/mii.h> 36 #include <asm/io.h> 37 #include <asm/dma-mapping.h> 38 #include <asm/arch/clk.h> 39 #include <asm-generic/errno.h> 40 41 #include "macb.h" 42 43 #define MACB_RX_BUFFER_SIZE 4096 44 #define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128) 45 #define MACB_TX_RING_SIZE 16 46 #define MACB_TX_TIMEOUT 1000 47 #define MACB_AUTONEG_TIMEOUT 5000000 48 49 struct macb_dma_desc { 50 u32 addr; 51 u32 ctrl; 52 }; 53 54 #define RXADDR_USED 0x00000001 55 #define RXADDR_WRAP 0x00000002 56 57 #define RXBUF_FRMLEN_MASK 0x00000fff 58 #define RXBUF_FRAME_START 0x00004000 59 #define RXBUF_FRAME_END 0x00008000 60 #define RXBUF_TYPEID_MATCH 0x00400000 61 #define RXBUF_ADDR4_MATCH 0x00800000 62 #define RXBUF_ADDR3_MATCH 0x01000000 63 #define RXBUF_ADDR2_MATCH 0x02000000 64 #define RXBUF_ADDR1_MATCH 0x04000000 65 #define RXBUF_BROADCAST 0x80000000 66 67 #define TXBUF_FRMLEN_MASK 0x000007ff 68 #define TXBUF_FRAME_END 0x00008000 69 #define TXBUF_NOCRC 0x00010000 70 #define TXBUF_EXHAUSTED 0x08000000 71 #define TXBUF_UNDERRUN 0x10000000 72 #define TXBUF_MAXRETRY 0x20000000 73 #define TXBUF_WRAP 0x40000000 74 #define TXBUF_USED 0x80000000 75 76 struct macb_device { 77 void *regs; 78 79 unsigned int rx_tail; 80 unsigned int tx_head; 81 unsigned int tx_tail; 82 83 void *rx_buffer; 84 void *tx_buffer; 85 struct macb_dma_desc *rx_ring; 86 struct macb_dma_desc *tx_ring; 87 88 unsigned long rx_buffer_dma; 89 unsigned long rx_ring_dma; 90 unsigned long tx_ring_dma; 91 92 const struct device *dev; 93 struct eth_device netdev; 94 unsigned short phy_addr; 95 struct mii_dev *bus; 96 }; 97 #define to_macb(_nd) container_of(_nd, struct macb_device, netdev) 98 99 static int macb_is_gem(struct macb_device *macb) 100 { 101 return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) == 0x2; 102 } 103 104 static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value) 105 { 106 unsigned long netctl; 107 unsigned long netstat; 108 unsigned long frame; 109 110 netctl = macb_readl(macb, NCR); 111 netctl |= MACB_BIT(MPE); 112 macb_writel(macb, NCR, netctl); 113 114 frame = (MACB_BF(SOF, 1) 115 | MACB_BF(RW, 1) 116 | MACB_BF(PHYA, macb->phy_addr) 117 | MACB_BF(REGA, reg) 118 | MACB_BF(CODE, 2) 119 | MACB_BF(DATA, value)); 120 macb_writel(macb, MAN, frame); 121 122 do { 123 netstat = macb_readl(macb, NSR); 124 } while (!(netstat & MACB_BIT(IDLE))); 125 126 netctl = macb_readl(macb, NCR); 127 netctl &= ~MACB_BIT(MPE); 128 macb_writel(macb, NCR, netctl); 129 } 130 131 static u16 macb_mdio_read(struct macb_device *macb, u8 reg) 132 { 133 unsigned long netctl; 134 unsigned long netstat; 135 unsigned long frame; 136 137 netctl = macb_readl(macb, NCR); 138 netctl |= MACB_BIT(MPE); 139 macb_writel(macb, NCR, netctl); 140 141 frame = (MACB_BF(SOF, 1) 142 | MACB_BF(RW, 2) 143 | MACB_BF(PHYA, macb->phy_addr) 144 | MACB_BF(REGA, reg) 145 | MACB_BF(CODE, 2)); 146 macb_writel(macb, MAN, frame); 147 148 do { 149 netstat = macb_readl(macb, NSR); 150 } while (!(netstat & MACB_BIT(IDLE))); 151 152 frame = macb_readl(macb, MAN); 153 154 netctl = macb_readl(macb, NCR); 155 netctl &= ~MACB_BIT(MPE); 156 macb_writel(macb, NCR, netctl); 157 158 return MACB_BFEXT(DATA, frame); 159 } 160 161 void __weak arch_get_mdio_control(const char *name) 162 { 163 return; 164 } 165 166 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 167 168 int macb_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value) 169 { 170 struct eth_device *dev = eth_get_dev_by_name(devname); 171 struct macb_device *macb = to_macb(dev); 172 173 if (macb->phy_addr != phy_adr) 174 return -1; 175 176 arch_get_mdio_control(devname); 177 *value = macb_mdio_read(macb, reg); 178 179 return 0; 180 } 181 182 int macb_miiphy_write(const char *devname, u8 phy_adr, u8 reg, u16 value) 183 { 184 struct eth_device *dev = eth_get_dev_by_name(devname); 185 struct macb_device *macb = to_macb(dev); 186 187 if (macb->phy_addr != phy_adr) 188 return -1; 189 190 arch_get_mdio_control(devname); 191 macb_mdio_write(macb, reg, value); 192 193 return 0; 194 } 195 #endif 196 197 198 #if defined(CONFIG_CMD_NET) 199 200 static int macb_send(struct eth_device *netdev, void *packet, int length) 201 { 202 struct macb_device *macb = to_macb(netdev); 203 unsigned long paddr, ctrl; 204 unsigned int tx_head = macb->tx_head; 205 int i; 206 207 paddr = dma_map_single(packet, length, DMA_TO_DEVICE); 208 209 ctrl = length & TXBUF_FRMLEN_MASK; 210 ctrl |= TXBUF_FRAME_END; 211 if (tx_head == (MACB_TX_RING_SIZE - 1)) { 212 ctrl |= TXBUF_WRAP; 213 macb->tx_head = 0; 214 } else { 215 macb->tx_head++; 216 } 217 218 macb->tx_ring[tx_head].ctrl = ctrl; 219 macb->tx_ring[tx_head].addr = paddr; 220 barrier(); 221 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART)); 222 223 /* 224 * I guess this is necessary because the networking core may 225 * re-use the transmit buffer as soon as we return... 226 */ 227 for (i = 0; i <= MACB_TX_TIMEOUT; i++) { 228 barrier(); 229 ctrl = macb->tx_ring[tx_head].ctrl; 230 if (ctrl & TXBUF_USED) 231 break; 232 udelay(1); 233 } 234 235 dma_unmap_single(packet, length, paddr); 236 237 if (i <= MACB_TX_TIMEOUT) { 238 if (ctrl & TXBUF_UNDERRUN) 239 printf("%s: TX underrun\n", netdev->name); 240 if (ctrl & TXBUF_EXHAUSTED) 241 printf("%s: TX buffers exhausted in mid frame\n", 242 netdev->name); 243 } else { 244 printf("%s: TX timeout\n", netdev->name); 245 } 246 247 /* No one cares anyway */ 248 return 0; 249 } 250 251 static void reclaim_rx_buffers(struct macb_device *macb, 252 unsigned int new_tail) 253 { 254 unsigned int i; 255 256 i = macb->rx_tail; 257 while (i > new_tail) { 258 macb->rx_ring[i].addr &= ~RXADDR_USED; 259 i++; 260 if (i > MACB_RX_RING_SIZE) 261 i = 0; 262 } 263 264 while (i < new_tail) { 265 macb->rx_ring[i].addr &= ~RXADDR_USED; 266 i++; 267 } 268 269 barrier(); 270 macb->rx_tail = new_tail; 271 } 272 273 static int macb_recv(struct eth_device *netdev) 274 { 275 struct macb_device *macb = to_macb(netdev); 276 unsigned int rx_tail = macb->rx_tail; 277 void *buffer; 278 int length; 279 int wrapped = 0; 280 u32 status; 281 282 for (;;) { 283 if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED)) 284 return -1; 285 286 status = macb->rx_ring[rx_tail].ctrl; 287 if (status & RXBUF_FRAME_START) { 288 if (rx_tail != macb->rx_tail) 289 reclaim_rx_buffers(macb, rx_tail); 290 wrapped = 0; 291 } 292 293 if (status & RXBUF_FRAME_END) { 294 buffer = macb->rx_buffer + 128 * macb->rx_tail; 295 length = status & RXBUF_FRMLEN_MASK; 296 if (wrapped) { 297 unsigned int headlen, taillen; 298 299 headlen = 128 * (MACB_RX_RING_SIZE 300 - macb->rx_tail); 301 taillen = length - headlen; 302 memcpy((void *)NetRxPackets[0], 303 buffer, headlen); 304 memcpy((void *)NetRxPackets[0] + headlen, 305 macb->rx_buffer, taillen); 306 buffer = (void *)NetRxPackets[0]; 307 } 308 309 NetReceive(buffer, length); 310 if (++rx_tail >= MACB_RX_RING_SIZE) 311 rx_tail = 0; 312 reclaim_rx_buffers(macb, rx_tail); 313 } else { 314 if (++rx_tail >= MACB_RX_RING_SIZE) { 315 wrapped = 1; 316 rx_tail = 0; 317 } 318 } 319 barrier(); 320 } 321 322 return 0; 323 } 324 325 static void macb_phy_reset(struct macb_device *macb) 326 { 327 struct eth_device *netdev = &macb->netdev; 328 int i; 329 u16 status, adv; 330 331 adv = ADVERTISE_CSMA | ADVERTISE_ALL; 332 macb_mdio_write(macb, MII_ADVERTISE, adv); 333 printf("%s: Starting autonegotiation...\n", netdev->name); 334 macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE 335 | BMCR_ANRESTART)); 336 337 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) { 338 status = macb_mdio_read(macb, MII_BMSR); 339 if (status & BMSR_ANEGCOMPLETE) 340 break; 341 udelay(100); 342 } 343 344 if (status & BMSR_ANEGCOMPLETE) 345 printf("%s: Autonegotiation complete\n", netdev->name); 346 else 347 printf("%s: Autonegotiation timed out (status=0x%04x)\n", 348 netdev->name, status); 349 } 350 351 #ifdef CONFIG_MACB_SEARCH_PHY 352 static int macb_phy_find(struct macb_device *macb) 353 { 354 int i; 355 u16 phy_id; 356 357 /* Search for PHY... */ 358 for (i = 0; i < 32; i++) { 359 macb->phy_addr = i; 360 phy_id = macb_mdio_read(macb, MII_PHYSID1); 361 if (phy_id != 0xffff) { 362 printf("%s: PHY present at %d\n", macb->netdev.name, i); 363 return 1; 364 } 365 } 366 367 /* PHY isn't up to snuff */ 368 printf("%s: PHY not found\n", macb->netdev.name); 369 370 return 0; 371 } 372 #endif /* CONFIG_MACB_SEARCH_PHY */ 373 374 375 static int macb_phy_init(struct macb_device *macb) 376 { 377 struct eth_device *netdev = &macb->netdev; 378 #ifdef CONFIG_PHYLIB 379 struct phy_device *phydev; 380 #endif 381 u32 ncfgr; 382 u16 phy_id, status, adv, lpa; 383 int media, speed, duplex; 384 int i; 385 386 arch_get_mdio_control(netdev->name); 387 #ifdef CONFIG_MACB_SEARCH_PHY 388 /* Auto-detect phy_addr */ 389 if (!macb_phy_find(macb)) 390 return 0; 391 #endif /* CONFIG_MACB_SEARCH_PHY */ 392 393 /* Check if the PHY is up to snuff... */ 394 phy_id = macb_mdio_read(macb, MII_PHYSID1); 395 if (phy_id == 0xffff) { 396 printf("%s: No PHY present\n", netdev->name); 397 return 0; 398 } 399 400 #ifdef CONFIG_PHYLIB 401 /* need to consider other phy interface mode */ 402 phydev = phy_connect(macb->bus, macb->phy_addr, netdev, 403 PHY_INTERFACE_MODE_RGMII); 404 if (!phydev) { 405 printf("phy_connect failed\n"); 406 return -ENODEV; 407 } 408 409 phy_config(phydev); 410 #endif 411 412 status = macb_mdio_read(macb, MII_BMSR); 413 if (!(status & BMSR_LSTATUS)) { 414 /* Try to re-negotiate if we don't have link already. */ 415 macb_phy_reset(macb); 416 417 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) { 418 status = macb_mdio_read(macb, MII_BMSR); 419 if (status & BMSR_LSTATUS) 420 break; 421 udelay(100); 422 } 423 } 424 425 if (!(status & BMSR_LSTATUS)) { 426 printf("%s: link down (status: 0x%04x)\n", 427 netdev->name, status); 428 return 0; 429 } 430 431 /* First check for GMAC */ 432 if (macb_is_gem(macb)) { 433 lpa = macb_mdio_read(macb, MII_STAT1000); 434 if (lpa & (1 << 11)) { 435 speed = 1000; 436 duplex = 1; 437 } else { 438 if (lpa & (1 << 10)) { 439 speed = 1000; 440 duplex = 1; 441 } else { 442 speed = 0; 443 } 444 } 445 446 if (speed == 1000) { 447 printf("%s: link up, %dMbps %s-duplex (lpa: 0x%04x)\n", 448 netdev->name, 449 speed, 450 duplex ? "full" : "half", 451 lpa); 452 453 ncfgr = macb_readl(macb, NCFGR); 454 ncfgr &= ~(GEM_BIT(GBE) | MACB_BIT(SPD) | MACB_BIT(FD)); 455 if (speed) 456 ncfgr |= GEM_BIT(GBE); 457 if (duplex) 458 ncfgr |= MACB_BIT(FD); 459 macb_writel(macb, NCFGR, ncfgr); 460 461 return 1; 462 } 463 } 464 465 /* fall back for EMAC checking */ 466 adv = macb_mdio_read(macb, MII_ADVERTISE); 467 lpa = macb_mdio_read(macb, MII_LPA); 468 media = mii_nway_result(lpa & adv); 469 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) 470 ? 1 : 0); 471 duplex = (media & ADVERTISE_FULL) ? 1 : 0; 472 printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n", 473 netdev->name, 474 speed ? "100" : "10", 475 duplex ? "full" : "half", 476 lpa); 477 478 ncfgr = macb_readl(macb, NCFGR); 479 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); 480 if (speed) 481 ncfgr |= MACB_BIT(SPD); 482 if (duplex) 483 ncfgr |= MACB_BIT(FD); 484 macb_writel(macb, NCFGR, ncfgr); 485 486 return 1; 487 } 488 489 static int macb_init(struct eth_device *netdev, bd_t *bd) 490 { 491 struct macb_device *macb = to_macb(netdev); 492 unsigned long paddr; 493 int i; 494 495 /* 496 * macb_halt should have been called at some point before now, 497 * so we'll assume the controller is idle. 498 */ 499 500 /* initialize DMA descriptors */ 501 paddr = macb->rx_buffer_dma; 502 for (i = 0; i < MACB_RX_RING_SIZE; i++) { 503 if (i == (MACB_RX_RING_SIZE - 1)) 504 paddr |= RXADDR_WRAP; 505 macb->rx_ring[i].addr = paddr; 506 macb->rx_ring[i].ctrl = 0; 507 paddr += 128; 508 } 509 for (i = 0; i < MACB_TX_RING_SIZE; i++) { 510 macb->tx_ring[i].addr = 0; 511 if (i == (MACB_TX_RING_SIZE - 1)) 512 macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP; 513 else 514 macb->tx_ring[i].ctrl = TXBUF_USED; 515 } 516 macb->rx_tail = 0; 517 macb->tx_head = 0; 518 macb->tx_tail = 0; 519 520 macb_writel(macb, RBQP, macb->rx_ring_dma); 521 macb_writel(macb, TBQP, macb->tx_ring_dma); 522 523 if (macb_is_gem(macb)) { 524 #ifdef CONFIG_RGMII 525 gem_writel(macb, UR, GEM_BIT(RGMII)); 526 #else 527 gem_writel(macb, UR, 0); 528 #endif 529 } else { 530 /* choose RMII or MII mode. This depends on the board */ 531 #ifdef CONFIG_RMII 532 #ifdef CONFIG_AT91FAMILY 533 macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN)); 534 #else 535 macb_writel(macb, USRIO, 0); 536 #endif 537 #else 538 #ifdef CONFIG_AT91FAMILY 539 macb_writel(macb, USRIO, MACB_BIT(CLKEN)); 540 #else 541 macb_writel(macb, USRIO, MACB_BIT(MII)); 542 #endif 543 #endif /* CONFIG_RMII */ 544 } 545 546 if (!macb_phy_init(macb)) 547 return -1; 548 549 /* Enable TX and RX */ 550 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE)); 551 552 return 0; 553 } 554 555 static void macb_halt(struct eth_device *netdev) 556 { 557 struct macb_device *macb = to_macb(netdev); 558 u32 ncr, tsr; 559 560 /* Halt the controller and wait for any ongoing transmission to end. */ 561 ncr = macb_readl(macb, NCR); 562 ncr |= MACB_BIT(THALT); 563 macb_writel(macb, NCR, ncr); 564 565 do { 566 tsr = macb_readl(macb, TSR); 567 } while (tsr & MACB_BIT(TGO)); 568 569 /* Disable TX and RX, and clear statistics */ 570 macb_writel(macb, NCR, MACB_BIT(CLRSTAT)); 571 } 572 573 static int macb_write_hwaddr(struct eth_device *dev) 574 { 575 struct macb_device *macb = to_macb(dev); 576 u32 hwaddr_bottom; 577 u16 hwaddr_top; 578 579 /* set hardware address */ 580 hwaddr_bottom = dev->enetaddr[0] | dev->enetaddr[1] << 8 | 581 dev->enetaddr[2] << 16 | dev->enetaddr[3] << 24; 582 macb_writel(macb, SA1B, hwaddr_bottom); 583 hwaddr_top = dev->enetaddr[4] | dev->enetaddr[5] << 8; 584 macb_writel(macb, SA1T, hwaddr_top); 585 return 0; 586 } 587 588 static u32 macb_mdc_clk_div(int id, struct macb_device *macb) 589 { 590 u32 config; 591 unsigned long macb_hz = get_macb_pclk_rate(id); 592 593 if (macb_hz < 20000000) 594 config = MACB_BF(CLK, MACB_CLK_DIV8); 595 else if (macb_hz < 40000000) 596 config = MACB_BF(CLK, MACB_CLK_DIV16); 597 else if (macb_hz < 80000000) 598 config = MACB_BF(CLK, MACB_CLK_DIV32); 599 else 600 config = MACB_BF(CLK, MACB_CLK_DIV64); 601 602 return config; 603 } 604 605 static u32 gem_mdc_clk_div(int id, struct macb_device *macb) 606 { 607 u32 config; 608 unsigned long macb_hz = get_macb_pclk_rate(id); 609 610 if (macb_hz < 20000000) 611 config = GEM_BF(CLK, GEM_CLK_DIV8); 612 else if (macb_hz < 40000000) 613 config = GEM_BF(CLK, GEM_CLK_DIV16); 614 else if (macb_hz < 80000000) 615 config = GEM_BF(CLK, GEM_CLK_DIV32); 616 else if (macb_hz < 120000000) 617 config = GEM_BF(CLK, GEM_CLK_DIV48); 618 else if (macb_hz < 160000000) 619 config = GEM_BF(CLK, GEM_CLK_DIV64); 620 else 621 config = GEM_BF(CLK, GEM_CLK_DIV96); 622 623 return config; 624 } 625 626 /* 627 * Get the DMA bus width field of the network configuration register that we 628 * should program. We find the width from decoding the design configuration 629 * register to find the maximum supported data bus width. 630 */ 631 static u32 macb_dbw(struct macb_device *macb) 632 { 633 switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) { 634 case 4: 635 return GEM_BF(DBW, GEM_DBW128); 636 case 2: 637 return GEM_BF(DBW, GEM_DBW64); 638 case 1: 639 default: 640 return GEM_BF(DBW, GEM_DBW32); 641 } 642 } 643 644 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) 645 { 646 struct macb_device *macb; 647 struct eth_device *netdev; 648 u32 ncfgr; 649 650 macb = malloc(sizeof(struct macb_device)); 651 if (!macb) { 652 printf("Error: Failed to allocate memory for MACB%d\n", id); 653 return -1; 654 } 655 memset(macb, 0, sizeof(struct macb_device)); 656 657 netdev = &macb->netdev; 658 659 macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE, 660 &macb->rx_buffer_dma); 661 macb->rx_ring = dma_alloc_coherent(MACB_RX_RING_SIZE 662 * sizeof(struct macb_dma_desc), 663 &macb->rx_ring_dma); 664 macb->tx_ring = dma_alloc_coherent(MACB_TX_RING_SIZE 665 * sizeof(struct macb_dma_desc), 666 &macb->tx_ring_dma); 667 668 macb->regs = regs; 669 macb->phy_addr = phy_addr; 670 671 if (macb_is_gem(macb)) 672 sprintf(netdev->name, "gmac%d", id); 673 else 674 sprintf(netdev->name, "macb%d", id); 675 676 netdev->init = macb_init; 677 netdev->halt = macb_halt; 678 netdev->send = macb_send; 679 netdev->recv = macb_recv; 680 netdev->write_hwaddr = macb_write_hwaddr; 681 682 /* 683 * Do some basic initialization so that we at least can talk 684 * to the PHY 685 */ 686 if (macb_is_gem(macb)) { 687 ncfgr = gem_mdc_clk_div(id, macb); 688 ncfgr |= macb_dbw(macb); 689 } else { 690 ncfgr = macb_mdc_clk_div(id, macb); 691 } 692 693 macb_writel(macb, NCFGR, ncfgr); 694 695 eth_register(netdev); 696 697 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 698 miiphy_register(netdev->name, macb_miiphy_read, macb_miiphy_write); 699 macb->bus = miiphy_get_dev_by_name(netdev->name); 700 #endif 701 return 0; 702 } 703 704 #endif 705