1*44937214SPrabhakar Kushwaha /* 2*44937214SPrabhakar Kushwaha * Copyright 2015 Freescale Semiconductor, Inc. 3*44937214SPrabhakar Kushwaha * 4*44937214SPrabhakar Kushwaha * SPDX-License-Identifier: GPL-2.0+ 5*44937214SPrabhakar Kushwaha */ 6*44937214SPrabhakar Kushwaha #include <common.h> 7*44937214SPrabhakar Kushwaha #include <phy.h> 8*44937214SPrabhakar Kushwaha #include <fsl-mc/ldpaa_wriop.h> 9*44937214SPrabhakar Kushwaha #include <asm/io.h> 10*44937214SPrabhakar Kushwaha #include <asm/arch/fsl_serdes.h> 11*44937214SPrabhakar Kushwaha 12*44937214SPrabhakar Kushwaha u32 dpmac_to_devdisr[] = { 13*44937214SPrabhakar Kushwaha [WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1, 14*44937214SPrabhakar Kushwaha [WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2, 15*44937214SPrabhakar Kushwaha [WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3, 16*44937214SPrabhakar Kushwaha [WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4, 17*44937214SPrabhakar Kushwaha [WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5, 18*44937214SPrabhakar Kushwaha [WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6, 19*44937214SPrabhakar Kushwaha [WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7, 20*44937214SPrabhakar Kushwaha [WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8, 21*44937214SPrabhakar Kushwaha [WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9, 22*44937214SPrabhakar Kushwaha [WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10, 23*44937214SPrabhakar Kushwaha [WRIOP1_DPMAC11] = FSL_CHASSIS3_DEVDISR2_DPMAC11, 24*44937214SPrabhakar Kushwaha [WRIOP1_DPMAC12] = FSL_CHASSIS3_DEVDISR2_DPMAC12, 25*44937214SPrabhakar Kushwaha [WRIOP1_DPMAC13] = FSL_CHASSIS3_DEVDISR2_DPMAC13, 26*44937214SPrabhakar Kushwaha [WRIOP1_DPMAC14] = FSL_CHASSIS3_DEVDISR2_DPMAC14, 27*44937214SPrabhakar Kushwaha [WRIOP1_DPMAC15] = FSL_CHASSIS3_DEVDISR2_DPMAC15, 28*44937214SPrabhakar Kushwaha [WRIOP1_DPMAC16] = FSL_CHASSIS3_DEVDISR2_DPMAC16, 29*44937214SPrabhakar Kushwaha [WRIOP1_DPMAC17] = FSL_CHASSIS3_DEVDISR2_DPMAC17, 30*44937214SPrabhakar Kushwaha [WRIOP1_DPMAC18] = FSL_CHASSIS3_DEVDISR2_DPMAC18, 31*44937214SPrabhakar Kushwaha [WRIOP1_DPMAC19] = FSL_CHASSIS3_DEVDISR2_DPMAC19, 32*44937214SPrabhakar Kushwaha [WRIOP1_DPMAC20] = FSL_CHASSIS3_DEVDISR2_DPMAC20, 33*44937214SPrabhakar Kushwaha [WRIOP1_DPMAC21] = FSL_CHASSIS3_DEVDISR2_DPMAC21, 34*44937214SPrabhakar Kushwaha [WRIOP1_DPMAC22] = FSL_CHASSIS3_DEVDISR2_DPMAC22, 35*44937214SPrabhakar Kushwaha [WRIOP1_DPMAC23] = FSL_CHASSIS3_DEVDISR2_DPMAC23, 36*44937214SPrabhakar Kushwaha [WRIOP1_DPMAC24] = FSL_CHASSIS3_DEVDISR2_DPMAC24, 37*44937214SPrabhakar Kushwaha }; 38*44937214SPrabhakar Kushwaha 39*44937214SPrabhakar Kushwaha static int is_device_disabled(int dpmac_id) 40*44937214SPrabhakar Kushwaha { 41*44937214SPrabhakar Kushwaha struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; 42*44937214SPrabhakar Kushwaha u32 devdisr2 = in_le32(&gur->devdisr2); 43*44937214SPrabhakar Kushwaha 44*44937214SPrabhakar Kushwaha return dpmac_to_devdisr[dpmac_id] & devdisr2; 45*44937214SPrabhakar Kushwaha } 46*44937214SPrabhakar Kushwaha 47*44937214SPrabhakar Kushwaha void wriop_dpmac_disable(int dpmac_id) 48*44937214SPrabhakar Kushwaha { 49*44937214SPrabhakar Kushwaha struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; 50*44937214SPrabhakar Kushwaha 51*44937214SPrabhakar Kushwaha setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]); 52*44937214SPrabhakar Kushwaha } 53*44937214SPrabhakar Kushwaha 54*44937214SPrabhakar Kushwaha void wriop_dpmac_enable(int dpmac_id) 55*44937214SPrabhakar Kushwaha { 56*44937214SPrabhakar Kushwaha struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; 57*44937214SPrabhakar Kushwaha 58*44937214SPrabhakar Kushwaha clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]); 59*44937214SPrabhakar Kushwaha } 60*44937214SPrabhakar Kushwaha 61*44937214SPrabhakar Kushwaha phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl) 62*44937214SPrabhakar Kushwaha { 63*44937214SPrabhakar Kushwaha enum srds_prtcl; 64*44937214SPrabhakar Kushwaha 65*44937214SPrabhakar Kushwaha if (is_device_disabled(dpmac_id + 1)) 66*44937214SPrabhakar Kushwaha return PHY_INTERFACE_MODE_NONE; 67*44937214SPrabhakar Kushwaha 68*44937214SPrabhakar Kushwaha if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII16) 69*44937214SPrabhakar Kushwaha return PHY_INTERFACE_MODE_SGMII; 70*44937214SPrabhakar Kushwaha 71*44937214SPrabhakar Kushwaha if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8) 72*44937214SPrabhakar Kushwaha return PHY_INTERFACE_MODE_XGMII; 73*44937214SPrabhakar Kushwaha 74*44937214SPrabhakar Kushwaha if (lane_prtcl >= XAUI1 && lane_prtcl <= XAUI2) 75*44937214SPrabhakar Kushwaha return PHY_INTERFACE_MODE_XGMII; 76*44937214SPrabhakar Kushwaha 77*44937214SPrabhakar Kushwaha if (lane_prtcl >= QSGMII_A && lane_prtcl <= QSGMII_D) 78*44937214SPrabhakar Kushwaha return PHY_INTERFACE_MODE_QSGMII; 79*44937214SPrabhakar Kushwaha 80*44937214SPrabhakar Kushwaha return PHY_INTERFACE_MODE_NONE; 81*44937214SPrabhakar Kushwaha } 82