1 /* 2 * Ethernet driver for TI K2HK EVM. 3 * 4 * (C) Copyright 2012-2014 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 #include <common.h> 10 #include <command.h> 11 12 #include <net.h> 13 #include <phy.h> 14 #include <errno.h> 15 #include <miiphy.h> 16 #include <malloc.h> 17 #include <asm/ti-common/keystone_nav.h> 18 #include <asm/ti-common/keystone_net.h> 19 #include <asm/ti-common/keystone_serdes.h> 20 21 unsigned int emac_open; 22 static struct mii_dev *mdio_bus; 23 static unsigned int sys_has_mdio = 1; 24 25 #ifdef KEYSTONE2_EMAC_GIG_ENABLE 26 #define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x) 27 #else 28 #define emac_gigabit_enable(x) /* no gigabit to enable */ 29 #endif 30 31 #define RX_BUFF_NUMS 24 32 #define RX_BUFF_LEN 1520 33 #define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN 34 #define SGMII_ANEG_TIMEOUT 4000 35 36 static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16); 37 38 struct rx_buff_desc net_rx_buffs = { 39 .buff_ptr = rx_buffs, 40 .num_buffs = RX_BUFF_NUMS, 41 .buff_len = RX_BUFF_LEN, 42 .rx_flow = 22, 43 }; 44 45 #ifndef CONFIG_SOC_K2G 46 static void keystone2_net_serdes_setup(void); 47 #endif 48 49 int keystone2_eth_read_mac_addr(struct eth_device *dev) 50 { 51 struct eth_priv_t *eth_priv; 52 u32 maca = 0; 53 u32 macb = 0; 54 55 eth_priv = (struct eth_priv_t *)dev->priv; 56 57 /* Read the e-fuse mac address */ 58 if (eth_priv->slave_port == 1) { 59 maca = __raw_readl(MAC_ID_BASE_ADDR); 60 macb = __raw_readl(MAC_ID_BASE_ADDR + 4); 61 } 62 63 dev->enetaddr[0] = (macb >> 8) & 0xff; 64 dev->enetaddr[1] = (macb >> 0) & 0xff; 65 dev->enetaddr[2] = (maca >> 24) & 0xff; 66 dev->enetaddr[3] = (maca >> 16) & 0xff; 67 dev->enetaddr[4] = (maca >> 8) & 0xff; 68 dev->enetaddr[5] = (maca >> 0) & 0xff; 69 70 return 0; 71 } 72 73 /* MDIO */ 74 75 static int keystone2_mdio_reset(struct mii_dev *bus) 76 { 77 u_int32_t clkdiv; 78 struct mdio_regs *adap_mdio = bus->priv; 79 80 clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; 81 82 writel((clkdiv & 0xffff) | MDIO_CONTROL_ENABLE | 83 MDIO_CONTROL_FAULT | MDIO_CONTROL_FAULT_ENABLE, 84 &adap_mdio->control); 85 86 while (readl(&adap_mdio->control) & MDIO_CONTROL_IDLE) 87 ; 88 89 return 0; 90 } 91 92 /** 93 * keystone2_mdio_read - read a PHY register via MDIO interface. 94 * Blocks until operation is complete. 95 */ 96 static int keystone2_mdio_read(struct mii_dev *bus, 97 int addr, int devad, int reg) 98 { 99 int tmp; 100 struct mdio_regs *adap_mdio = bus->priv; 101 102 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO) 103 ; 104 105 writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_READ | 106 ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16), 107 &adap_mdio->useraccess0); 108 109 /* Wait for command to complete */ 110 while ((tmp = readl(&adap_mdio->useraccess0)) & MDIO_USERACCESS0_GO) 111 ; 112 113 if (tmp & MDIO_USERACCESS0_ACK) 114 return tmp & 0xffff; 115 116 return -1; 117 } 118 119 /** 120 * keystone2_mdio_write - write to a PHY register via MDIO interface. 121 * Blocks until operation is complete. 122 */ 123 static int keystone2_mdio_write(struct mii_dev *bus, 124 int addr, int devad, int reg, u16 val) 125 { 126 struct mdio_regs *adap_mdio = bus->priv; 127 128 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO) 129 ; 130 131 writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_WRITE | 132 ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16) | 133 (val & 0xffff), &adap_mdio->useraccess0); 134 135 /* Wait for command to complete */ 136 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO) 137 ; 138 139 return 0; 140 } 141 142 static void __attribute__((unused)) 143 keystone2_eth_gigabit_enable(struct eth_device *dev) 144 { 145 u_int16_t data; 146 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; 147 148 if (sys_has_mdio) { 149 data = keystone2_mdio_read(mdio_bus, eth_priv->phy_addr, 150 MDIO_DEVAD_NONE, 0); 151 /* speed selection MSB */ 152 if (!(data & (1 << 6))) 153 return; 154 } 155 156 /* 157 * Check if link detected is giga-bit 158 * If Gigabit mode detected, enable gigbit in MAC 159 */ 160 writel(readl(DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + 161 CPGMACSL_REG_CTL) | 162 EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE, 163 DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + CPGMACSL_REG_CTL); 164 } 165 166 #ifdef CONFIG_SOC_K2G 167 int keystone_rgmii_config(struct phy_device *phy_dev) 168 { 169 unsigned int i, status; 170 171 i = 0; 172 do { 173 if (i > SGMII_ANEG_TIMEOUT) { 174 puts(" TIMEOUT !\n"); 175 phy_dev->link = 0; 176 return 0; 177 } 178 179 if (ctrlc()) { 180 puts("user interrupt!\n"); 181 phy_dev->link = 0; 182 return -EINTR; 183 } 184 185 if ((i++ % 500) == 0) 186 printf("."); 187 188 udelay(1000); /* 1 ms */ 189 status = readl(RGMII_STATUS_REG); 190 } while (!(status & RGMII_REG_STATUS_LINK)); 191 192 puts(" done\n"); 193 194 return 0; 195 } 196 #else 197 int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface) 198 { 199 unsigned int i, status, mask; 200 unsigned int mr_adv_ability, control; 201 202 switch (interface) { 203 case SGMII_LINK_MAC_MAC_AUTONEG: 204 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE | 205 SGMII_REG_MR_ADV_LINK | 206 SGMII_REG_MR_ADV_FULL_DUPLEX | 207 SGMII_REG_MR_ADV_GIG_MODE); 208 control = (SGMII_REG_CONTROL_MASTER | 209 SGMII_REG_CONTROL_AUTONEG); 210 211 break; 212 case SGMII_LINK_MAC_PHY: 213 case SGMII_LINK_MAC_PHY_FORCED: 214 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE; 215 control = SGMII_REG_CONTROL_AUTONEG; 216 217 break; 218 case SGMII_LINK_MAC_MAC_FORCED: 219 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE | 220 SGMII_REG_MR_ADV_LINK | 221 SGMII_REG_MR_ADV_FULL_DUPLEX | 222 SGMII_REG_MR_ADV_GIG_MODE); 223 control = SGMII_REG_CONTROL_MASTER; 224 225 break; 226 case SGMII_LINK_MAC_FIBER: 227 mr_adv_ability = 0x20; 228 control = SGMII_REG_CONTROL_AUTONEG; 229 230 break; 231 default: 232 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE; 233 control = SGMII_REG_CONTROL_AUTONEG; 234 } 235 236 __raw_writel(0, SGMII_CTL_REG(port)); 237 238 /* 239 * Wait for the SerDes pll to lock, 240 * but don't trap if lock is never read 241 */ 242 for (i = 0; i < 1000; i++) { 243 udelay(2000); 244 status = __raw_readl(SGMII_STATUS_REG(port)); 245 if ((status & SGMII_REG_STATUS_LOCK) != 0) 246 break; 247 } 248 249 __raw_writel(mr_adv_ability, SGMII_MRADV_REG(port)); 250 __raw_writel(control, SGMII_CTL_REG(port)); 251 252 253 mask = SGMII_REG_STATUS_LINK; 254 255 if (control & SGMII_REG_CONTROL_AUTONEG) 256 mask |= SGMII_REG_STATUS_AUTONEG; 257 258 status = __raw_readl(SGMII_STATUS_REG(port)); 259 if ((status & mask) == mask) 260 return 0; 261 262 printf("\n%s Waiting for SGMII auto negotiation to complete", 263 phy_dev->dev->name); 264 while ((status & mask) != mask) { 265 /* 266 * Timeout reached ? 267 */ 268 if (i > SGMII_ANEG_TIMEOUT) { 269 puts(" TIMEOUT !\n"); 270 phy_dev->link = 0; 271 return 0; 272 } 273 274 if (ctrlc()) { 275 puts("user interrupt!\n"); 276 phy_dev->link = 0; 277 return -EINTR; 278 } 279 280 if ((i++ % 500) == 0) 281 printf("."); 282 283 udelay(1000); /* 1 ms */ 284 status = __raw_readl(SGMII_STATUS_REG(port)); 285 } 286 puts(" done\n"); 287 288 return 0; 289 } 290 #endif 291 292 int mac_sl_reset(u32 port) 293 { 294 u32 i, v; 295 296 if (port >= DEVICE_N_GMACSL_PORTS) 297 return GMACSL_RET_INVALID_PORT; 298 299 /* Set the soft reset bit */ 300 writel(CPGMAC_REG_RESET_VAL_RESET, 301 DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET); 302 303 /* Wait for the bit to clear */ 304 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) { 305 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET); 306 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) != 307 CPGMAC_REG_RESET_VAL_RESET) 308 return GMACSL_RET_OK; 309 } 310 311 /* Timeout on the reset */ 312 return GMACSL_RET_WARN_RESET_INCOMPLETE; 313 } 314 315 int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg) 316 { 317 u32 v, i; 318 int ret = GMACSL_RET_OK; 319 320 if (port >= DEVICE_N_GMACSL_PORTS) 321 return GMACSL_RET_INVALID_PORT; 322 323 if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) { 324 cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN; 325 ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG; 326 } 327 328 /* Must wait if the device is undergoing reset */ 329 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) { 330 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET); 331 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) != 332 CPGMAC_REG_RESET_VAL_RESET) 333 break; 334 } 335 336 if (i == DEVICE_EMACSL_RESET_POLL_COUNT) 337 return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE; 338 339 writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN); 340 writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL); 341 342 #ifndef CONFIG_SOC_K2HK 343 /* Map RX packet flow priority to 0 */ 344 writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP); 345 #endif 346 347 return ret; 348 } 349 350 int ethss_config(u32 ctl, u32 max_pkt_size) 351 { 352 u32 i; 353 354 /* Max length register */ 355 writel(max_pkt_size, DEVICE_CPSW_BASE + CPSW_REG_MAXLEN); 356 357 /* Control register */ 358 writel(ctl, DEVICE_CPSW_BASE + CPSW_REG_CTL); 359 360 /* All statistics enabled by default */ 361 writel(CPSW_REG_VAL_STAT_ENABLE_ALL, 362 DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN); 363 364 /* Reset and enable the ALE */ 365 writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE | 366 CPSW_REG_VAL_ALE_CTL_BYPASS, 367 DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL); 368 369 /* All ports put into forward mode */ 370 for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++) 371 writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE, 372 DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i)); 373 374 return 0; 375 } 376 377 int ethss_start(void) 378 { 379 int i; 380 struct mac_sl_cfg cfg; 381 382 cfg.max_rx_len = MAX_SIZE_STREAM_BUFFER; 383 cfg.ctl = GMACSL_ENABLE | GMACSL_RX_ENABLE_EXT_CTL; 384 385 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) { 386 mac_sl_reset(i); 387 mac_sl_config(i, &cfg); 388 } 389 390 return 0; 391 } 392 393 int ethss_stop(void) 394 { 395 int i; 396 397 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) 398 mac_sl_reset(i); 399 400 return 0; 401 } 402 403 int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int slave_port_num) 404 { 405 if (num_bytes < EMAC_MIN_ETHERNET_PKT_SIZE) 406 num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE; 407 408 return ksnav_send(&netcp_pktdma, buffer, 409 num_bytes, (slave_port_num) << 16); 410 } 411 412 /* Eth device open */ 413 static int keystone2_eth_open(struct eth_device *dev, bd_t *bis) 414 { 415 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; 416 struct phy_device *phy_dev = eth_priv->phy_dev; 417 418 debug("+ emac_open\n"); 419 420 net_rx_buffs.rx_flow = eth_priv->rx_flow; 421 422 sys_has_mdio = 423 (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0; 424 425 if (sys_has_mdio) 426 keystone2_mdio_reset(mdio_bus); 427 428 #ifdef CONFIG_SOC_K2G 429 keystone_rgmii_config(phy_dev); 430 #else 431 keystone_sgmii_config(phy_dev, eth_priv->slave_port - 1, 432 eth_priv->sgmii_link_type); 433 #endif 434 435 udelay(10000); 436 437 /* On chip switch configuration */ 438 ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE); 439 440 /* TODO: add error handling code */ 441 if (qm_init()) { 442 printf("ERROR: qm_init()\n"); 443 return -1; 444 } 445 if (ksnav_init(&netcp_pktdma, &net_rx_buffs)) { 446 qm_close(); 447 printf("ERROR: netcp_init()\n"); 448 return -1; 449 } 450 451 /* 452 * Streaming switch configuration. If not present this 453 * statement is defined to void in target.h. 454 * If present this is usually defined to a series of register writes 455 */ 456 hw_config_streaming_switch(); 457 458 if (sys_has_mdio) { 459 keystone2_mdio_reset(mdio_bus); 460 461 phy_startup(phy_dev); 462 if (phy_dev->link == 0) { 463 ksnav_close(&netcp_pktdma); 464 qm_close(); 465 return -1; 466 } 467 } 468 469 emac_gigabit_enable(dev); 470 471 ethss_start(); 472 473 debug("- emac_open\n"); 474 475 emac_open = 1; 476 477 return 0; 478 } 479 480 /* Eth device close */ 481 void keystone2_eth_close(struct eth_device *dev) 482 { 483 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; 484 struct phy_device *phy_dev = eth_priv->phy_dev; 485 486 debug("+ emac_close\n"); 487 488 if (!emac_open) 489 return; 490 491 ethss_stop(); 492 493 ksnav_close(&netcp_pktdma); 494 qm_close(); 495 phy_shutdown(phy_dev); 496 497 emac_open = 0; 498 499 debug("- emac_close\n"); 500 } 501 502 /* 503 * This function sends a single packet on the network and returns 504 * positive number (number of bytes transmitted) or negative for error 505 */ 506 static int keystone2_eth_send_packet(struct eth_device *dev, 507 void *packet, int length) 508 { 509 int ret_status = -1; 510 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; 511 struct phy_device *phy_dev = eth_priv->phy_dev; 512 513 genphy_update_link(phy_dev); 514 if (phy_dev->link == 0) 515 return -1; 516 517 if (cpmac_drv_send((u32 *)packet, length, eth_priv->slave_port) != 0) 518 return ret_status; 519 520 return length; 521 } 522 523 /* 524 * This function handles receipt of a packet from the network 525 */ 526 static int keystone2_eth_rcv_packet(struct eth_device *dev) 527 { 528 void *hd; 529 int pkt_size; 530 u32 *pkt; 531 532 hd = ksnav_recv(&netcp_pktdma, &pkt, &pkt_size); 533 if (hd == NULL) 534 return 0; 535 536 net_process_received_packet((uchar *)pkt, pkt_size); 537 538 ksnav_release_rxhd(&netcp_pktdma, hd); 539 540 return pkt_size; 541 } 542 543 #ifdef CONFIG_MCAST_TFTP 544 static int keystone2_eth_bcast_addr(struct eth_device *dev, u32 ip, u8 set) 545 { 546 return 0; 547 } 548 #endif 549 550 /* 551 * This function initializes the EMAC hardware. 552 */ 553 int keystone2_emac_initialize(struct eth_priv_t *eth_priv) 554 { 555 int res; 556 struct eth_device *dev; 557 struct phy_device *phy_dev; 558 559 dev = malloc(sizeof(struct eth_device)); 560 if (dev == NULL) 561 return -1; 562 563 memset(dev, 0, sizeof(struct eth_device)); 564 565 strcpy(dev->name, eth_priv->int_name); 566 dev->priv = eth_priv; 567 568 keystone2_eth_read_mac_addr(dev); 569 570 dev->iobase = 0; 571 dev->init = keystone2_eth_open; 572 dev->halt = keystone2_eth_close; 573 dev->send = keystone2_eth_send_packet; 574 dev->recv = keystone2_eth_rcv_packet; 575 #ifdef CONFIG_MCAST_TFTP 576 dev->mcast = keystone2_eth_bcast_addr; 577 #endif 578 579 eth_register(dev); 580 581 /* Register MDIO bus if it's not registered yet */ 582 if (!mdio_bus) { 583 mdio_bus = mdio_alloc(); 584 mdio_bus->read = keystone2_mdio_read; 585 mdio_bus->write = keystone2_mdio_write; 586 mdio_bus->reset = keystone2_mdio_reset; 587 mdio_bus->priv = (void *)EMAC_MDIO_BASE_ADDR; 588 sprintf(mdio_bus->name, "ethernet-mdio"); 589 590 res = mdio_register(mdio_bus); 591 if (res) 592 return res; 593 } 594 595 #ifndef CONFIG_SOC_K2G 596 keystone2_net_serdes_setup(); 597 #endif 598 599 /* Create phy device and bind it with driver */ 600 #ifdef CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE 601 phy_dev = phy_connect(mdio_bus, eth_priv->phy_addr, 602 dev, eth_priv->phy_if); 603 phy_config(phy_dev); 604 #else 605 phy_dev = phy_find_by_mask(mdio_bus, 1 << eth_priv->phy_addr, 606 eth_priv->phy_if); 607 phy_dev->dev = dev; 608 #endif 609 eth_priv->phy_dev = phy_dev; 610 611 return 0; 612 } 613 614 struct ks2_serdes ks2_serdes_sgmii_156p25mhz = { 615 .clk = SERDES_CLOCK_156P25M, 616 .rate = SERDES_RATE_5G, 617 .rate_mode = SERDES_QUARTER_RATE, 618 .intf = SERDES_PHY_SGMII, 619 .loopback = 0, 620 }; 621 622 #ifndef CONFIG_SOC_K2G 623 static void keystone2_net_serdes_setup(void) 624 { 625 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE, 626 &ks2_serdes_sgmii_156p25mhz, 627 CONFIG_KSNET_SERDES_LANES_PER_SGMII); 628 629 #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L) 630 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE, 631 &ks2_serdes_sgmii_156p25mhz, 632 CONFIG_KSNET_SERDES_LANES_PER_SGMII); 633 #endif 634 635 /* wait till setup */ 636 udelay(5000); 637 } 638 #endif 639