1 /* 2 * Ethernet driver for TI K2HK EVM. 3 * 4 * (C) Copyright 2012-2014 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 #include <common.h> 10 #include <command.h> 11 12 #include <net.h> 13 #include <phy.h> 14 #include <miiphy.h> 15 #include <malloc.h> 16 #include <asm/ti-common/keystone_nav.h> 17 #include <asm/ti-common/keystone_net.h> 18 #include <asm/ti-common/keystone_serdes.h> 19 20 unsigned int emac_open; 21 static struct mii_dev *mdio_bus; 22 static unsigned int sys_has_mdio = 1; 23 24 #ifdef KEYSTONE2_EMAC_GIG_ENABLE 25 #define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x) 26 #else 27 #define emac_gigabit_enable(x) /* no gigabit to enable */ 28 #endif 29 30 #define RX_BUFF_NUMS 24 31 #define RX_BUFF_LEN 1520 32 #define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN 33 34 static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16); 35 36 struct rx_buff_desc net_rx_buffs = { 37 .buff_ptr = rx_buffs, 38 .num_buffs = RX_BUFF_NUMS, 39 .buff_len = RX_BUFF_LEN, 40 .rx_flow = 22, 41 }; 42 43 static void keystone2_net_serdes_setup(void); 44 45 static int gen_get_link_speed(int phy_addr); 46 47 int keystone2_eth_read_mac_addr(struct eth_device *dev) 48 { 49 struct eth_priv_t *eth_priv; 50 u32 maca = 0; 51 u32 macb = 0; 52 53 eth_priv = (struct eth_priv_t *)dev->priv; 54 55 /* Read the e-fuse mac address */ 56 if (eth_priv->slave_port == 1) { 57 maca = __raw_readl(MAC_ID_BASE_ADDR); 58 macb = __raw_readl(MAC_ID_BASE_ADDR + 4); 59 } 60 61 dev->enetaddr[0] = (macb >> 8) & 0xff; 62 dev->enetaddr[1] = (macb >> 0) & 0xff; 63 dev->enetaddr[2] = (maca >> 24) & 0xff; 64 dev->enetaddr[3] = (maca >> 16) & 0xff; 65 dev->enetaddr[4] = (maca >> 8) & 0xff; 66 dev->enetaddr[5] = (maca >> 0) & 0xff; 67 68 return 0; 69 } 70 71 /* MDIO */ 72 73 static int keystone2_mdio_reset(struct mii_dev *bus) 74 { 75 u_int32_t clkdiv; 76 struct mdio_regs *adap_mdio = bus->priv; 77 78 clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; 79 80 writel((clkdiv & 0xffff) | MDIO_CONTROL_ENABLE | 81 MDIO_CONTROL_FAULT | MDIO_CONTROL_FAULT_ENABLE, 82 &adap_mdio->control); 83 84 while (readl(&adap_mdio->control) & MDIO_CONTROL_IDLE) 85 ; 86 87 return 0; 88 } 89 90 /** 91 * keystone2_mdio_read - read a PHY register via MDIO interface. 92 * Blocks until operation is complete. 93 */ 94 static int keystone2_mdio_read(struct mii_dev *bus, 95 int addr, int devad, int reg) 96 { 97 int tmp; 98 struct mdio_regs *adap_mdio = bus->priv; 99 100 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO) 101 ; 102 103 writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_READ | 104 ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16), 105 &adap_mdio->useraccess0); 106 107 /* Wait for command to complete */ 108 while ((tmp = readl(&adap_mdio->useraccess0)) & MDIO_USERACCESS0_GO) 109 ; 110 111 if (tmp & MDIO_USERACCESS0_ACK) 112 return tmp & 0xffff; 113 114 return -1; 115 } 116 117 /** 118 * keystone2_mdio_write - write to a PHY register via MDIO interface. 119 * Blocks until operation is complete. 120 */ 121 static int keystone2_mdio_write(struct mii_dev *bus, 122 int addr, int devad, int reg, u16 val) 123 { 124 struct mdio_regs *adap_mdio = bus->priv; 125 126 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO) 127 ; 128 129 writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_WRITE | 130 ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16) | 131 (val & 0xffff), &adap_mdio->useraccess0); 132 133 /* Wait for command to complete */ 134 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO) 135 ; 136 137 return 0; 138 } 139 140 /* PHY functions for a generic PHY */ 141 static int gen_get_link_speed(int phy_addr) 142 { 143 u_int16_t tmp; 144 145 tmp = mdio_bus->read(mdio_bus, phy_addr, 146 MDIO_DEVAD_NONE, MII_STATUS_REG); 147 if (tmp & 0x04) 148 return 0; 149 150 return -1; 151 } 152 153 static void __attribute__((unused)) 154 keystone2_eth_gigabit_enable(struct eth_device *dev) 155 { 156 u_int16_t data; 157 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; 158 159 if (sys_has_mdio) { 160 data = keystone2_mdio_read(mdio_bus, eth_priv->phy_addr, 161 MDIO_DEVAD_NONE, 0); 162 /* speed selection MSB */ 163 if (!(data & (1 << 6))) 164 return; 165 } 166 167 /* 168 * Check if link detected is giga-bit 169 * If Gigabit mode detected, enable gigbit in MAC 170 */ 171 writel(readl(DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + 172 CPGMACSL_REG_CTL) | 173 EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE, 174 DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + CPGMACSL_REG_CTL); 175 } 176 177 int keystone_sgmii_link_status(int port) 178 { 179 u32 status = 0; 180 181 status = __raw_readl(SGMII_STATUS_REG(port)); 182 183 return status & SGMII_REG_STATUS_LINK; 184 } 185 186 187 int keystone_get_link_status(struct eth_device *dev) 188 { 189 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; 190 int sgmii_link; 191 int link_state = 0; 192 #if CONFIG_GET_LINK_STATUS_ATTEMPTS > 1 193 int j; 194 195 for (j = 0; (j < CONFIG_GET_LINK_STATUS_ATTEMPTS) && (link_state == 0); 196 j++) { 197 #endif 198 sgmii_link = 199 keystone_sgmii_link_status(eth_priv->slave_port - 1); 200 201 if (sgmii_link) { 202 link_state = 1; 203 204 if (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) 205 if (gen_get_link_speed(eth_priv->phy_addr)) 206 link_state = 0; 207 } 208 #if CONFIG_GET_LINK_STATUS_ATTEMPTS > 1 209 } 210 #endif 211 return link_state; 212 } 213 214 int keystone_sgmii_config(int port, int interface) 215 { 216 unsigned int i, status, mask; 217 unsigned int mr_adv_ability, control; 218 219 switch (interface) { 220 case SGMII_LINK_MAC_MAC_AUTONEG: 221 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE | 222 SGMII_REG_MR_ADV_LINK | 223 SGMII_REG_MR_ADV_FULL_DUPLEX | 224 SGMII_REG_MR_ADV_GIG_MODE); 225 control = (SGMII_REG_CONTROL_MASTER | 226 SGMII_REG_CONTROL_AUTONEG); 227 228 break; 229 case SGMII_LINK_MAC_PHY: 230 case SGMII_LINK_MAC_PHY_FORCED: 231 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE; 232 control = SGMII_REG_CONTROL_AUTONEG; 233 234 break; 235 case SGMII_LINK_MAC_MAC_FORCED: 236 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE | 237 SGMII_REG_MR_ADV_LINK | 238 SGMII_REG_MR_ADV_FULL_DUPLEX | 239 SGMII_REG_MR_ADV_GIG_MODE); 240 control = SGMII_REG_CONTROL_MASTER; 241 242 break; 243 case SGMII_LINK_MAC_FIBER: 244 mr_adv_ability = 0x20; 245 control = SGMII_REG_CONTROL_AUTONEG; 246 247 break; 248 default: 249 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE; 250 control = SGMII_REG_CONTROL_AUTONEG; 251 } 252 253 __raw_writel(0, SGMII_CTL_REG(port)); 254 255 /* 256 * Wait for the SerDes pll to lock, 257 * but don't trap if lock is never read 258 */ 259 for (i = 0; i < 1000; i++) { 260 udelay(2000); 261 status = __raw_readl(SGMII_STATUS_REG(port)); 262 if ((status & SGMII_REG_STATUS_LOCK) != 0) 263 break; 264 } 265 266 __raw_writel(mr_adv_ability, SGMII_MRADV_REG(port)); 267 __raw_writel(control, SGMII_CTL_REG(port)); 268 269 270 mask = SGMII_REG_STATUS_LINK; 271 272 if (control & SGMII_REG_CONTROL_AUTONEG) 273 mask |= SGMII_REG_STATUS_AUTONEG; 274 275 for (i = 0; i < 1000; i++) { 276 status = __raw_readl(SGMII_STATUS_REG(port)); 277 if ((status & mask) == mask) 278 break; 279 } 280 281 return 0; 282 } 283 284 int mac_sl_reset(u32 port) 285 { 286 u32 i, v; 287 288 if (port >= DEVICE_N_GMACSL_PORTS) 289 return GMACSL_RET_INVALID_PORT; 290 291 /* Set the soft reset bit */ 292 writel(CPGMAC_REG_RESET_VAL_RESET, 293 DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET); 294 295 /* Wait for the bit to clear */ 296 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) { 297 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET); 298 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) != 299 CPGMAC_REG_RESET_VAL_RESET) 300 return GMACSL_RET_OK; 301 } 302 303 /* Timeout on the reset */ 304 return GMACSL_RET_WARN_RESET_INCOMPLETE; 305 } 306 307 int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg) 308 { 309 u32 v, i; 310 int ret = GMACSL_RET_OK; 311 312 if (port >= DEVICE_N_GMACSL_PORTS) 313 return GMACSL_RET_INVALID_PORT; 314 315 if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) { 316 cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN; 317 ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG; 318 } 319 320 /* Must wait if the device is undergoing reset */ 321 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) { 322 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET); 323 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) != 324 CPGMAC_REG_RESET_VAL_RESET) 325 break; 326 } 327 328 if (i == DEVICE_EMACSL_RESET_POLL_COUNT) 329 return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE; 330 331 writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN); 332 writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL); 333 334 return ret; 335 } 336 337 int ethss_config(u32 ctl, u32 max_pkt_size) 338 { 339 u32 i; 340 341 /* Max length register */ 342 writel(max_pkt_size, DEVICE_CPSW_BASE + CPSW_REG_MAXLEN); 343 344 /* Control register */ 345 writel(ctl, DEVICE_CPSW_BASE + CPSW_REG_CTL); 346 347 /* All statistics enabled by default */ 348 writel(CPSW_REG_VAL_STAT_ENABLE_ALL, 349 DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN); 350 351 /* Reset and enable the ALE */ 352 writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE | 353 CPSW_REG_VAL_ALE_CTL_BYPASS, 354 DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL); 355 356 /* All ports put into forward mode */ 357 for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++) 358 writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE, 359 DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i)); 360 361 return 0; 362 } 363 364 int ethss_start(void) 365 { 366 int i; 367 struct mac_sl_cfg cfg; 368 369 cfg.max_rx_len = MAX_SIZE_STREAM_BUFFER; 370 cfg.ctl = GMACSL_ENABLE | GMACSL_RX_ENABLE_EXT_CTL; 371 372 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) { 373 mac_sl_reset(i); 374 mac_sl_config(i, &cfg); 375 } 376 377 return 0; 378 } 379 380 int ethss_stop(void) 381 { 382 int i; 383 384 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) 385 mac_sl_reset(i); 386 387 return 0; 388 } 389 390 int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int slave_port_num) 391 { 392 if (num_bytes < EMAC_MIN_ETHERNET_PKT_SIZE) 393 num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE; 394 395 return ksnav_send(&netcp_pktdma, buffer, 396 num_bytes, (slave_port_num) << 16); 397 } 398 399 /* Eth device open */ 400 static int keystone2_eth_open(struct eth_device *dev, bd_t *bis) 401 { 402 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; 403 struct phy_device *phy_dev = eth_priv->phy_dev; 404 405 debug("+ emac_open\n"); 406 407 net_rx_buffs.rx_flow = eth_priv->rx_flow; 408 409 sys_has_mdio = 410 (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0; 411 412 keystone2_net_serdes_setup(); 413 414 keystone_sgmii_config(eth_priv->slave_port - 1, 415 eth_priv->sgmii_link_type); 416 417 udelay(10000); 418 419 /* On chip switch configuration */ 420 ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE); 421 422 /* TODO: add error handling code */ 423 if (qm_init()) { 424 printf("ERROR: qm_init()\n"); 425 return -1; 426 } 427 if (ksnav_init(&netcp_pktdma, &net_rx_buffs)) { 428 qm_close(); 429 printf("ERROR: netcp_init()\n"); 430 return -1; 431 } 432 433 /* 434 * Streaming switch configuration. If not present this 435 * statement is defined to void in target.h. 436 * If present this is usually defined to a series of register writes 437 */ 438 hw_config_streaming_switch(); 439 440 if (sys_has_mdio) { 441 keystone2_mdio_reset(mdio_bus); 442 443 phy_startup(phy_dev); 444 if (phy_dev->link == 0) { 445 ksnav_close(&netcp_pktdma); 446 qm_close(); 447 return -1; 448 } 449 } 450 451 emac_gigabit_enable(dev); 452 453 ethss_start(); 454 455 debug("- emac_open\n"); 456 457 emac_open = 1; 458 459 return 0; 460 } 461 462 /* Eth device close */ 463 void keystone2_eth_close(struct eth_device *dev) 464 { 465 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; 466 struct phy_device *phy_dev = eth_priv->phy_dev; 467 468 debug("+ emac_close\n"); 469 470 if (!emac_open) 471 return; 472 473 ethss_stop(); 474 475 ksnav_close(&netcp_pktdma); 476 qm_close(); 477 phy_shutdown(phy_dev); 478 479 emac_open = 0; 480 481 debug("- emac_close\n"); 482 } 483 484 /* 485 * This function sends a single packet on the network and returns 486 * positive number (number of bytes transmitted) or negative for error 487 */ 488 static int keystone2_eth_send_packet(struct eth_device *dev, 489 void *packet, int length) 490 { 491 int ret_status = -1; 492 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; 493 494 if (keystone_get_link_status(dev) == 0) 495 return -1; 496 497 if (cpmac_drv_send((u32 *)packet, length, eth_priv->slave_port) != 0) 498 return ret_status; 499 500 return length; 501 } 502 503 /* 504 * This function handles receipt of a packet from the network 505 */ 506 static int keystone2_eth_rcv_packet(struct eth_device *dev) 507 { 508 void *hd; 509 int pkt_size; 510 u32 *pkt; 511 512 hd = ksnav_recv(&netcp_pktdma, &pkt, &pkt_size); 513 if (hd == NULL) 514 return 0; 515 516 NetReceive((uchar *)pkt, pkt_size); 517 518 ksnav_release_rxhd(&netcp_pktdma, hd); 519 520 return pkt_size; 521 } 522 523 /* 524 * This function initializes the EMAC hardware. 525 */ 526 int keystone2_emac_initialize(struct eth_priv_t *eth_priv) 527 { 528 int res; 529 struct eth_device *dev; 530 struct phy_device *phy_dev; 531 532 dev = malloc(sizeof(struct eth_device)); 533 if (dev == NULL) 534 return -1; 535 536 memset(dev, 0, sizeof(struct eth_device)); 537 538 strcpy(dev->name, eth_priv->int_name); 539 dev->priv = eth_priv; 540 541 keystone2_eth_read_mac_addr(dev); 542 543 dev->iobase = 0; 544 dev->init = keystone2_eth_open; 545 dev->halt = keystone2_eth_close; 546 dev->send = keystone2_eth_send_packet; 547 dev->recv = keystone2_eth_rcv_packet; 548 549 eth_register(dev); 550 551 /* Register MDIO bus if it's not registered yet */ 552 if (!mdio_bus) { 553 mdio_bus = mdio_alloc(); 554 mdio_bus->read = keystone2_mdio_read; 555 mdio_bus->write = keystone2_mdio_write; 556 mdio_bus->reset = keystone2_mdio_reset; 557 mdio_bus->priv = (void *)EMAC_MDIO_BASE_ADDR; 558 sprintf(mdio_bus->name, "ethernet-mdio"); 559 560 res = mdio_register(mdio_bus); 561 if (res) 562 return res; 563 } 564 565 /* Create phy device and bind it with driver */ 566 #ifdef CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE 567 phy_dev = phy_connect(mdio_bus, eth_priv->phy_addr, 568 dev, PHY_INTERFACE_MODE_SGMII); 569 phy_config(phy_dev); 570 #else 571 phy_dev = phy_find_by_mask(mdio_bus, 1 << eth_priv->phy_addr, 572 PHY_INTERFACE_MODE_SGMII); 573 phy_dev->dev = dev; 574 #endif 575 eth_priv->phy_dev = phy_dev; 576 577 return 0; 578 } 579 580 struct ks2_serdes ks2_serdes_sgmii_156p25mhz = { 581 .clk = SERDES_CLOCK_156P25M, 582 .rate = SERDES_RATE_5G, 583 .rate_mode = SERDES_QUARTER_RATE, 584 .intf = SERDES_PHY_SGMII, 585 .loopback = 0, 586 }; 587 588 static void keystone2_net_serdes_setup(void) 589 { 590 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE, 591 &ks2_serdes_sgmii_156p25mhz, 592 CONFIG_KSNET_SERDES_LANES_PER_SGMII); 593 594 /* wait till setup */ 595 udelay(5000); 596 } 597