1 /* 2 * Ethernet driver for TI K2HK EVM. 3 * 4 * (C) Copyright 2012-2014 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 #include <common.h> 10 #include <command.h> 11 12 #include <net.h> 13 #include <miiphy.h> 14 #include <malloc.h> 15 #include <asm/arch/emac_defs.h> 16 #include <asm/arch/psc_defs.h> 17 #include <asm/arch/keystone_nav.h> 18 19 unsigned int emac_dbg; 20 21 unsigned int emac_open; 22 static unsigned int sys_has_mdio = 1; 23 24 #ifdef KEYSTONE2_EMAC_GIG_ENABLE 25 #define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x) 26 #else 27 #define emac_gigabit_enable(x) /* no gigabit to enable */ 28 #endif 29 30 #define RX_BUFF_NUMS 24 31 #define RX_BUFF_LEN 1520 32 #define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN 33 34 static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16); 35 36 struct rx_buff_desc net_rx_buffs = { 37 .buff_ptr = rx_buffs, 38 .num_buffs = RX_BUFF_NUMS, 39 .buff_len = RX_BUFF_LEN, 40 .rx_flow = 22, 41 }; 42 43 static void keystone2_eth_mdio_enable(void); 44 45 static int gen_get_link_speed(int phy_addr); 46 47 /* EMAC Addresses */ 48 static volatile struct emac_regs *adap_emac = 49 (struct emac_regs *)EMAC_EMACSL_BASE_ADDR; 50 static volatile struct mdio_regs *adap_mdio = 51 (struct mdio_regs *)EMAC_MDIO_BASE_ADDR; 52 53 int keystone2_eth_read_mac_addr(struct eth_device *dev) 54 { 55 struct eth_priv_t *eth_priv; 56 u32 maca = 0; 57 u32 macb = 0; 58 59 eth_priv = (struct eth_priv_t *)dev->priv; 60 61 /* Read the e-fuse mac address */ 62 if (eth_priv->slave_port == 1) { 63 maca = __raw_readl(MAC_ID_BASE_ADDR); 64 macb = __raw_readl(MAC_ID_BASE_ADDR + 4); 65 } 66 67 dev->enetaddr[0] = (macb >> 8) & 0xff; 68 dev->enetaddr[1] = (macb >> 0) & 0xff; 69 dev->enetaddr[2] = (maca >> 24) & 0xff; 70 dev->enetaddr[3] = (maca >> 16) & 0xff; 71 dev->enetaddr[4] = (maca >> 8) & 0xff; 72 dev->enetaddr[5] = (maca >> 0) & 0xff; 73 74 return 0; 75 } 76 77 static void keystone2_eth_mdio_enable(void) 78 { 79 u_int32_t clkdiv; 80 81 clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; 82 83 writel((clkdiv & 0xffff) | 84 MDIO_CONTROL_ENABLE | 85 MDIO_CONTROL_FAULT | 86 MDIO_CONTROL_FAULT_ENABLE, 87 &adap_mdio->control); 88 89 while (readl(&adap_mdio->control) & MDIO_CONTROL_IDLE) 90 ; 91 } 92 93 /* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */ 94 int keystone2_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data) 95 { 96 int tmp; 97 98 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO) 99 ; 100 101 writel(MDIO_USERACCESS0_GO | 102 MDIO_USERACCESS0_WRITE_READ | 103 ((reg_num & 0x1f) << 21) | 104 ((phy_addr & 0x1f) << 16), 105 &adap_mdio->useraccess0); 106 107 /* Wait for command to complete */ 108 while ((tmp = readl(&adap_mdio->useraccess0)) & MDIO_USERACCESS0_GO) 109 ; 110 111 if (tmp & MDIO_USERACCESS0_ACK) { 112 *data = tmp & 0xffff; 113 return 0; 114 } 115 116 *data = -1; 117 return -1; 118 } 119 120 /* 121 * Write to a PHY register via MDIO inteface. 122 * Blocks until operation is complete. 123 */ 124 int keystone2_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data) 125 { 126 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO) 127 ; 128 129 writel(MDIO_USERACCESS0_GO | 130 MDIO_USERACCESS0_WRITE_WRITE | 131 ((reg_num & 0x1f) << 21) | 132 ((phy_addr & 0x1f) << 16) | 133 (data & 0xffff), 134 &adap_mdio->useraccess0); 135 136 /* Wait for command to complete */ 137 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO) 138 ; 139 140 return 0; 141 } 142 143 /* PHY functions for a generic PHY */ 144 static int gen_get_link_speed(int phy_addr) 145 { 146 u_int16_t tmp; 147 148 if ((!keystone2_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp)) && 149 (tmp & 0x04)) { 150 return 0; 151 } 152 153 return -1; 154 } 155 156 static void __attribute__((unused)) 157 keystone2_eth_gigabit_enable(struct eth_device *dev) 158 { 159 u_int16_t data; 160 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; 161 162 if (sys_has_mdio) { 163 if (keystone2_eth_phy_read(eth_priv->phy_addr, 0, &data) || 164 !(data & (1 << 6))) /* speed selection MSB */ 165 return; 166 } 167 168 /* 169 * Check if link detected is giga-bit 170 * If Gigabit mode detected, enable gigbit in MAC 171 */ 172 writel(readl(&(adap_emac[eth_priv->slave_port - 1].maccontrol)) | 173 EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE, 174 &(adap_emac[eth_priv->slave_port - 1].maccontrol)) 175 ; 176 } 177 178 int keystone_sgmii_link_status(int port) 179 { 180 u32 status = 0; 181 182 status = __raw_readl(SGMII_STATUS_REG(port)); 183 184 return status & SGMII_REG_STATUS_LINK; 185 } 186 187 188 int keystone_get_link_status(struct eth_device *dev) 189 { 190 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; 191 int sgmii_link; 192 int link_state = 0; 193 #if CONFIG_GET_LINK_STATUS_ATTEMPTS > 1 194 int j; 195 196 for (j = 0; (j < CONFIG_GET_LINK_STATUS_ATTEMPTS) && (link_state == 0); 197 j++) { 198 #endif 199 sgmii_link = 200 keystone_sgmii_link_status(eth_priv->slave_port - 1); 201 202 if (sgmii_link) { 203 link_state = 1; 204 205 if (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) 206 if (gen_get_link_speed(eth_priv->phy_addr)) 207 link_state = 0; 208 } 209 #if CONFIG_GET_LINK_STATUS_ATTEMPTS > 1 210 } 211 #endif 212 return link_state; 213 } 214 215 int keystone_sgmii_config(int port, int interface) 216 { 217 unsigned int i, status, mask; 218 unsigned int mr_adv_ability, control; 219 220 switch (interface) { 221 case SGMII_LINK_MAC_MAC_AUTONEG: 222 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE | 223 SGMII_REG_MR_ADV_LINK | 224 SGMII_REG_MR_ADV_FULL_DUPLEX | 225 SGMII_REG_MR_ADV_GIG_MODE); 226 control = (SGMII_REG_CONTROL_MASTER | 227 SGMII_REG_CONTROL_AUTONEG); 228 229 break; 230 case SGMII_LINK_MAC_PHY: 231 case SGMII_LINK_MAC_PHY_FORCED: 232 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE; 233 control = SGMII_REG_CONTROL_AUTONEG; 234 235 break; 236 case SGMII_LINK_MAC_MAC_FORCED: 237 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE | 238 SGMII_REG_MR_ADV_LINK | 239 SGMII_REG_MR_ADV_FULL_DUPLEX | 240 SGMII_REG_MR_ADV_GIG_MODE); 241 control = SGMII_REG_CONTROL_MASTER; 242 243 break; 244 case SGMII_LINK_MAC_FIBER: 245 mr_adv_ability = 0x20; 246 control = SGMII_REG_CONTROL_AUTONEG; 247 248 break; 249 default: 250 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE; 251 control = SGMII_REG_CONTROL_AUTONEG; 252 } 253 254 __raw_writel(0, SGMII_CTL_REG(port)); 255 256 /* 257 * Wait for the SerDes pll to lock, 258 * but don't trap if lock is never read 259 */ 260 for (i = 0; i < 1000; i++) { 261 udelay(2000); 262 status = __raw_readl(SGMII_STATUS_REG(port)); 263 if ((status & SGMII_REG_STATUS_LOCK) != 0) 264 break; 265 } 266 267 __raw_writel(mr_adv_ability, SGMII_MRADV_REG(port)); 268 __raw_writel(control, SGMII_CTL_REG(port)); 269 270 271 mask = SGMII_REG_STATUS_LINK; 272 273 if (control & SGMII_REG_CONTROL_AUTONEG) 274 mask |= SGMII_REG_STATUS_AUTONEG; 275 276 for (i = 0; i < 1000; i++) { 277 status = __raw_readl(SGMII_STATUS_REG(port)); 278 if ((status & mask) == mask) 279 break; 280 } 281 282 return 0; 283 } 284 285 int mac_sl_reset(u32 port) 286 { 287 u32 i, v; 288 289 if (port >= DEVICE_N_GMACSL_PORTS) 290 return GMACSL_RET_INVALID_PORT; 291 292 /* Set the soft reset bit */ 293 DEVICE_REG32_W(DEVICE_EMACSL_BASE(port) + 294 CPGMACSL_REG_RESET, CPGMAC_REG_RESET_VAL_RESET); 295 296 /* Wait for the bit to clear */ 297 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) { 298 v = DEVICE_REG32_R(DEVICE_EMACSL_BASE(port) + 299 CPGMACSL_REG_RESET); 300 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) != 301 CPGMAC_REG_RESET_VAL_RESET) 302 return GMACSL_RET_OK; 303 } 304 305 /* Timeout on the reset */ 306 return GMACSL_RET_WARN_RESET_INCOMPLETE; 307 } 308 309 int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg) 310 { 311 u32 v, i; 312 int ret = GMACSL_RET_OK; 313 314 if (port >= DEVICE_N_GMACSL_PORTS) 315 return GMACSL_RET_INVALID_PORT; 316 317 if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) { 318 cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN; 319 ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG; 320 } 321 322 /* Must wait if the device is undergoing reset */ 323 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) { 324 v = DEVICE_REG32_R(DEVICE_EMACSL_BASE(port) + 325 CPGMACSL_REG_RESET); 326 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) != 327 CPGMAC_REG_RESET_VAL_RESET) 328 break; 329 } 330 331 if (i == DEVICE_EMACSL_RESET_POLL_COUNT) 332 return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE; 333 334 DEVICE_REG32_W(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN, 335 cfg->max_rx_len); 336 337 DEVICE_REG32_W(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL, 338 cfg->ctl); 339 340 return ret; 341 } 342 343 int ethss_config(u32 ctl, u32 max_pkt_size) 344 { 345 u32 i; 346 347 /* Max length register */ 348 DEVICE_REG32_W(DEVICE_CPSW_BASE + CPSW_REG_MAXLEN, max_pkt_size); 349 350 /* Control register */ 351 DEVICE_REG32_W(DEVICE_CPSW_BASE + CPSW_REG_CTL, ctl); 352 353 /* All statistics enabled by default */ 354 DEVICE_REG32_W(DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN, 355 CPSW_REG_VAL_STAT_ENABLE_ALL); 356 357 /* Reset and enable the ALE */ 358 DEVICE_REG32_W(DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL, 359 CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE | 360 CPSW_REG_VAL_ALE_CTL_BYPASS); 361 362 /* All ports put into forward mode */ 363 for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++) 364 DEVICE_REG32_W(DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i), 365 CPSW_REG_VAL_PORTCTL_FORWARD_MODE); 366 367 return 0; 368 } 369 370 int ethss_start(void) 371 { 372 int i; 373 struct mac_sl_cfg cfg; 374 375 cfg.max_rx_len = MAX_SIZE_STREAM_BUFFER; 376 cfg.ctl = GMACSL_ENABLE | GMACSL_RX_ENABLE_EXT_CTL; 377 378 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) { 379 mac_sl_reset(i); 380 mac_sl_config(i, &cfg); 381 } 382 383 return 0; 384 } 385 386 int ethss_stop(void) 387 { 388 int i; 389 390 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) 391 mac_sl_reset(i); 392 393 return 0; 394 } 395 396 int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int slave_port_num) 397 { 398 if (num_bytes < EMAC_MIN_ETHERNET_PKT_SIZE) 399 num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE; 400 401 return netcp_send(buffer, num_bytes, (slave_port_num) << 16); 402 } 403 404 /* Eth device open */ 405 static int keystone2_eth_open(struct eth_device *dev, bd_t *bis) 406 { 407 u_int32_t clkdiv; 408 int link; 409 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; 410 411 debug("+ emac_open\n"); 412 413 net_rx_buffs.rx_flow = eth_priv->rx_flow; 414 415 sys_has_mdio = 416 (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0; 417 418 psc_enable_module(KS2_LPSC_PA); 419 psc_enable_module(KS2_LPSC_CPGMAC); 420 421 sgmii_serdes_setup_156p25mhz(); 422 423 if (sys_has_mdio) 424 keystone2_eth_mdio_enable(); 425 426 keystone_sgmii_config(eth_priv->slave_port - 1, 427 eth_priv->sgmii_link_type); 428 429 udelay(10000); 430 431 /* On chip switch configuration */ 432 ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE); 433 434 /* TODO: add error handling code */ 435 if (qm_init()) { 436 printf("ERROR: qm_init()\n"); 437 return -1; 438 } 439 if (netcp_init(&net_rx_buffs)) { 440 qm_close(); 441 printf("ERROR: netcp_init()\n"); 442 return -1; 443 } 444 445 /* 446 * Streaming switch configuration. If not present this 447 * statement is defined to void in target.h. 448 * If present this is usually defined to a series of register writes 449 */ 450 hw_config_streaming_switch(); 451 452 if (sys_has_mdio) { 453 /* Init MDIO & get link state */ 454 clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; 455 writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | 456 MDIO_CONTROL_FAULT, &adap_mdio->control) 457 ; 458 459 /* We need to wait for MDIO to start */ 460 udelay(1000); 461 462 link = keystone_get_link_status(dev); 463 if (link == 0) { 464 netcp_close(); 465 qm_close(); 466 return -1; 467 } 468 } 469 470 emac_gigabit_enable(dev); 471 472 ethss_start(); 473 474 debug("- emac_open\n"); 475 476 emac_open = 1; 477 478 return 0; 479 } 480 481 /* Eth device close */ 482 void keystone2_eth_close(struct eth_device *dev) 483 { 484 debug("+ emac_close\n"); 485 486 if (!emac_open) 487 return; 488 489 ethss_stop(); 490 491 netcp_close(); 492 qm_close(); 493 494 emac_open = 0; 495 496 debug("- emac_close\n"); 497 } 498 499 static int tx_send_loop; 500 501 /* 502 * This function sends a single packet on the network and returns 503 * positive number (number of bytes transmitted) or negative for error 504 */ 505 static int keystone2_eth_send_packet(struct eth_device *dev, 506 void *packet, int length) 507 { 508 int ret_status = -1; 509 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; 510 511 tx_send_loop = 0; 512 513 if (keystone_get_link_status(dev) == 0) 514 return -1; 515 516 emac_gigabit_enable(dev); 517 518 if (cpmac_drv_send((u32 *)packet, length, eth_priv->slave_port) != 0) 519 return ret_status; 520 521 if (keystone_get_link_status(dev) == 0) 522 return -1; 523 524 emac_gigabit_enable(dev); 525 526 return length; 527 } 528 529 /* 530 * This function handles receipt of a packet from the network 531 */ 532 static int keystone2_eth_rcv_packet(struct eth_device *dev) 533 { 534 void *hd; 535 int pkt_size; 536 u32 *pkt; 537 538 hd = netcp_recv(&pkt, &pkt_size); 539 if (hd == NULL) 540 return 0; 541 542 NetReceive((uchar *)pkt, pkt_size); 543 544 netcp_release_rxhd(hd); 545 546 return pkt_size; 547 } 548 549 /* 550 * This function initializes the EMAC hardware. 551 */ 552 int keystone2_emac_initialize(struct eth_priv_t *eth_priv) 553 { 554 struct eth_device *dev; 555 556 dev = malloc(sizeof(struct eth_device)); 557 if (dev == NULL) 558 return -1; 559 560 memset(dev, 0, sizeof(struct eth_device)); 561 562 strcpy(dev->name, eth_priv->int_name); 563 dev->priv = eth_priv; 564 565 keystone2_eth_read_mac_addr(dev); 566 567 dev->iobase = 0; 568 dev->init = keystone2_eth_open; 569 dev->halt = keystone2_eth_close; 570 dev->send = keystone2_eth_send_packet; 571 dev->recv = keystone2_eth_rcv_packet; 572 573 eth_register(dev); 574 575 return 0; 576 } 577 578 void sgmii_serdes_setup_156p25mhz(void) 579 { 580 unsigned int cnt; 581 582 /* 583 * configure Serializer/Deserializer (SerDes) hardware. SerDes IP 584 * hardware vendor published only register addresses and their values 585 * to be used for configuring SerDes. So had to use hardcoded values 586 * below. 587 */ 588 clrsetbits_le32(0x0232a000, 0xffff0000, 0x00800000); 589 clrsetbits_le32(0x0232a014, 0x0000ffff, 0x00008282); 590 clrsetbits_le32(0x0232a060, 0x00ffffff, 0x00142438); 591 clrsetbits_le32(0x0232a064, 0x00ffff00, 0x00c3c700); 592 clrsetbits_le32(0x0232a078, 0x0000ff00, 0x0000c000); 593 594 clrsetbits_le32(0x0232a204, 0xff0000ff, 0x38000080); 595 clrsetbits_le32(0x0232a208, 0x000000ff, 0x00000000); 596 clrsetbits_le32(0x0232a20c, 0xff000000, 0x02000000); 597 clrsetbits_le32(0x0232a210, 0xff000000, 0x1b000000); 598 clrsetbits_le32(0x0232a214, 0x0000ffff, 0x00006fb8); 599 clrsetbits_le32(0x0232a218, 0xffff00ff, 0x758000e4); 600 clrsetbits_le32(0x0232a2ac, 0x0000ff00, 0x00004400); 601 clrsetbits_le32(0x0232a22c, 0x00ffff00, 0x00200800); 602 clrsetbits_le32(0x0232a280, 0x00ff00ff, 0x00820082); 603 clrsetbits_le32(0x0232a284, 0xffffffff, 0x1d0f0385); 604 605 clrsetbits_le32(0x0232a404, 0xff0000ff, 0x38000080); 606 clrsetbits_le32(0x0232a408, 0x000000ff, 0x00000000); 607 clrsetbits_le32(0x0232a40c, 0xff000000, 0x02000000); 608 clrsetbits_le32(0x0232a410, 0xff000000, 0x1b000000); 609 clrsetbits_le32(0x0232a414, 0x0000ffff, 0x00006fb8); 610 clrsetbits_le32(0x0232a418, 0xffff00ff, 0x758000e4); 611 clrsetbits_le32(0x0232a4ac, 0x0000ff00, 0x00004400); 612 clrsetbits_le32(0x0232a42c, 0x00ffff00, 0x00200800); 613 clrsetbits_le32(0x0232a480, 0x00ff00ff, 0x00820082); 614 clrsetbits_le32(0x0232a484, 0xffffffff, 0x1d0f0385); 615 616 clrsetbits_le32(0x0232a604, 0xff0000ff, 0x38000080); 617 clrsetbits_le32(0x0232a608, 0x000000ff, 0x00000000); 618 clrsetbits_le32(0x0232a60c, 0xff000000, 0x02000000); 619 clrsetbits_le32(0x0232a610, 0xff000000, 0x1b000000); 620 clrsetbits_le32(0x0232a614, 0x0000ffff, 0x00006fb8); 621 clrsetbits_le32(0x0232a618, 0xffff00ff, 0x758000e4); 622 clrsetbits_le32(0x0232a6ac, 0x0000ff00, 0x00004400); 623 clrsetbits_le32(0x0232a62c, 0x00ffff00, 0x00200800); 624 clrsetbits_le32(0x0232a680, 0x00ff00ff, 0x00820082); 625 clrsetbits_le32(0x0232a684, 0xffffffff, 0x1d0f0385); 626 627 clrsetbits_le32(0x0232a804, 0xff0000ff, 0x38000080); 628 clrsetbits_le32(0x0232a808, 0x000000ff, 0x00000000); 629 clrsetbits_le32(0x0232a80c, 0xff000000, 0x02000000); 630 clrsetbits_le32(0x0232a810, 0xff000000, 0x1b000000); 631 clrsetbits_le32(0x0232a814, 0x0000ffff, 0x00006fb8); 632 clrsetbits_le32(0x0232a818, 0xffff00ff, 0x758000e4); 633 clrsetbits_le32(0x0232a8ac, 0x0000ff00, 0x00004400); 634 clrsetbits_le32(0x0232a82c, 0x00ffff00, 0x00200800); 635 clrsetbits_le32(0x0232a880, 0x00ff00ff, 0x00820082); 636 clrsetbits_le32(0x0232a884, 0xffffffff, 0x1d0f0385); 637 638 clrsetbits_le32(0x0232aa00, 0x0000ff00, 0x00000800); 639 clrsetbits_le32(0x0232aa08, 0xffff0000, 0x38a20000); 640 clrsetbits_le32(0x0232aa30, 0x00ffff00, 0x008a8a00); 641 clrsetbits_le32(0x0232aa84, 0x0000ff00, 0x00000600); 642 clrsetbits_le32(0x0232aa94, 0xff000000, 0x10000000); 643 clrsetbits_le32(0x0232aaa0, 0xff000000, 0x81000000); 644 clrsetbits_le32(0x0232aabc, 0xff000000, 0xff000000); 645 clrsetbits_le32(0x0232aac0, 0x000000ff, 0x0000008b); 646 clrsetbits_le32(0x0232ab08, 0xffff0000, 0x583f0000); 647 clrsetbits_le32(0x0232ab0c, 0x000000ff, 0x0000004e); 648 clrsetbits_le32(0x0232a000, 0x000000ff, 0x00000003); 649 clrsetbits_le32(0x0232aa00, 0x000000ff, 0x0000005f); 650 651 clrsetbits_le32(0x0232aa48, 0x00ffff00, 0x00fd8c00); 652 clrsetbits_le32(0x0232aa54, 0x00ffffff, 0x002fec72); 653 clrsetbits_le32(0x0232aa58, 0xffffff00, 0x00f92100); 654 clrsetbits_le32(0x0232aa5c, 0xffffffff, 0x00040060); 655 clrsetbits_le32(0x0232aa60, 0xffffffff, 0x00008000); 656 clrsetbits_le32(0x0232aa64, 0xffffffff, 0x0c581220); 657 clrsetbits_le32(0x0232aa68, 0xffffffff, 0xe13b0602); 658 clrsetbits_le32(0x0232aa6c, 0xffffffff, 0xb8074cc1); 659 clrsetbits_le32(0x0232aa70, 0xffffffff, 0x3f02e989); 660 clrsetbits_le32(0x0232aa74, 0x000000ff, 0x00000001); 661 clrsetbits_le32(0x0232ab20, 0x00ff0000, 0x00370000); 662 clrsetbits_le32(0x0232ab1c, 0xff000000, 0x37000000); 663 clrsetbits_le32(0x0232ab20, 0x000000ff, 0x0000005d); 664 665 /*Bring SerDes out of Reset if SerDes is Shutdown & is in Reset Mode*/ 666 clrbits_le32(0x0232a010, 1 << 28); 667 668 /* Enable TX and RX via the LANExCTL_STS 0x0000 + x*4 */ 669 clrbits_le32(0x0232a228, 1 << 29); 670 writel(0xF800F8C0, 0x0232bfe0); 671 clrbits_le32(0x0232a428, 1 << 29); 672 writel(0xF800F8C0, 0x0232bfe4); 673 clrbits_le32(0x0232a628, 1 << 29); 674 writel(0xF800F8C0, 0x0232bfe8); 675 clrbits_le32(0x0232a828, 1 << 29); 676 writel(0xF800F8C0, 0x0232bfec); 677 678 /*Enable pll via the pll_ctrl 0x0014*/ 679 writel(0xe0000000, 0x0232bff4) 680 ; 681 682 /*Waiting for SGMII Serdes PLL lock.*/ 683 for (cnt = 10000; cnt > 0 && ((readl(0x02090114) & 0x10) == 0); cnt--) 684 ; 685 686 for (cnt = 10000; cnt > 0 && ((readl(0x02090214) & 0x10) == 0); cnt--) 687 ; 688 689 for (cnt = 10000; cnt > 0 && ((readl(0x02090414) & 0x10) == 0); cnt--) 690 ; 691 692 for (cnt = 10000; cnt > 0 && ((readl(0x02090514) & 0x10) == 0); cnt--) 693 ; 694 695 udelay(45000); 696 } 697 698 void sgmii_serdes_shutdown(void) 699 { 700 /* 701 * shutdown SerDes hardware. SerDes hardware vendor published only 702 * register addresses and their values. So had to use hardcoded 703 * values below. 704 */ 705 clrbits_le32(0x0232bfe0, 3 << 29 | 3 << 13); 706 setbits_le32(0x02320228, 1 << 29); 707 clrbits_le32(0x0232bfe4, 3 << 29 | 3 << 13); 708 setbits_le32(0x02320428, 1 << 29); 709 clrbits_le32(0x0232bfe8, 3 << 29 | 3 << 13); 710 setbits_le32(0x02320628, 1 << 29); 711 clrbits_le32(0x0232bfec, 3 << 29 | 3 << 13); 712 setbits_le32(0x02320828, 1 << 29); 713 714 clrbits_le32(0x02320034, 3 << 29); 715 setbits_le32(0x02320010, 1 << 28); 716 } 717