1 /* 2 * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Rockchip GMAC ethernet IP driver for U-Boot 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <clk.h> 12 #include <phy.h> 13 #include <reset.h> 14 #include <syscon.h> 15 #include <asm/io.h> 16 #include <asm/arch/periph.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/hardware.h> 19 #ifdef CONFIG_DWC_ETH_QOS 20 #include <asm/arch/grf_rk3568.h> 21 #include <asm/arch/grf_rv1126.h> 22 #include "dwc_eth_qos.h" 23 #else 24 #include <asm/arch/grf_px30.h> 25 #include <asm/arch/grf_rk1808.h> 26 #include <asm/arch/grf_rk322x.h> 27 #include <asm/arch/grf_rk3288.h> 28 #include <asm/arch/grf_rk3308.h> 29 #include <asm/arch/grf_rk3328.h> 30 #include <asm/arch/grf_rk3368.h> 31 #include <asm/arch/grf_rk3399.h> 32 #include <asm/arch/grf_rv1108.h> 33 #include "designware.h" 34 #include <dt-bindings/clock/rk3288-cru.h> 35 #endif 36 #include <dm/pinctrl.h> 37 #include <dm/of_access.h> 38 39 DECLARE_GLOBAL_DATA_PTR; 40 41 struct rockchip_eth_dev { 42 #ifdef CONFIG_DWC_ETH_QOS 43 struct eqos_priv eqos; 44 #else 45 struct dw_eth_dev dw; 46 #endif 47 int phy_interface; 48 }; 49 50 /* 51 * Platform data for the gmac 52 * 53 * dw_eth_pdata: Required platform data for designware driver (must be first) 54 */ 55 struct gmac_rockchip_platdata { 56 #ifndef CONFIG_DWC_ETH_QOS 57 struct dw_eth_pdata dw_eth_pdata; 58 #else 59 struct eth_pdata eth_pdata; 60 #endif 61 struct reset_ctl phy_reset; 62 bool integrated_phy; 63 bool clock_input; 64 int phy_interface; 65 int tx_delay; 66 int rx_delay; 67 int bus_id; 68 }; 69 70 struct rk_gmac_ops { 71 #ifdef CONFIG_DWC_ETH_QOS 72 const struct eqos_config config; 73 #endif 74 int (*fix_mac_speed)(struct gmac_rockchip_platdata *pdata, 75 struct rockchip_eth_dev *dev); 76 void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata); 77 void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata); 78 void (*integrated_phy_powerup)(struct gmac_rockchip_platdata *pdata); 79 }; 80 81 #ifdef CONFIG_DWC_ETH_QOS 82 static const struct eqos_config eqos_rockchip_config = { 83 .reg_access_always_ok = false, 84 .mdio_wait = 10000, 85 .swr_wait = 200, 86 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED, 87 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_100_150, 88 .ops = &eqos_rockchip_ops, 89 }; 90 #endif 91 92 void gmac_set_rgmii(struct udevice *dev, u32 tx_delay, u32 rx_delay) 93 { 94 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 95 struct rk_gmac_ops *ops = 96 (struct rk_gmac_ops *)dev_get_driver_data(dev); 97 98 pdata->tx_delay = tx_delay; 99 pdata->rx_delay = rx_delay; 100 101 ops->set_to_rgmii(pdata); 102 } 103 104 static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) 105 { 106 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 107 struct ofnode_phandle_args args; 108 const char *string; 109 int ret; 110 111 string = dev_read_string(dev, "clock_in_out"); 112 if (!strcmp(string, "input")) 113 pdata->clock_input = true; 114 else 115 pdata->clock_input = false; 116 117 /* If phy-handle property is passed from DT, use it as the PHY */ 118 ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &args); 119 if (ret) { 120 debug("Cannot get phy phandle: ret=%d\n", ret); 121 pdata->integrated_phy = dev_read_bool(dev, "phy-is-integrated"); 122 } else { 123 debug("Found phy-handle subnode\n"); 124 pdata->integrated_phy = ofnode_read_bool(args.node, 125 "phy-is-integrated"); 126 } 127 128 if (pdata->integrated_phy) { 129 ret = reset_get_by_name(dev, "mac-phy", &pdata->phy_reset); 130 if (ret) { 131 debug("No PHY reset control found: ret=%d\n", ret); 132 return ret; 133 } 134 } 135 136 /* Check the new naming-style first... */ 137 pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT); 138 pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT); 139 140 /* ... and fall back to the old naming style or default, if necessary */ 141 if (pdata->tx_delay == -ENOENT) 142 pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30); 143 if (pdata->rx_delay == -ENOENT) 144 pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10); 145 146 #ifdef CONFIG_DWC_ETH_QOS 147 return 0; 148 #else 149 return designware_eth_ofdata_to_platdata(dev); 150 #endif 151 } 152 153 #ifndef CONFIG_DWC_ETH_QOS 154 static int px30_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 155 struct rockchip_eth_dev *dev) 156 { 157 struct dw_eth_dev *priv = &dev->dw; 158 struct px30_grf *grf; 159 struct clk clk_speed; 160 int speed, ret; 161 enum { 162 PX30_GMAC_SPEED_SHIFT = 0x2, 163 PX30_GMAC_SPEED_MASK = BIT(2), 164 PX30_GMAC_SPEED_10M = 0, 165 PX30_GMAC_SPEED_100M = BIT(2), 166 }; 167 168 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 169 &clk_speed); 170 if (ret) 171 return ret; 172 173 switch (priv->phydev->speed) { 174 case 10: 175 speed = PX30_GMAC_SPEED_10M; 176 ret = clk_set_rate(&clk_speed, 2500000); 177 if (ret) 178 return ret; 179 break; 180 case 100: 181 speed = PX30_GMAC_SPEED_100M; 182 ret = clk_set_rate(&clk_speed, 25000000); 183 if (ret) 184 return ret; 185 break; 186 default: 187 debug("Unknown phy speed: %d\n", priv->phydev->speed); 188 return -EINVAL; 189 } 190 191 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 192 rk_clrsetreg(&grf->mac_con1, PX30_GMAC_SPEED_MASK, speed); 193 194 return 0; 195 } 196 197 static int rk1808_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 198 struct rockchip_eth_dev *dev) 199 { 200 struct dw_eth_dev *priv = &dev->dw; 201 struct clk clk_speed; 202 int ret; 203 204 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 205 &clk_speed); 206 if (ret) 207 return ret; 208 209 switch (priv->phydev->speed) { 210 case 10: 211 ret = clk_set_rate(&clk_speed, 2500000); 212 if (ret) 213 return ret; 214 break; 215 case 100: 216 ret = clk_set_rate(&clk_speed, 25000000); 217 if (ret) 218 return ret; 219 break; 220 case 1000: 221 ret = clk_set_rate(&clk_speed, 125000000); 222 if (ret) 223 return ret; 224 break; 225 default: 226 debug("Unknown phy speed: %d\n", priv->phydev->speed); 227 return -EINVAL; 228 } 229 230 return 0; 231 } 232 233 static int rk3228_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 234 struct rockchip_eth_dev *dev) 235 { 236 struct dw_eth_dev *priv = &dev->dw; 237 struct rk322x_grf *grf; 238 int clk; 239 enum { 240 RK3228_GMAC_CLK_SEL_SHIFT = 8, 241 RK3228_GMAC_CLK_SEL_MASK = GENMASK(9, 8), 242 RK3228_GMAC_CLK_SEL_125M = 0 << 8, 243 RK3228_GMAC_CLK_SEL_25M = 3 << 8, 244 RK3228_GMAC_CLK_SEL_2_5M = 2 << 8, 245 246 RK3228_GMAC_RMII_CLK_MASK = BIT(7), 247 RK3228_GMAC_RMII_CLK_2_5M = 0, 248 RK3228_GMAC_RMII_CLK_25M = BIT(7), 249 250 RK3228_GMAC_RMII_SPEED_MASK = BIT(2), 251 RK3228_GMAC_RMII_SPEED_10 = 0, 252 RK3228_GMAC_RMII_SPEED_100 = BIT(2), 253 }; 254 255 switch (priv->phydev->speed) { 256 case 10: 257 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 258 (RK3228_GMAC_RMII_CLK_2_5M | RK3228_GMAC_RMII_SPEED_10) : 259 RK3228_GMAC_CLK_SEL_2_5M; 260 break; 261 case 100: 262 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 263 (RK3228_GMAC_RMII_CLK_25M | RK3228_GMAC_RMII_SPEED_100) : 264 RK3228_GMAC_CLK_SEL_25M; 265 break; 266 case 1000: 267 clk = RK3228_GMAC_CLK_SEL_125M; 268 break; 269 default: 270 debug("Unknown phy speed: %d\n", priv->phydev->speed); 271 return -EINVAL; 272 } 273 274 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 275 rk_clrsetreg(&grf->mac_con[1], 276 RK3228_GMAC_CLK_SEL_MASK | 277 RK3228_GMAC_RMII_CLK_MASK | 278 RK3228_GMAC_RMII_SPEED_MASK, 279 clk); 280 281 return 0; 282 } 283 284 static int rk3288_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 285 struct rockchip_eth_dev *dev) 286 { 287 struct dw_eth_dev *priv = &dev->dw; 288 struct rk3288_grf *grf; 289 int clk; 290 291 switch (priv->phydev->speed) { 292 case 10: 293 clk = RK3288_GMAC_CLK_SEL_2_5M; 294 break; 295 case 100: 296 clk = RK3288_GMAC_CLK_SEL_25M; 297 break; 298 case 1000: 299 clk = RK3288_GMAC_CLK_SEL_125M; 300 break; 301 default: 302 debug("Unknown phy speed: %d\n", priv->phydev->speed); 303 return -EINVAL; 304 } 305 306 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 307 rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk); 308 309 return 0; 310 } 311 312 static int rk3308_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 313 struct rockchip_eth_dev *dev) 314 { 315 struct dw_eth_dev *priv = &dev->dw; 316 struct rk3308_grf *grf; 317 struct clk clk_speed; 318 int speed, ret; 319 enum { 320 RK3308_GMAC_SPEED_SHIFT = 0x0, 321 RK3308_GMAC_SPEED_MASK = BIT(0), 322 RK3308_GMAC_SPEED_10M = 0, 323 RK3308_GMAC_SPEED_100M = BIT(0), 324 }; 325 326 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 327 &clk_speed); 328 if (ret) 329 return ret; 330 331 switch (priv->phydev->speed) { 332 case 10: 333 speed = RK3308_GMAC_SPEED_10M; 334 ret = clk_set_rate(&clk_speed, 2500000); 335 if (ret) 336 return ret; 337 break; 338 case 100: 339 speed = RK3308_GMAC_SPEED_100M; 340 ret = clk_set_rate(&clk_speed, 25000000); 341 if (ret) 342 return ret; 343 break; 344 default: 345 debug("Unknown phy speed: %d\n", priv->phydev->speed); 346 return -EINVAL; 347 } 348 349 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 350 rk_clrsetreg(&grf->mac_con0, RK3308_GMAC_SPEED_MASK, speed); 351 352 return 0; 353 } 354 355 static int rk3328_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 356 struct rockchip_eth_dev *dev) 357 { 358 struct dw_eth_dev *priv = &dev->dw; 359 struct rk3328_grf_regs *grf; 360 int clk; 361 enum { 362 RK3328_GMAC_CLK_SEL_SHIFT = 11, 363 RK3328_GMAC_CLK_SEL_MASK = GENMASK(12, 11), 364 RK3328_GMAC_CLK_SEL_125M = 0 << 11, 365 RK3328_GMAC_CLK_SEL_25M = 3 << 11, 366 RK3328_GMAC_CLK_SEL_2_5M = 2 << 11, 367 368 RK3328_GMAC_RMII_CLK_MASK = BIT(7), 369 RK3328_GMAC_RMII_CLK_2_5M = 0, 370 RK3328_GMAC_RMII_CLK_25M = BIT(7), 371 372 RK3328_GMAC_RMII_SPEED_MASK = BIT(2), 373 RK3328_GMAC_RMII_SPEED_10 = 0, 374 RK3328_GMAC_RMII_SPEED_100 = BIT(2), 375 }; 376 377 switch (priv->phydev->speed) { 378 case 10: 379 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 380 (RK3328_GMAC_RMII_CLK_2_5M | RK3328_GMAC_RMII_SPEED_10) : 381 RK3328_GMAC_CLK_SEL_2_5M; 382 break; 383 case 100: 384 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 385 (RK3328_GMAC_RMII_CLK_25M | RK3328_GMAC_RMII_SPEED_100) : 386 RK3328_GMAC_CLK_SEL_25M; 387 break; 388 case 1000: 389 clk = RK3328_GMAC_CLK_SEL_125M; 390 break; 391 default: 392 debug("Unknown phy speed: %d\n", priv->phydev->speed); 393 return -EINVAL; 394 } 395 396 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 397 rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1], 398 RK3328_GMAC_CLK_SEL_MASK | 399 RK3328_GMAC_RMII_CLK_MASK | 400 RK3328_GMAC_RMII_SPEED_MASK, 401 clk); 402 403 return 0; 404 } 405 406 static int rk3368_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 407 struct rockchip_eth_dev *dev) 408 { 409 struct dw_eth_dev *priv = &dev->dw; 410 struct rk3368_grf *grf; 411 int clk; 412 enum { 413 RK3368_GMAC_CLK_SEL_2_5M = 2 << 4, 414 RK3368_GMAC_CLK_SEL_25M = 3 << 4, 415 RK3368_GMAC_CLK_SEL_125M = 0 << 4, 416 RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4), 417 }; 418 419 switch (priv->phydev->speed) { 420 case 10: 421 clk = RK3368_GMAC_CLK_SEL_2_5M; 422 break; 423 case 100: 424 clk = RK3368_GMAC_CLK_SEL_25M; 425 break; 426 case 1000: 427 clk = RK3368_GMAC_CLK_SEL_125M; 428 break; 429 default: 430 debug("Unknown phy speed: %d\n", priv->phydev->speed); 431 return -EINVAL; 432 } 433 434 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 435 rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk); 436 437 return 0; 438 } 439 440 static int rk3399_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 441 struct rockchip_eth_dev *dev) 442 { 443 struct dw_eth_dev *priv = &dev->dw; 444 struct rk3399_grf_regs *grf; 445 int clk; 446 447 switch (priv->phydev->speed) { 448 case 10: 449 clk = RK3399_GMAC_CLK_SEL_2_5M; 450 break; 451 case 100: 452 clk = RK3399_GMAC_CLK_SEL_25M; 453 break; 454 case 1000: 455 clk = RK3399_GMAC_CLK_SEL_125M; 456 break; 457 default: 458 debug("Unknown phy speed: %d\n", priv->phydev->speed); 459 return -EINVAL; 460 } 461 462 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 463 rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk); 464 465 return 0; 466 } 467 468 static int rv1108_set_rmii_speed(struct gmac_rockchip_platdata *pdata, 469 struct rockchip_eth_dev *dev) 470 { 471 struct dw_eth_dev *priv = &dev->dw; 472 struct rv1108_grf *grf; 473 int clk, speed; 474 enum { 475 RV1108_GMAC_SPEED_MASK = BIT(2), 476 RV1108_GMAC_SPEED_10M = 0 << 2, 477 RV1108_GMAC_SPEED_100M = 1 << 2, 478 RV1108_GMAC_CLK_SEL_MASK = BIT(7), 479 RV1108_GMAC_CLK_SEL_2_5M = 0 << 7, 480 RV1108_GMAC_CLK_SEL_25M = 1 << 7, 481 }; 482 483 switch (priv->phydev->speed) { 484 case 10: 485 clk = RV1108_GMAC_CLK_SEL_2_5M; 486 speed = RV1108_GMAC_SPEED_10M; 487 break; 488 case 100: 489 clk = RV1108_GMAC_CLK_SEL_25M; 490 speed = RV1108_GMAC_SPEED_100M; 491 break; 492 default: 493 debug("Unknown phy speed: %d\n", priv->phydev->speed); 494 return -EINVAL; 495 } 496 497 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 498 rk_clrsetreg(&grf->gmac_con0, 499 RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK, 500 clk | speed); 501 502 return 0; 503 } 504 #else 505 static int rv1126_set_rgmii_speed(struct gmac_rockchip_platdata *pdata, 506 struct rockchip_eth_dev *dev) 507 { 508 struct eqos_priv *priv = &dev->eqos; 509 struct clk clk_speed; 510 int ret; 511 512 ret = clk_get_by_name(priv->phy->dev, "clk_mac_speed", 513 &clk_speed); 514 if (ret) { 515 printf("%s can't get clk_mac_speed clock (ret=%d):\n", 516 __func__, ret); 517 return ret; 518 } 519 520 switch ( priv->phy->speed) { 521 case 10: 522 ret = clk_set_rate(&clk_speed, 2500000); 523 if (ret) 524 return ret; 525 break; 526 case 100: 527 ret = clk_set_rate(&clk_speed, 25000000); 528 if (ret) 529 return ret; 530 break; 531 case 1000: 532 ret = clk_set_rate(&clk_speed, 125000000); 533 if (ret) 534 return ret; 535 break; 536 default: 537 debug("Unknown phy speed: %d\n", priv->phy->speed); 538 return -EINVAL; 539 } 540 541 return 0; 542 } 543 #endif 544 545 #ifndef CONFIG_DWC_ETH_QOS 546 static void px30_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 547 { 548 struct px30_grf *grf; 549 enum { 550 px30_GMAC_PHY_INTF_SEL_SHIFT = 4, 551 px30_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 6), 552 px30_GMAC_PHY_INTF_SEL_RMII = BIT(6), 553 }; 554 555 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 556 557 rk_clrsetreg(&grf->mac_con1, 558 px30_GMAC_PHY_INTF_SEL_MASK, 559 px30_GMAC_PHY_INTF_SEL_RMII); 560 } 561 562 static void rk1808_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 563 { 564 struct rk1808_grf *grf; 565 enum { 566 RK1808_GMAC_PHY_INTF_SEL_SHIFT = 4, 567 RK1808_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 568 RK1808_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 569 570 RK1808_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 571 RK1808_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 572 RK1808_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 573 574 RK1808_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 575 RK1808_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 576 RK1808_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 577 }; 578 enum { 579 RK1808_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 580 RK1808_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 7), 581 582 RK1808_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 583 RK1808_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 584 }; 585 586 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 587 rk_clrsetreg(&grf->mac_con1, 588 RK1808_GMAC_PHY_INTF_SEL_MASK | 589 RK1808_RXCLK_DLY_ENA_GMAC_MASK | 590 RK1808_TXCLK_DLY_ENA_GMAC_MASK, 591 RK1808_GMAC_PHY_INTF_SEL_RGMII | 592 RK1808_RXCLK_DLY_ENA_GMAC_ENABLE | 593 RK1808_TXCLK_DLY_ENA_GMAC_ENABLE); 594 595 rk_clrsetreg(&grf->mac_con0, 596 RK1808_CLK_RX_DL_CFG_GMAC_MASK | 597 RK1808_CLK_TX_DL_CFG_GMAC_MASK, 598 pdata->rx_delay << RK1808_CLK_RX_DL_CFG_GMAC_SHIFT | 599 pdata->tx_delay << RK1808_CLK_TX_DL_CFG_GMAC_SHIFT); 600 } 601 602 static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 603 { 604 struct rk322x_grf *grf; 605 enum { 606 RK3228_RMII_MODE_SHIFT = 10, 607 RK3228_RMII_MODE_MASK = BIT(10), 608 609 RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4, 610 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 611 RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 612 613 RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 614 RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 615 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 616 617 RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 618 RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 619 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 620 }; 621 enum { 622 RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 623 RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 624 625 RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 626 RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 627 }; 628 629 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 630 rk_clrsetreg(&grf->mac_con[1], 631 RK3228_RMII_MODE_MASK | 632 RK3228_GMAC_PHY_INTF_SEL_MASK | 633 RK3228_RXCLK_DLY_ENA_GMAC_MASK | 634 RK3228_TXCLK_DLY_ENA_GMAC_MASK, 635 RK3228_GMAC_PHY_INTF_SEL_RGMII | 636 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE | 637 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE); 638 639 rk_clrsetreg(&grf->mac_con[0], 640 RK3228_CLK_RX_DL_CFG_GMAC_MASK | 641 RK3228_CLK_TX_DL_CFG_GMAC_MASK, 642 pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT | 643 pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT); 644 } 645 646 static void rk3228_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 647 { 648 struct rk322x_grf *grf; 649 enum { 650 RK3228_GRF_CON_RMII_MODE_MASK = BIT(11), 651 RK3228_GRF_CON_RMII_MODE_SEL = BIT(11), 652 RK3228_RMII_MODE_MASK = BIT(10), 653 RK3228_RMII_MODE_SEL = BIT(10), 654 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 655 RK3228_GMAC_PHY_INTF_SEL_RMII = BIT(6), 656 }; 657 658 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 659 rk_clrsetreg(&grf->mac_con[1], 660 RK3228_GRF_CON_RMII_MODE_MASK | 661 RK3228_RMII_MODE_MASK | 662 RK3228_GMAC_PHY_INTF_SEL_MASK, 663 RK3228_GRF_CON_RMII_MODE_SEL | 664 RK3228_RMII_MODE_SEL | 665 RK3228_GMAC_PHY_INTF_SEL_RMII); 666 } 667 668 static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 669 { 670 struct rk3288_grf *grf; 671 672 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 673 rk_clrsetreg(&grf->soc_con1, 674 RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK, 675 RK3288_GMAC_PHY_INTF_SEL_RGMII); 676 677 rk_clrsetreg(&grf->soc_con3, 678 RK3288_RXCLK_DLY_ENA_GMAC_MASK | 679 RK3288_TXCLK_DLY_ENA_GMAC_MASK | 680 RK3288_CLK_RX_DL_CFG_GMAC_MASK | 681 RK3288_CLK_TX_DL_CFG_GMAC_MASK, 682 RK3288_RXCLK_DLY_ENA_GMAC_ENABLE | 683 RK3288_TXCLK_DLY_ENA_GMAC_ENABLE | 684 pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT | 685 pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT); 686 } 687 688 static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 689 { 690 struct rk3308_grf *grf; 691 enum { 692 RK3308_GMAC_PHY_INTF_SEL_SHIFT = 2, 693 RK3308_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 2), 694 RK3308_GMAC_PHY_INTF_SEL_RMII = BIT(4), 695 }; 696 697 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 698 699 rk_clrsetreg(&grf->mac_con0, 700 RK3308_GMAC_PHY_INTF_SEL_MASK, 701 RK3308_GMAC_PHY_INTF_SEL_RMII); 702 } 703 704 static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 705 { 706 struct rk3328_grf_regs *grf; 707 enum { 708 RK3328_RMII_MODE_SHIFT = 9, 709 RK3328_RMII_MODE_MASK = BIT(9), 710 711 RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4, 712 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 713 RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 714 715 RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 716 RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 717 RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 718 719 RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 720 RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 721 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 722 }; 723 enum { 724 RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 725 RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 726 727 RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 728 RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 729 }; 730 731 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 732 rk_clrsetreg(&grf->mac_con[1], 733 RK3328_RMII_MODE_MASK | 734 RK3328_GMAC_PHY_INTF_SEL_MASK | 735 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 736 RK3328_TXCLK_DLY_ENA_GMAC_MASK, 737 RK3328_GMAC_PHY_INTF_SEL_RGMII | 738 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 739 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE); 740 741 rk_clrsetreg(&grf->mac_con[0], 742 RK3328_CLK_RX_DL_CFG_GMAC_MASK | 743 RK3328_CLK_TX_DL_CFG_GMAC_MASK, 744 pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT | 745 pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT); 746 } 747 748 static void rk3328_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 749 { 750 struct rk3328_grf_regs *grf; 751 enum { 752 RK3328_RMII_MODE_MASK = BIT(9), 753 RK3328_RMII_MODE = BIT(9), 754 755 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 756 RK3328_GMAC_PHY_INTF_SEL_RMII = BIT(6), 757 }; 758 759 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 760 rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1], 761 RK3328_RMII_MODE_MASK | 762 RK3328_GMAC_PHY_INTF_SEL_MASK, 763 RK3328_GMAC_PHY_INTF_SEL_RMII | 764 RK3328_RMII_MODE); 765 } 766 767 static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 768 { 769 struct rk3368_grf *grf; 770 enum { 771 RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9, 772 RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9), 773 RK3368_RMII_MODE_MASK = BIT(6), 774 RK3368_RMII_MODE = BIT(6), 775 }; 776 enum { 777 RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15), 778 RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 779 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15), 780 RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7), 781 RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 782 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7), 783 RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8, 784 RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 785 RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0, 786 RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 787 }; 788 789 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 790 rk_clrsetreg(&grf->soc_con15, 791 RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK, 792 RK3368_GMAC_PHY_INTF_SEL_RGMII); 793 794 rk_clrsetreg(&grf->soc_con16, 795 RK3368_RXCLK_DLY_ENA_GMAC_MASK | 796 RK3368_TXCLK_DLY_ENA_GMAC_MASK | 797 RK3368_CLK_RX_DL_CFG_GMAC_MASK | 798 RK3368_CLK_TX_DL_CFG_GMAC_MASK, 799 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE | 800 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE | 801 pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT | 802 pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT); 803 } 804 805 static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 806 { 807 struct rk3399_grf_regs *grf; 808 809 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 810 811 rk_clrsetreg(&grf->soc_con5, 812 RK3399_GMAC_PHY_INTF_SEL_MASK, 813 RK3399_GMAC_PHY_INTF_SEL_RGMII); 814 815 rk_clrsetreg(&grf->soc_con6, 816 RK3399_RXCLK_DLY_ENA_GMAC_MASK | 817 RK3399_TXCLK_DLY_ENA_GMAC_MASK | 818 RK3399_CLK_RX_DL_CFG_GMAC_MASK | 819 RK3399_CLK_TX_DL_CFG_GMAC_MASK, 820 RK3399_RXCLK_DLY_ENA_GMAC_ENABLE | 821 RK3399_TXCLK_DLY_ENA_GMAC_ENABLE | 822 pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT | 823 pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT); 824 } 825 826 static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 827 { 828 struct rv1108_grf *grf; 829 830 enum { 831 RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 832 RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4, 833 }; 834 835 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 836 rk_clrsetreg(&grf->gmac_con0, 837 RV1108_GMAC_PHY_INTF_SEL_MASK, 838 RV1108_GMAC_PHY_INTF_SEL_RMII); 839 } 840 841 static void rk3228_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 842 { 843 struct rk322x_grf *grf; 844 enum { 845 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK = BIT(15), 846 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY = BIT(15), 847 }; 848 enum { 849 RK3228_MACPHY_CFG_CLK_50M_MASK = BIT(14), 850 RK3228_MACPHY_CFG_CLK_50M = BIT(14), 851 852 RK3228_MACPHY_RMII_MODE_MASK = GENMASK(7, 6), 853 RK3228_MACPHY_RMII_MODE = BIT(6), 854 855 RK3228_MACPHY_ENABLE_MASK = BIT(0), 856 RK3228_MACPHY_DISENABLE = 0, 857 RK3228_MACPHY_ENABLE = BIT(0), 858 }; 859 enum { 860 RK3228_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0), 861 RK3228_RK_GRF_CON2_MACPHY_ID = 0x1234, 862 }; 863 enum { 864 RK3228_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0), 865 RK3228_RK_GRF_CON3_MACPHY_ID = 0x35, 866 }; 867 868 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 869 rk_clrsetreg(&grf->con_iomux, 870 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK, 871 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY); 872 873 rk_clrsetreg(&grf->macphy_con[2], 874 RK3228_RK_GRF_CON2_MACPHY_ID_MASK, 875 RK3228_RK_GRF_CON2_MACPHY_ID); 876 877 rk_clrsetreg(&grf->macphy_con[3], 878 RK3228_RK_GRF_CON3_MACPHY_ID_MASK, 879 RK3228_RK_GRF_CON3_MACPHY_ID); 880 881 /* disabled before trying to reset it &*/ 882 rk_clrsetreg(&grf->macphy_con[0], 883 RK3228_MACPHY_CFG_CLK_50M_MASK | 884 RK3228_MACPHY_RMII_MODE_MASK | 885 RK3228_MACPHY_ENABLE_MASK, 886 RK3228_MACPHY_CFG_CLK_50M | 887 RK3228_MACPHY_RMII_MODE | 888 RK3228_MACPHY_DISENABLE); 889 890 reset_assert(&pdata->phy_reset); 891 udelay(10); 892 reset_deassert(&pdata->phy_reset); 893 udelay(10); 894 895 rk_clrsetreg(&grf->macphy_con[0], 896 RK3228_MACPHY_ENABLE_MASK, 897 RK3228_MACPHY_ENABLE); 898 udelay(30 * 1000); 899 } 900 901 static void rk3328_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 902 { 903 struct rk3328_grf_regs *grf; 904 enum { 905 RK3328_GRF_CON_RMII_MODE_MASK = BIT(9), 906 RK3328_GRF_CON_RMII_MODE = BIT(9), 907 }; 908 enum { 909 RK3328_MACPHY_CFG_CLK_50M_MASK = BIT(14), 910 RK3328_MACPHY_CFG_CLK_50M = BIT(14), 911 912 RK3328_MACPHY_RMII_MODE_MASK = GENMASK(7, 6), 913 RK3328_MACPHY_RMII_MODE = BIT(6), 914 915 RK3328_MACPHY_ENABLE_MASK = BIT(0), 916 RK3328_MACPHY_DISENABLE = 0, 917 RK3328_MACPHY_ENABLE = BIT(0), 918 }; 919 enum { 920 RK3328_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0), 921 RK3328_RK_GRF_CON2_MACPHY_ID = 0x1234, 922 }; 923 enum { 924 RK3328_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0), 925 RK3328_RK_GRF_CON3_MACPHY_ID = 0x35, 926 }; 927 928 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 929 rk_clrsetreg(&grf->macphy_con[1], 930 RK3328_GRF_CON_RMII_MODE_MASK, 931 RK3328_GRF_CON_RMII_MODE); 932 933 rk_clrsetreg(&grf->macphy_con[2], 934 RK3328_RK_GRF_CON2_MACPHY_ID_MASK, 935 RK3328_RK_GRF_CON2_MACPHY_ID); 936 937 rk_clrsetreg(&grf->macphy_con[3], 938 RK3328_RK_GRF_CON3_MACPHY_ID_MASK, 939 RK3328_RK_GRF_CON3_MACPHY_ID); 940 941 /* disabled before trying to reset it &*/ 942 rk_clrsetreg(&grf->macphy_con[0], 943 RK3328_MACPHY_CFG_CLK_50M_MASK | 944 RK3328_MACPHY_RMII_MODE_MASK | 945 RK3328_MACPHY_ENABLE_MASK, 946 RK3328_MACPHY_CFG_CLK_50M | 947 RK3328_MACPHY_RMII_MODE | 948 RK3328_MACPHY_DISENABLE); 949 950 reset_assert(&pdata->phy_reset); 951 udelay(10); 952 reset_deassert(&pdata->phy_reset); 953 udelay(10); 954 955 rk_clrsetreg(&grf->macphy_con[0], 956 RK3328_MACPHY_ENABLE_MASK, 957 RK3328_MACPHY_ENABLE); 958 udelay(30 * 1000); 959 } 960 961 #else 962 static void rk3568_set_to_rmii(struct gmac_rockchip_platdata *pdata) 963 { 964 struct rk3568_grf *grf; 965 void *con1; 966 967 enum { 968 RK3568_GMAC_PHY_INTF_SEL_SHIFT = 4, 969 RK3568_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 970 RK3568_GMAC_PHY_INTF_SEL_RMII = BIT(6), 971 }; 972 973 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 974 975 if (pdata->bus_id == 1) 976 con1 = &grf->mac1_con1; 977 else 978 con1 = &grf->mac0_con1; 979 980 rk_clrsetreg(con1, 981 RK3568_GMAC_PHY_INTF_SEL_MASK, 982 RK3568_GMAC_PHY_INTF_SEL_RMII); 983 } 984 985 static void rk3568_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 986 { 987 struct rk3568_grf *grf; 988 void *con0, *con1; 989 990 enum { 991 RK3568_GMAC_PHY_INTF_SEL_SHIFT = 4, 992 RK3568_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 993 RK3568_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 994 995 RK3568_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 996 RK3568_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 997 RK3568_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 998 999 RK3568_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 1000 RK3568_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 1001 RK3568_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 1002 }; 1003 1004 enum { 1005 RK3568_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1006 RK3568_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 8), 1007 1008 RK3568_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1009 RK3568_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 1010 }; 1011 1012 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1013 1014 if (pdata->bus_id == 1) { 1015 con0 = &grf->mac1_con0; 1016 con1 = &grf->mac1_con1; 1017 } else { 1018 con0 = &grf->mac0_con0; 1019 con1 = &grf->mac0_con1; 1020 } 1021 1022 rk_clrsetreg(con0, 1023 RK3568_CLK_RX_DL_CFG_GMAC_MASK | 1024 RK3568_CLK_TX_DL_CFG_GMAC_MASK, 1025 pdata->rx_delay << RK3568_CLK_RX_DL_CFG_GMAC_SHIFT | 1026 pdata->tx_delay << RK3568_CLK_TX_DL_CFG_GMAC_SHIFT); 1027 1028 rk_clrsetreg(con1, 1029 RK3568_TXCLK_DLY_ENA_GMAC_MASK | 1030 RK3568_RXCLK_DLY_ENA_GMAC_MASK | 1031 RK3568_GMAC_PHY_INTF_SEL_MASK, 1032 RK3568_TXCLK_DLY_ENA_GMAC_ENABLE | 1033 RK3568_RXCLK_DLY_ENA_GMAC_ENABLE | 1034 RK3568_GMAC_PHY_INTF_SEL_RGMII); 1035 } 1036 1037 static void rv1126_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1038 { 1039 struct rv1126_grf *grf; 1040 1041 enum { 1042 RV1126_GMAC_PHY_INTF_SEL_SHIFT = 4, 1043 RV1126_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1044 RV1126_GMAC_PHY_INTF_SEL_RMII = BIT(6), 1045 }; 1046 1047 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1048 1049 rk_clrsetreg(&grf->mac_con0, 1050 RV1126_GMAC_PHY_INTF_SEL_MASK, 1051 RV1126_GMAC_PHY_INTF_SEL_RMII); 1052 } 1053 1054 static void rv1126_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1055 { 1056 struct rv1126_grf *grf; 1057 1058 enum { 1059 RV1126_GMAC_PHY_INTF_SEL_SHIFT = 4, 1060 RV1126_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1061 RV1126_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 1062 1063 RV1126_RXCLK_M1_DLY_ENA_GMAC_MASK = BIT(3), 1064 RV1126_RXCLK_M1_DLY_ENA_GMAC_DISABLE = 0, 1065 RV1126_RXCLK_M1_DLY_ENA_GMAC_ENABLE = BIT(3), 1066 1067 RV1126_TXCLK_M1_DLY_ENA_GMAC_MASK = BIT(2), 1068 RV1126_TXCLK_M1_DLY_ENA_GMAC_DISABLE = 0, 1069 RV1126_TXCLK_M1_DLY_ENA_GMAC_ENABLE = BIT(2), 1070 1071 RV1126_RXCLK_M0_DLY_ENA_GMAC_MASK = BIT(1), 1072 RV1126_RXCLK_M0_DLY_ENA_GMAC_DISABLE = 0, 1073 RV1126_RXCLK_M0_DLY_ENA_GMAC_ENABLE = BIT(1), 1074 1075 RV1126_TXCLK_M0_DLY_ENA_GMAC_MASK = BIT(0), 1076 RV1126_TXCLK_M0_DLY_ENA_GMAC_DISABLE = 0, 1077 RV1126_TXCLK_M0_DLY_ENA_GMAC_ENABLE = BIT(0), 1078 }; 1079 enum { 1080 RV1126_M0_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1081 RV1126_M0_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 1082 1083 RV1126_M0_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1084 RV1126_M0_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 1085 }; 1086 enum { 1087 RV1126_M1_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1088 RV1126_M1_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 1089 1090 RV1126_M1_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1091 RV1126_M1_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 1092 }; 1093 1094 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1095 1096 rk_clrsetreg(&grf->mac_con0, 1097 RV1126_TXCLK_M0_DLY_ENA_GMAC_MASK | 1098 RV1126_RXCLK_M0_DLY_ENA_GMAC_MASK | 1099 RV1126_TXCLK_M1_DLY_ENA_GMAC_MASK | 1100 RV1126_RXCLK_M1_DLY_ENA_GMAC_MASK | 1101 RV1126_GMAC_PHY_INTF_SEL_MASK, 1102 RV1126_TXCLK_M0_DLY_ENA_GMAC_ENABLE | 1103 RV1126_RXCLK_M0_DLY_ENA_GMAC_ENABLE | 1104 RV1126_TXCLK_M1_DLY_ENA_GMAC_ENABLE | 1105 RV1126_RXCLK_M1_DLY_ENA_GMAC_ENABLE | 1106 RV1126_GMAC_PHY_INTF_SEL_RGMII); 1107 1108 rk_clrsetreg(&grf->mac_con1, 1109 RV1126_M0_CLK_RX_DL_CFG_GMAC_MASK | 1110 RV1126_M0_CLK_TX_DL_CFG_GMAC_MASK, 1111 pdata->rx_delay << RV1126_M0_CLK_RX_DL_CFG_GMAC_SHIFT | 1112 pdata->tx_delay << RV1126_M0_CLK_TX_DL_CFG_GMAC_SHIFT); 1113 1114 rk_clrsetreg(&grf->mac_con2, 1115 RV1126_M1_CLK_RX_DL_CFG_GMAC_MASK | 1116 RV1126_M1_CLK_TX_DL_CFG_GMAC_MASK, 1117 pdata->rx_delay << RV1126_M1_CLK_RX_DL_CFG_GMAC_SHIFT | 1118 pdata->tx_delay << RV1126_M1_CLK_TX_DL_CFG_GMAC_SHIFT); 1119 } 1120 #endif 1121 1122 static int gmac_rockchip_probe(struct udevice *dev) 1123 { 1124 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 1125 struct rk_gmac_ops *ops = 1126 (struct rk_gmac_ops *)dev_get_driver_data(dev); 1127 #ifdef CONFIG_DWC_ETH_QOS 1128 struct eqos_config *config; 1129 #else 1130 struct dw_eth_pdata *dw_pdata; 1131 #endif 1132 struct eth_pdata *eth_pdata; 1133 struct clk clk; 1134 ulong rate; 1135 int ret; 1136 1137 #ifdef CONFIG_DWC_ETH_QOS 1138 eth_pdata = &pdata->eth_pdata; 1139 config = (struct eqos_config *)&ops->config; 1140 memcpy(config, &eqos_rockchip_config, sizeof(struct eqos_config)); 1141 eth_pdata->phy_interface = config->ops->eqos_get_interface(dev); 1142 #else 1143 dw_pdata = &pdata->dw_eth_pdata; 1144 eth_pdata = &dw_pdata->eth_pdata; 1145 #endif 1146 pdata->bus_id = dev->seq; 1147 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 1148 ret = clk_set_defaults(dev); 1149 if (ret) 1150 debug("%s clk_set_defaults failed %d\n", __func__, ret); 1151 1152 ret = clk_get_by_index(dev, 0, &clk); 1153 if (ret) 1154 return ret; 1155 1156 pdata->phy_interface = eth_pdata->phy_interface; 1157 1158 if (pdata->integrated_phy && ops->integrated_phy_powerup) 1159 ops->integrated_phy_powerup(pdata); 1160 1161 switch (eth_pdata->phy_interface) { 1162 case PHY_INTERFACE_MODE_RGMII: 1163 /* 1164 * If the gmac clock is from internal pll, need to set and 1165 * check the return value for gmac clock at RGMII mode. If 1166 * the gmac clock is from external source, the clock rate 1167 * is not set, because of it is bypassed. 1168 */ 1169 if (!pdata->clock_input) { 1170 rate = clk_set_rate(&clk, 125000000); 1171 if (rate != 125000000) 1172 return -EINVAL; 1173 } 1174 1175 /* Set to RGMII mode */ 1176 if (ops->set_to_rgmii) 1177 ops->set_to_rgmii(pdata); 1178 else 1179 return -EPERM; 1180 1181 break; 1182 case PHY_INTERFACE_MODE_RMII: 1183 /* The commet is the same as RGMII mode */ 1184 if (!pdata->clock_input) { 1185 rate = clk_set_rate(&clk, 50000000); 1186 if (rate != 50000000) 1187 return -EINVAL; 1188 } 1189 1190 /* Set to RMII mode */ 1191 if (ops->set_to_rmii) 1192 ops->set_to_rmii(pdata); 1193 else 1194 return -EPERM; 1195 1196 break; 1197 default: 1198 debug("NO interface defined!\n"); 1199 return -ENXIO; 1200 } 1201 1202 #ifdef CONFIG_DWC_ETH_QOS 1203 return eqos_probe(dev); 1204 #else 1205 return designware_eth_probe(dev); 1206 #endif 1207 } 1208 1209 static int gmac_rockchip_eth_write_hwaddr(struct udevice *dev) 1210 { 1211 #if defined(CONFIG_DWC_ETH_QOS) 1212 return eqos_write_hwaddr(dev); 1213 #else 1214 return designware_eth_write_hwaddr(dev); 1215 #endif 1216 } 1217 1218 static int gmac_rockchip_eth_free_pkt(struct udevice *dev, uchar *packet, 1219 int length) 1220 { 1221 #ifdef CONFIG_DWC_ETH_QOS 1222 return eqos_free_pkt(dev, packet, length); 1223 #else 1224 return designware_eth_free_pkt(dev, packet, length); 1225 #endif 1226 } 1227 1228 static int gmac_rockchip_eth_send(struct udevice *dev, void *packet, 1229 int length) 1230 { 1231 #ifdef CONFIG_DWC_ETH_QOS 1232 return eqos_send(dev, packet, length); 1233 #else 1234 return designware_eth_send(dev, packet, length); 1235 #endif 1236 } 1237 1238 static int gmac_rockchip_eth_recv(struct udevice *dev, int flags, 1239 uchar **packetp) 1240 { 1241 #ifdef CONFIG_DWC_ETH_QOS 1242 return eqos_recv(dev, flags, packetp); 1243 #else 1244 return designware_eth_recv(dev, flags, packetp); 1245 #endif 1246 } 1247 1248 static int gmac_rockchip_eth_start(struct udevice *dev) 1249 { 1250 struct rockchip_eth_dev *priv = dev_get_priv(dev); 1251 struct rk_gmac_ops *ops = 1252 (struct rk_gmac_ops *)dev_get_driver_data(dev); 1253 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 1254 #ifndef CONFIG_DWC_ETH_QOS 1255 struct dw_eth_pdata *dw_pdata; 1256 struct eth_pdata *eth_pdata; 1257 #endif 1258 int ret; 1259 1260 #ifdef CONFIG_DWC_ETH_QOS 1261 ret = eqos_init(dev); 1262 #else 1263 dw_pdata = &pdata->dw_eth_pdata; 1264 eth_pdata = &dw_pdata->eth_pdata; 1265 ret = designware_eth_init((struct dw_eth_dev *)priv, 1266 eth_pdata->enetaddr); 1267 #endif 1268 if (ret) 1269 return ret; 1270 ret = ops->fix_mac_speed(pdata, priv); 1271 if (ret) 1272 return ret; 1273 1274 #ifdef CONFIG_DWC_ETH_QOS 1275 eqos_enable(dev); 1276 #else 1277 ret = designware_eth_enable((struct dw_eth_dev *)priv); 1278 if (ret) 1279 return ret; 1280 #endif 1281 1282 return 0; 1283 } 1284 1285 static void gmac_rockchip_eth_stop(struct udevice *dev) 1286 { 1287 #ifdef CONFIG_DWC_ETH_QOS 1288 eqos_stop(dev); 1289 #else 1290 designware_eth_stop(dev); 1291 #endif 1292 } 1293 1294 const struct eth_ops gmac_rockchip_eth_ops = { 1295 .start = gmac_rockchip_eth_start, 1296 .send = gmac_rockchip_eth_send, 1297 .recv = gmac_rockchip_eth_recv, 1298 .free_pkt = gmac_rockchip_eth_free_pkt, 1299 .stop = gmac_rockchip_eth_stop, 1300 .write_hwaddr = gmac_rockchip_eth_write_hwaddr, 1301 }; 1302 1303 #ifndef CONFIG_DWC_ETH_QOS 1304 const struct rk_gmac_ops px30_gmac_ops = { 1305 .fix_mac_speed = px30_gmac_fix_mac_speed, 1306 .set_to_rmii = px30_gmac_set_to_rmii, 1307 }; 1308 1309 const struct rk_gmac_ops rk1808_gmac_ops = { 1310 .fix_mac_speed = rk1808_gmac_fix_mac_speed, 1311 .set_to_rgmii = rk1808_gmac_set_to_rgmii, 1312 }; 1313 1314 const struct rk_gmac_ops rk3228_gmac_ops = { 1315 .fix_mac_speed = rk3228_gmac_fix_mac_speed, 1316 .set_to_rmii = rk3228_gmac_set_to_rmii, 1317 .set_to_rgmii = rk3228_gmac_set_to_rgmii, 1318 .integrated_phy_powerup = rk3228_gmac_integrated_phy_powerup, 1319 }; 1320 1321 const struct rk_gmac_ops rk3288_gmac_ops = { 1322 .fix_mac_speed = rk3288_gmac_fix_mac_speed, 1323 .set_to_rgmii = rk3288_gmac_set_to_rgmii, 1324 }; 1325 1326 const struct rk_gmac_ops rk3308_gmac_ops = { 1327 .fix_mac_speed = rk3308_gmac_fix_mac_speed, 1328 .set_to_rmii = rk3308_gmac_set_to_rmii, 1329 }; 1330 1331 const struct rk_gmac_ops rk3328_gmac_ops = { 1332 .fix_mac_speed = rk3328_gmac_fix_mac_speed, 1333 .set_to_rmii = rk3328_gmac_set_to_rmii, 1334 .set_to_rgmii = rk3328_gmac_set_to_rgmii, 1335 .integrated_phy_powerup = rk3328_gmac_integrated_phy_powerup, 1336 }; 1337 1338 const struct rk_gmac_ops rk3368_gmac_ops = { 1339 .fix_mac_speed = rk3368_gmac_fix_mac_speed, 1340 .set_to_rgmii = rk3368_gmac_set_to_rgmii, 1341 }; 1342 1343 const struct rk_gmac_ops rk3399_gmac_ops = { 1344 .fix_mac_speed = rk3399_gmac_fix_mac_speed, 1345 .set_to_rgmii = rk3399_gmac_set_to_rgmii, 1346 }; 1347 1348 const struct rk_gmac_ops rv1108_gmac_ops = { 1349 .fix_mac_speed = rv1108_set_rmii_speed, 1350 .set_to_rmii = rv1108_gmac_set_to_rmii, 1351 }; 1352 #else 1353 const struct rk_gmac_ops rk3568_gmac_ops = { 1354 .fix_mac_speed = rv1126_set_rgmii_speed, 1355 .set_to_rgmii = rk3568_set_to_rgmii, 1356 .set_to_rmii = rk3568_set_to_rmii, 1357 }; 1358 1359 const struct rk_gmac_ops rv1126_gmac_ops = { 1360 .fix_mac_speed = rv1126_set_rgmii_speed, 1361 .set_to_rgmii = rv1126_set_to_rgmii, 1362 .set_to_rmii = rv1126_set_to_rmii, 1363 }; 1364 #endif 1365 1366 static const struct udevice_id rockchip_gmac_ids[] = { 1367 #ifndef CONFIG_DWC_ETH_QOS 1368 { .compatible = "rockchip,px30-gmac", 1369 .data = (ulong)&px30_gmac_ops }, 1370 { .compatible = "rockchip,rk1808-gmac", 1371 .data = (ulong)&rk1808_gmac_ops }, 1372 { .compatible = "rockchip,rk3228-gmac", 1373 .data = (ulong)&rk3228_gmac_ops }, 1374 { .compatible = "rockchip,rk3288-gmac", 1375 .data = (ulong)&rk3288_gmac_ops }, 1376 { .compatible = "rockchip,rk3308-mac", 1377 .data = (ulong)&rk3308_gmac_ops }, 1378 { .compatible = "rockchip,rk3328-gmac", 1379 .data = (ulong)&rk3328_gmac_ops }, 1380 { .compatible = "rockchip,rk3368-gmac", 1381 .data = (ulong)&rk3368_gmac_ops }, 1382 { .compatible = "rockchip,rk3399-gmac", 1383 .data = (ulong)&rk3399_gmac_ops }, 1384 { .compatible = "rockchip,rv1108-gmac", 1385 .data = (ulong)&rv1108_gmac_ops }, 1386 #else 1387 { .compatible = "rockchip,rk3568-gmac", 1388 .data = (ulong)&rk3568_gmac_ops }, 1389 { .compatible = "rockchip,rv1126-gmac", 1390 .data = (ulong)&rv1126_gmac_ops }, 1391 #endif 1392 { } 1393 }; 1394 1395 U_BOOT_DRIVER(eth_gmac_rockchip) = { 1396 .name = "gmac_rockchip", 1397 .id = UCLASS_ETH, 1398 .of_match = rockchip_gmac_ids, 1399 .ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata, 1400 .probe = gmac_rockchip_probe, 1401 .ops = &gmac_rockchip_eth_ops, 1402 .priv_auto_alloc_size = sizeof(struct rockchip_eth_dev), 1403 .platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata), 1404 .flags = DM_FLAG_ALLOC_PRIV_DMA, 1405 }; 1406