1 /* 2 * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Rockchip GMAC ethernet IP driver for U-Boot 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <clk.h> 12 #include <phy.h> 13 #include <syscon.h> 14 #include <asm/io.h> 15 #include <asm/arch/periph.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/hardware.h> 18 #ifdef CONFIG_DWC_ETH_QOS 19 #include <asm/arch/grf_rk3568.h> 20 #include <asm/arch/grf_rv1126.h> 21 #include "dwc_eth_qos.h" 22 #else 23 #include <asm/arch/grf_px30.h> 24 #include <asm/arch/grf_rk1808.h> 25 #include <asm/arch/grf_rk322x.h> 26 #include <asm/arch/grf_rk3288.h> 27 #include <asm/arch/grf_rk3308.h> 28 #include <asm/arch/grf_rk3328.h> 29 #include <asm/arch/grf_rk3368.h> 30 #include <asm/arch/grf_rk3399.h> 31 #include <asm/arch/grf_rv1108.h> 32 #include "designware.h" 33 #include <dt-bindings/clock/rk3288-cru.h> 34 #endif 35 #include <dm/pinctrl.h> 36 37 DECLARE_GLOBAL_DATA_PTR; 38 39 struct rockchip_eth_dev { 40 #ifdef CONFIG_DWC_ETH_QOS 41 struct eqos_priv eqos; 42 #else 43 struct dw_eth_dev dw; 44 #endif 45 }; 46 47 /* 48 * Platform data for the gmac 49 * 50 * dw_eth_pdata: Required platform data for designware driver (must be first) 51 */ 52 struct gmac_rockchip_platdata { 53 #ifndef CONFIG_DWC_ETH_QOS 54 struct dw_eth_pdata dw_eth_pdata; 55 #else 56 struct eth_pdata eth_pdata; 57 #endif 58 bool clock_input; 59 int tx_delay; 60 int rx_delay; 61 int bus_id; 62 }; 63 64 struct rk_gmac_ops { 65 #ifdef CONFIG_DWC_ETH_QOS 66 const struct eqos_config config; 67 #endif 68 int (*fix_mac_speed)(struct rockchip_eth_dev *dev); 69 void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata); 70 void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata); 71 }; 72 73 #ifdef CONFIG_DWC_ETH_QOS 74 static const struct eqos_config eqos_rockchip_config = { 75 .reg_access_always_ok = false, 76 .mdio_wait = 10000, 77 .swr_wait = 200, 78 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED, 79 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_100_150, 80 .ops = &eqos_rockchip_ops, 81 }; 82 #endif 83 84 void gmac_set_rgmii(struct udevice *dev, u32 tx_delay, u32 rx_delay) 85 { 86 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 87 struct rk_gmac_ops *ops = 88 (struct rk_gmac_ops *)dev_get_driver_data(dev); 89 90 pdata->tx_delay = tx_delay; 91 pdata->rx_delay = rx_delay; 92 93 ops->set_to_rgmii(pdata); 94 } 95 96 static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) 97 { 98 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 99 const char *string; 100 101 string = dev_read_string(dev, "clock_in_out"); 102 if (!strcmp(string, "input")) 103 pdata->clock_input = true; 104 else 105 pdata->clock_input = false; 106 107 /* Check the new naming-style first... */ 108 pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT); 109 pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT); 110 111 /* ... and fall back to the old naming style or default, if necessary */ 112 if (pdata->tx_delay == -ENOENT) 113 pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30); 114 if (pdata->rx_delay == -ENOENT) 115 pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10); 116 117 #ifdef CONFIG_DWC_ETH_QOS 118 return 0; 119 #else 120 return designware_eth_ofdata_to_platdata(dev); 121 #endif 122 } 123 124 #ifndef CONFIG_DWC_ETH_QOS 125 static int px30_gmac_fix_mac_speed(struct rockchip_eth_dev *dev) 126 { 127 struct dw_eth_dev *priv = &dev->dw; 128 struct px30_grf *grf; 129 struct clk clk_speed; 130 int speed, ret; 131 enum { 132 PX30_GMAC_SPEED_SHIFT = 0x2, 133 PX30_GMAC_SPEED_MASK = BIT(2), 134 PX30_GMAC_SPEED_10M = 0, 135 PX30_GMAC_SPEED_100M = BIT(2), 136 }; 137 138 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 139 &clk_speed); 140 if (ret) 141 return ret; 142 143 switch (priv->phydev->speed) { 144 case 10: 145 speed = PX30_GMAC_SPEED_10M; 146 ret = clk_set_rate(&clk_speed, 2500000); 147 if (ret) 148 return ret; 149 break; 150 case 100: 151 speed = PX30_GMAC_SPEED_100M; 152 ret = clk_set_rate(&clk_speed, 25000000); 153 if (ret) 154 return ret; 155 break; 156 default: 157 debug("Unknown phy speed: %d\n", priv->phydev->speed); 158 return -EINVAL; 159 } 160 161 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 162 rk_clrsetreg(&grf->mac_con1, PX30_GMAC_SPEED_MASK, speed); 163 164 return 0; 165 } 166 167 static int rk1808_gmac_fix_mac_speed(struct rockchip_eth_dev *dev) 168 { 169 struct dw_eth_dev *priv = &dev->dw; 170 struct clk clk_speed; 171 int ret; 172 173 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 174 &clk_speed); 175 if (ret) 176 return ret; 177 178 switch (priv->phydev->speed) { 179 case 10: 180 ret = clk_set_rate(&clk_speed, 2500000); 181 if (ret) 182 return ret; 183 break; 184 case 100: 185 ret = clk_set_rate(&clk_speed, 25000000); 186 if (ret) 187 return ret; 188 break; 189 case 1000: 190 ret = clk_set_rate(&clk_speed, 125000000); 191 if (ret) 192 return ret; 193 break; 194 default: 195 debug("Unknown phy speed: %d\n", priv->phydev->speed); 196 return -EINVAL; 197 } 198 199 return 0; 200 } 201 202 static int rk3228_gmac_fix_mac_speed(struct rockchip_eth_dev *dev) 203 { 204 struct dw_eth_dev *priv = &dev->dw; 205 struct rk322x_grf *grf; 206 int clk; 207 enum { 208 RK3228_GMAC_CLK_SEL_SHIFT = 8, 209 RK3228_GMAC_CLK_SEL_MASK = GENMASK(9, 8), 210 RK3228_GMAC_CLK_SEL_125M = 0 << 8, 211 RK3228_GMAC_CLK_SEL_25M = 3 << 8, 212 RK3228_GMAC_CLK_SEL_2_5M = 2 << 8, 213 }; 214 215 switch (priv->phydev->speed) { 216 case 10: 217 clk = RK3228_GMAC_CLK_SEL_2_5M; 218 break; 219 case 100: 220 clk = RK3228_GMAC_CLK_SEL_25M; 221 break; 222 case 1000: 223 clk = RK3228_GMAC_CLK_SEL_125M; 224 break; 225 default: 226 debug("Unknown phy speed: %d\n", priv->phydev->speed); 227 return -EINVAL; 228 } 229 230 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 231 rk_clrsetreg(&grf->mac_con[1], RK3228_GMAC_CLK_SEL_MASK, clk); 232 233 return 0; 234 } 235 236 static int rk3288_gmac_fix_mac_speed(struct rockchip_eth_dev *dev) 237 { 238 struct dw_eth_dev *priv = &dev->dw; 239 struct rk3288_grf *grf; 240 int clk; 241 242 switch (priv->phydev->speed) { 243 case 10: 244 clk = RK3288_GMAC_CLK_SEL_2_5M; 245 break; 246 case 100: 247 clk = RK3288_GMAC_CLK_SEL_25M; 248 break; 249 case 1000: 250 clk = RK3288_GMAC_CLK_SEL_125M; 251 break; 252 default: 253 debug("Unknown phy speed: %d\n", priv->phydev->speed); 254 return -EINVAL; 255 } 256 257 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 258 rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk); 259 260 return 0; 261 } 262 263 static int rk3308_gmac_fix_mac_speed(struct rockchip_eth_dev *dev) 264 { 265 struct dw_eth_dev *priv = &dev->dw; 266 struct rk3308_grf *grf; 267 struct clk clk_speed; 268 int speed, ret; 269 enum { 270 RK3308_GMAC_SPEED_SHIFT = 0x0, 271 RK3308_GMAC_SPEED_MASK = BIT(0), 272 RK3308_GMAC_SPEED_10M = 0, 273 RK3308_GMAC_SPEED_100M = BIT(0), 274 }; 275 276 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 277 &clk_speed); 278 if (ret) 279 return ret; 280 281 switch (priv->phydev->speed) { 282 case 10: 283 speed = RK3308_GMAC_SPEED_10M; 284 ret = clk_set_rate(&clk_speed, 2500000); 285 if (ret) 286 return ret; 287 break; 288 case 100: 289 speed = RK3308_GMAC_SPEED_100M; 290 ret = clk_set_rate(&clk_speed, 25000000); 291 if (ret) 292 return ret; 293 break; 294 default: 295 debug("Unknown phy speed: %d\n", priv->phydev->speed); 296 return -EINVAL; 297 } 298 299 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 300 rk_clrsetreg(&grf->mac_con0, RK3308_GMAC_SPEED_MASK, speed); 301 302 return 0; 303 } 304 305 static int rk3328_gmac_fix_mac_speed(struct rockchip_eth_dev *dev) 306 { 307 struct dw_eth_dev *priv = &dev->dw; 308 struct rk3328_grf_regs *grf; 309 int clk; 310 enum { 311 RK3328_GMAC_CLK_SEL_SHIFT = 11, 312 RK3328_GMAC_CLK_SEL_MASK = GENMASK(12, 11), 313 RK3328_GMAC_CLK_SEL_125M = 0 << 11, 314 RK3328_GMAC_CLK_SEL_25M = 3 << 11, 315 RK3328_GMAC_CLK_SEL_2_5M = 2 << 11, 316 }; 317 318 switch (priv->phydev->speed) { 319 case 10: 320 clk = RK3328_GMAC_CLK_SEL_2_5M; 321 break; 322 case 100: 323 clk = RK3328_GMAC_CLK_SEL_25M; 324 break; 325 case 1000: 326 clk = RK3328_GMAC_CLK_SEL_125M; 327 break; 328 default: 329 debug("Unknown phy speed: %d\n", priv->phydev->speed); 330 return -EINVAL; 331 } 332 333 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 334 rk_clrsetreg(&grf->mac_con[1], RK3328_GMAC_CLK_SEL_MASK, clk); 335 336 return 0; 337 } 338 339 static int rk3368_gmac_fix_mac_speed(struct rockchip_eth_dev *dev) 340 { 341 struct dw_eth_dev *priv = &dev->dw; 342 struct rk3368_grf *grf; 343 int clk; 344 enum { 345 RK3368_GMAC_CLK_SEL_2_5M = 2 << 4, 346 RK3368_GMAC_CLK_SEL_25M = 3 << 4, 347 RK3368_GMAC_CLK_SEL_125M = 0 << 4, 348 RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4), 349 }; 350 351 switch (priv->phydev->speed) { 352 case 10: 353 clk = RK3368_GMAC_CLK_SEL_2_5M; 354 break; 355 case 100: 356 clk = RK3368_GMAC_CLK_SEL_25M; 357 break; 358 case 1000: 359 clk = RK3368_GMAC_CLK_SEL_125M; 360 break; 361 default: 362 debug("Unknown phy speed: %d\n", priv->phydev->speed); 363 return -EINVAL; 364 } 365 366 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 367 rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk); 368 369 return 0; 370 } 371 372 static int rk3399_gmac_fix_mac_speed(struct rockchip_eth_dev *dev) 373 { 374 struct dw_eth_dev *priv = &dev->dw; 375 struct rk3399_grf_regs *grf; 376 int clk; 377 378 switch (priv->phydev->speed) { 379 case 10: 380 clk = RK3399_GMAC_CLK_SEL_2_5M; 381 break; 382 case 100: 383 clk = RK3399_GMAC_CLK_SEL_25M; 384 break; 385 case 1000: 386 clk = RK3399_GMAC_CLK_SEL_125M; 387 break; 388 default: 389 debug("Unknown phy speed: %d\n", priv->phydev->speed); 390 return -EINVAL; 391 } 392 393 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 394 rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk); 395 396 return 0; 397 } 398 399 static int rv1108_set_rmii_speed(struct rockchip_eth_dev *dev) 400 { 401 struct dw_eth_dev *priv = &dev->dw; 402 struct rv1108_grf *grf; 403 int clk, speed; 404 enum { 405 RV1108_GMAC_SPEED_MASK = BIT(2), 406 RV1108_GMAC_SPEED_10M = 0 << 2, 407 RV1108_GMAC_SPEED_100M = 1 << 2, 408 RV1108_GMAC_CLK_SEL_MASK = BIT(7), 409 RV1108_GMAC_CLK_SEL_2_5M = 0 << 7, 410 RV1108_GMAC_CLK_SEL_25M = 1 << 7, 411 }; 412 413 switch (priv->phydev->speed) { 414 case 10: 415 clk = RV1108_GMAC_CLK_SEL_2_5M; 416 speed = RV1108_GMAC_SPEED_10M; 417 break; 418 case 100: 419 clk = RV1108_GMAC_CLK_SEL_25M; 420 speed = RV1108_GMAC_SPEED_100M; 421 break; 422 default: 423 debug("Unknown phy speed: %d\n", priv->phydev->speed); 424 return -EINVAL; 425 } 426 427 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 428 rk_clrsetreg(&grf->gmac_con0, 429 RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK, 430 clk | speed); 431 432 return 0; 433 } 434 #else 435 static int rv1126_set_rgmii_speed(struct rockchip_eth_dev *dev) 436 { 437 struct eqos_priv *priv = &dev->eqos; 438 struct clk clk_speed; 439 int ret; 440 441 ret = clk_get_by_name(priv->phy->dev, "clk_mac_speed", 442 &clk_speed); 443 if (ret) { 444 printf("%s can't get clk_mac_speed clock (ret=%d):\n", 445 __func__, ret); 446 return ret; 447 } 448 449 switch ( priv->phy->speed) { 450 case 10: 451 ret = clk_set_rate(&clk_speed, 2500000); 452 if (ret) 453 return ret; 454 break; 455 case 100: 456 ret = clk_set_rate(&clk_speed, 25000000); 457 if (ret) 458 return ret; 459 break; 460 case 1000: 461 ret = clk_set_rate(&clk_speed, 125000000); 462 if (ret) 463 return ret; 464 break; 465 default: 466 debug("Unknown phy speed: %d\n", priv->phy->speed); 467 return -EINVAL; 468 } 469 470 return 0; 471 } 472 #endif 473 474 #ifndef CONFIG_DWC_ETH_QOS 475 static void px30_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 476 { 477 struct px30_grf *grf; 478 enum { 479 px30_GMAC_PHY_INTF_SEL_SHIFT = 4, 480 px30_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 6), 481 px30_GMAC_PHY_INTF_SEL_RMII = BIT(6), 482 }; 483 484 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 485 486 rk_clrsetreg(&grf->mac_con1, 487 px30_GMAC_PHY_INTF_SEL_MASK, 488 px30_GMAC_PHY_INTF_SEL_RMII); 489 } 490 491 static void rk1808_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 492 { 493 struct rk1808_grf *grf; 494 enum { 495 RK1808_GMAC_PHY_INTF_SEL_SHIFT = 4, 496 RK1808_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 497 RK1808_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 498 499 RK1808_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 500 RK1808_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 501 RK1808_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 502 503 RK1808_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 504 RK1808_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 505 RK1808_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 506 }; 507 enum { 508 RK1808_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 509 RK1808_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 7), 510 511 RK1808_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 512 RK1808_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 513 }; 514 515 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 516 rk_clrsetreg(&grf->mac_con1, 517 RK1808_GMAC_PHY_INTF_SEL_MASK | 518 RK1808_RXCLK_DLY_ENA_GMAC_MASK | 519 RK1808_TXCLK_DLY_ENA_GMAC_MASK, 520 RK1808_GMAC_PHY_INTF_SEL_RGMII | 521 RK1808_RXCLK_DLY_ENA_GMAC_ENABLE | 522 RK1808_TXCLK_DLY_ENA_GMAC_ENABLE); 523 524 rk_clrsetreg(&grf->mac_con0, 525 RK1808_CLK_RX_DL_CFG_GMAC_MASK | 526 RK1808_CLK_TX_DL_CFG_GMAC_MASK, 527 pdata->rx_delay << RK1808_CLK_RX_DL_CFG_GMAC_SHIFT | 528 pdata->tx_delay << RK1808_CLK_TX_DL_CFG_GMAC_SHIFT); 529 } 530 531 static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 532 { 533 struct rk322x_grf *grf; 534 enum { 535 RK3228_RMII_MODE_SHIFT = 10, 536 RK3228_RMII_MODE_MASK = BIT(10), 537 538 RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4, 539 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 540 RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 541 542 RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 543 RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 544 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 545 546 RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 547 RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 548 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 549 }; 550 enum { 551 RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 552 RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 553 554 RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 555 RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 556 }; 557 558 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 559 rk_clrsetreg(&grf->mac_con[1], 560 RK3228_RMII_MODE_MASK | 561 RK3228_GMAC_PHY_INTF_SEL_MASK | 562 RK3228_RXCLK_DLY_ENA_GMAC_MASK | 563 RK3228_TXCLK_DLY_ENA_GMAC_MASK, 564 RK3228_GMAC_PHY_INTF_SEL_RGMII | 565 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE | 566 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE); 567 568 rk_clrsetreg(&grf->mac_con[0], 569 RK3228_CLK_RX_DL_CFG_GMAC_MASK | 570 RK3228_CLK_TX_DL_CFG_GMAC_MASK, 571 pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT | 572 pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT); 573 } 574 575 static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 576 { 577 struct rk3288_grf *grf; 578 579 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 580 rk_clrsetreg(&grf->soc_con1, 581 RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK, 582 RK3288_GMAC_PHY_INTF_SEL_RGMII); 583 584 rk_clrsetreg(&grf->soc_con3, 585 RK3288_RXCLK_DLY_ENA_GMAC_MASK | 586 RK3288_TXCLK_DLY_ENA_GMAC_MASK | 587 RK3288_CLK_RX_DL_CFG_GMAC_MASK | 588 RK3288_CLK_TX_DL_CFG_GMAC_MASK, 589 RK3288_RXCLK_DLY_ENA_GMAC_ENABLE | 590 RK3288_TXCLK_DLY_ENA_GMAC_ENABLE | 591 pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT | 592 pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT); 593 } 594 595 static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 596 { 597 struct rk3308_grf *grf; 598 enum { 599 RK3308_GMAC_PHY_INTF_SEL_SHIFT = 2, 600 RK3308_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 2), 601 RK3308_GMAC_PHY_INTF_SEL_RMII = BIT(4), 602 }; 603 604 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 605 606 rk_clrsetreg(&grf->mac_con0, 607 RK3308_GMAC_PHY_INTF_SEL_MASK, 608 RK3308_GMAC_PHY_INTF_SEL_RMII); 609 } 610 611 static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 612 { 613 struct rk3328_grf_regs *grf; 614 enum { 615 RK3328_RMII_MODE_SHIFT = 9, 616 RK3328_RMII_MODE_MASK = BIT(9), 617 618 RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4, 619 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 620 RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 621 622 RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 623 RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 624 RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 625 626 RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 627 RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 628 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 629 }; 630 enum { 631 RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 632 RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 633 634 RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 635 RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 636 }; 637 638 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 639 rk_clrsetreg(&grf->mac_con[1], 640 RK3328_RMII_MODE_MASK | 641 RK3328_GMAC_PHY_INTF_SEL_MASK | 642 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 643 RK3328_TXCLK_DLY_ENA_GMAC_MASK, 644 RK3328_GMAC_PHY_INTF_SEL_RGMII | 645 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 646 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE); 647 648 rk_clrsetreg(&grf->mac_con[0], 649 RK3328_CLK_RX_DL_CFG_GMAC_MASK | 650 RK3328_CLK_TX_DL_CFG_GMAC_MASK, 651 pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT | 652 pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT); 653 } 654 655 static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 656 { 657 struct rk3368_grf *grf; 658 enum { 659 RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9, 660 RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9), 661 RK3368_RMII_MODE_MASK = BIT(6), 662 RK3368_RMII_MODE = BIT(6), 663 }; 664 enum { 665 RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15), 666 RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 667 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15), 668 RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7), 669 RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 670 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7), 671 RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8, 672 RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 673 RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0, 674 RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 675 }; 676 677 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 678 rk_clrsetreg(&grf->soc_con15, 679 RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK, 680 RK3368_GMAC_PHY_INTF_SEL_RGMII); 681 682 rk_clrsetreg(&grf->soc_con16, 683 RK3368_RXCLK_DLY_ENA_GMAC_MASK | 684 RK3368_TXCLK_DLY_ENA_GMAC_MASK | 685 RK3368_CLK_RX_DL_CFG_GMAC_MASK | 686 RK3368_CLK_TX_DL_CFG_GMAC_MASK, 687 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE | 688 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE | 689 pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT | 690 pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT); 691 } 692 693 static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 694 { 695 struct rk3399_grf_regs *grf; 696 697 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 698 699 rk_clrsetreg(&grf->soc_con5, 700 RK3399_GMAC_PHY_INTF_SEL_MASK, 701 RK3399_GMAC_PHY_INTF_SEL_RGMII); 702 703 rk_clrsetreg(&grf->soc_con6, 704 RK3399_RXCLK_DLY_ENA_GMAC_MASK | 705 RK3399_TXCLK_DLY_ENA_GMAC_MASK | 706 RK3399_CLK_RX_DL_CFG_GMAC_MASK | 707 RK3399_CLK_TX_DL_CFG_GMAC_MASK, 708 RK3399_RXCLK_DLY_ENA_GMAC_ENABLE | 709 RK3399_TXCLK_DLY_ENA_GMAC_ENABLE | 710 pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT | 711 pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT); 712 } 713 714 static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 715 { 716 struct rv1108_grf *grf; 717 718 enum { 719 RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 720 RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4, 721 }; 722 723 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 724 rk_clrsetreg(&grf->gmac_con0, 725 RV1108_GMAC_PHY_INTF_SEL_MASK, 726 RV1108_GMAC_PHY_INTF_SEL_RMII); 727 } 728 #else 729 static void rk3568_set_to_rmii(struct gmac_rockchip_platdata *pdata) 730 { 731 struct rk3568_grf *grf; 732 void *con1; 733 734 enum { 735 RK3568_GMAC_PHY_INTF_SEL_SHIFT = 4, 736 RK3568_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 737 RK3568_GMAC_PHY_INTF_SEL_RMII = BIT(6), 738 }; 739 740 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 741 742 if (pdata->bus_id == 1) 743 con1 = &grf->mac1_con1; 744 else 745 con1 = &grf->mac0_con1; 746 747 rk_clrsetreg(con1, 748 RK3568_GMAC_PHY_INTF_SEL_MASK, 749 RK3568_GMAC_PHY_INTF_SEL_RMII); 750 } 751 752 static void rk3568_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 753 { 754 struct rk3568_grf *grf; 755 void *con0, *con1; 756 757 enum { 758 RK3568_GMAC_PHY_INTF_SEL_SHIFT = 4, 759 RK3568_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 760 RK3568_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 761 762 RK3568_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 763 RK3568_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 764 RK3568_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 765 766 RK3568_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 767 RK3568_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 768 RK3568_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 769 }; 770 771 enum { 772 RK3568_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 773 RK3568_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 8), 774 775 RK3568_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 776 RK3568_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 777 }; 778 779 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 780 781 if (pdata->bus_id == 1) { 782 con0 = &grf->mac1_con0; 783 con1 = &grf->mac1_con1; 784 } else { 785 con0 = &grf->mac0_con0; 786 con1 = &grf->mac0_con1; 787 } 788 789 rk_clrsetreg(con0, 790 RK3568_CLK_RX_DL_CFG_GMAC_MASK | 791 RK3568_CLK_TX_DL_CFG_GMAC_MASK, 792 pdata->rx_delay << RK3568_CLK_RX_DL_CFG_GMAC_SHIFT | 793 pdata->tx_delay << RK3568_CLK_TX_DL_CFG_GMAC_SHIFT); 794 795 rk_clrsetreg(con1, 796 RK3568_TXCLK_DLY_ENA_GMAC_MASK | 797 RK3568_RXCLK_DLY_ENA_GMAC_MASK | 798 RK3568_GMAC_PHY_INTF_SEL_MASK, 799 RK3568_TXCLK_DLY_ENA_GMAC_ENABLE | 800 RK3568_RXCLK_DLY_ENA_GMAC_ENABLE | 801 RK3568_GMAC_PHY_INTF_SEL_RGMII); 802 } 803 804 static void rv1126_set_to_rmii(struct gmac_rockchip_platdata *pdata) 805 { 806 struct rv1126_grf *grf; 807 808 enum { 809 RV1126_GMAC_PHY_INTF_SEL_SHIFT = 4, 810 RV1126_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 811 RV1126_GMAC_PHY_INTF_SEL_RMII = BIT(6), 812 }; 813 814 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 815 816 rk_clrsetreg(&grf->mac_con0, 817 RV1126_GMAC_PHY_INTF_SEL_MASK, 818 RV1126_GMAC_PHY_INTF_SEL_RMII); 819 } 820 821 static void rv1126_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 822 { 823 struct rv1126_grf *grf; 824 825 enum { 826 RV1126_GMAC_PHY_INTF_SEL_SHIFT = 4, 827 RV1126_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 828 RV1126_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 829 830 RV1126_RXCLK_M1_DLY_ENA_GMAC_MASK = BIT(3), 831 RV1126_RXCLK_M1_DLY_ENA_GMAC_DISABLE = 0, 832 RV1126_RXCLK_M1_DLY_ENA_GMAC_ENABLE = BIT(3), 833 834 RV1126_TXCLK_M1_DLY_ENA_GMAC_MASK = BIT(2), 835 RV1126_TXCLK_M1_DLY_ENA_GMAC_DISABLE = 0, 836 RV1126_TXCLK_M1_DLY_ENA_GMAC_ENABLE = BIT(2), 837 838 RV1126_RXCLK_M0_DLY_ENA_GMAC_MASK = BIT(1), 839 RV1126_RXCLK_M0_DLY_ENA_GMAC_DISABLE = 0, 840 RV1126_RXCLK_M0_DLY_ENA_GMAC_ENABLE = BIT(1), 841 842 RV1126_TXCLK_M0_DLY_ENA_GMAC_MASK = BIT(0), 843 RV1126_TXCLK_M0_DLY_ENA_GMAC_DISABLE = 0, 844 RV1126_TXCLK_M0_DLY_ENA_GMAC_ENABLE = BIT(0), 845 }; 846 enum { 847 RV1126_M0_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 848 RV1126_M0_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 849 850 RV1126_M0_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 851 RV1126_M0_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 852 }; 853 enum { 854 RV1126_M1_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 855 RV1126_M1_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 856 857 RV1126_M1_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 858 RV1126_M1_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 859 }; 860 861 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 862 863 rk_clrsetreg(&grf->mac_con0, 864 RV1126_TXCLK_M0_DLY_ENA_GMAC_MASK | 865 RV1126_RXCLK_M0_DLY_ENA_GMAC_MASK | 866 RV1126_TXCLK_M1_DLY_ENA_GMAC_MASK | 867 RV1126_RXCLK_M1_DLY_ENA_GMAC_MASK | 868 RV1126_GMAC_PHY_INTF_SEL_MASK, 869 RV1126_TXCLK_M0_DLY_ENA_GMAC_ENABLE | 870 RV1126_RXCLK_M0_DLY_ENA_GMAC_ENABLE | 871 RV1126_TXCLK_M1_DLY_ENA_GMAC_ENABLE | 872 RV1126_RXCLK_M1_DLY_ENA_GMAC_ENABLE | 873 RV1126_GMAC_PHY_INTF_SEL_RGMII); 874 875 rk_clrsetreg(&grf->mac_con1, 876 RV1126_M0_CLK_RX_DL_CFG_GMAC_MASK | 877 RV1126_M0_CLK_TX_DL_CFG_GMAC_MASK, 878 pdata->rx_delay << RV1126_M0_CLK_RX_DL_CFG_GMAC_SHIFT | 879 pdata->tx_delay << RV1126_M0_CLK_TX_DL_CFG_GMAC_SHIFT); 880 881 rk_clrsetreg(&grf->mac_con2, 882 RV1126_M1_CLK_RX_DL_CFG_GMAC_MASK | 883 RV1126_M1_CLK_TX_DL_CFG_GMAC_MASK, 884 pdata->rx_delay << RV1126_M1_CLK_RX_DL_CFG_GMAC_SHIFT | 885 pdata->tx_delay << RV1126_M1_CLK_TX_DL_CFG_GMAC_SHIFT); 886 } 887 #endif 888 889 static int gmac_rockchip_probe(struct udevice *dev) 890 { 891 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 892 struct rk_gmac_ops *ops = 893 (struct rk_gmac_ops *)dev_get_driver_data(dev); 894 #ifdef CONFIG_DWC_ETH_QOS 895 struct eqos_config *config; 896 #else 897 struct dw_eth_pdata *dw_pdata; 898 #endif 899 struct eth_pdata *eth_pdata; 900 struct clk clk; 901 ulong rate; 902 int ret; 903 904 #ifdef CONFIG_DWC_ETH_QOS 905 eth_pdata = &pdata->eth_pdata; 906 config = (struct eqos_config *)&ops->config; 907 memcpy(config, &eqos_rockchip_config, sizeof(struct eqos_config)); 908 eth_pdata->phy_interface = config->ops->eqos_get_interface(dev); 909 #else 910 dw_pdata = &pdata->dw_eth_pdata; 911 eth_pdata = &dw_pdata->eth_pdata; 912 #endif 913 pdata->bus_id = dev->seq; 914 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 915 ret = clk_set_defaults(dev); 916 if (ret) 917 debug("%s clk_set_defaults failed %d\n", __func__, ret); 918 919 ret = clk_get_by_index(dev, 0, &clk); 920 if (ret) 921 return ret; 922 923 switch (eth_pdata->phy_interface) { 924 case PHY_INTERFACE_MODE_RGMII: 925 /* 926 * If the gmac clock is from internal pll, need to set and 927 * check the return value for gmac clock at RGMII mode. If 928 * the gmac clock is from external source, the clock rate 929 * is not set, because of it is bypassed. 930 */ 931 if (!pdata->clock_input) { 932 rate = clk_set_rate(&clk, 125000000); 933 if (rate != 125000000) 934 return -EINVAL; 935 } 936 937 /* Set to RGMII mode */ 938 if (ops->set_to_rgmii) 939 ops->set_to_rgmii(pdata); 940 else 941 return -EPERM; 942 943 break; 944 case PHY_INTERFACE_MODE_RMII: 945 /* The commet is the same as RGMII mode */ 946 if (!pdata->clock_input) { 947 rate = clk_set_rate(&clk, 50000000); 948 if (rate != 50000000) 949 return -EINVAL; 950 } 951 952 /* Set to RMII mode */ 953 if (ops->set_to_rmii) 954 ops->set_to_rmii(pdata); 955 else 956 return -EPERM; 957 958 break; 959 default: 960 debug("NO interface defined!\n"); 961 return -ENXIO; 962 } 963 964 #ifdef CONFIG_DWC_ETH_QOS 965 return eqos_probe(dev); 966 #else 967 return designware_eth_probe(dev); 968 #endif 969 } 970 971 static int gmac_rockchip_eth_write_hwaddr(struct udevice *dev) 972 { 973 #if defined(CONFIG_DWC_ETH_QOS) 974 return eqos_write_hwaddr(dev); 975 #else 976 return designware_eth_write_hwaddr(dev); 977 #endif 978 } 979 980 static int gmac_rockchip_eth_free_pkt(struct udevice *dev, uchar *packet, 981 int length) 982 { 983 #ifdef CONFIG_DWC_ETH_QOS 984 return eqos_free_pkt(dev, packet, length); 985 #else 986 return designware_eth_free_pkt(dev, packet, length); 987 #endif 988 } 989 990 static int gmac_rockchip_eth_send(struct udevice *dev, void *packet, 991 int length) 992 { 993 #ifdef CONFIG_DWC_ETH_QOS 994 return eqos_send(dev, packet, length); 995 #else 996 return designware_eth_send(dev, packet, length); 997 #endif 998 } 999 1000 static int gmac_rockchip_eth_recv(struct udevice *dev, int flags, 1001 uchar **packetp) 1002 { 1003 #ifdef CONFIG_DWC_ETH_QOS 1004 return eqos_recv(dev, flags, packetp); 1005 #else 1006 return designware_eth_recv(dev, flags, packetp); 1007 #endif 1008 } 1009 1010 static int gmac_rockchip_eth_start(struct udevice *dev) 1011 { 1012 struct rockchip_eth_dev *priv = dev_get_priv(dev); 1013 struct rk_gmac_ops *ops = 1014 (struct rk_gmac_ops *)dev_get_driver_data(dev); 1015 #ifndef CONFIG_DWC_ETH_QOS 1016 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 1017 struct dw_eth_pdata *dw_pdata; 1018 struct eth_pdata *eth_pdata; 1019 #endif 1020 int ret; 1021 1022 #ifdef CONFIG_DWC_ETH_QOS 1023 ret = eqos_init(dev); 1024 #else 1025 dw_pdata = &pdata->dw_eth_pdata; 1026 eth_pdata = &dw_pdata->eth_pdata; 1027 ret = designware_eth_init((struct dw_eth_dev *)priv, 1028 eth_pdata->enetaddr); 1029 #endif 1030 if (ret) 1031 return ret; 1032 ret = ops->fix_mac_speed(priv); 1033 if (ret) 1034 return ret; 1035 1036 #ifdef CONFIG_DWC_ETH_QOS 1037 eqos_enable(dev); 1038 #else 1039 ret = designware_eth_enable((struct dw_eth_dev *)priv); 1040 if (ret) 1041 return ret; 1042 #endif 1043 1044 return 0; 1045 } 1046 1047 static void gmac_rockchip_eth_stop(struct udevice *dev) 1048 { 1049 #ifdef CONFIG_DWC_ETH_QOS 1050 eqos_stop(dev); 1051 #else 1052 designware_eth_stop(dev); 1053 #endif 1054 } 1055 1056 const struct eth_ops gmac_rockchip_eth_ops = { 1057 .start = gmac_rockchip_eth_start, 1058 .send = gmac_rockchip_eth_send, 1059 .recv = gmac_rockchip_eth_recv, 1060 .free_pkt = gmac_rockchip_eth_free_pkt, 1061 .stop = gmac_rockchip_eth_stop, 1062 .write_hwaddr = gmac_rockchip_eth_write_hwaddr, 1063 }; 1064 1065 #ifndef CONFIG_DWC_ETH_QOS 1066 const struct rk_gmac_ops px30_gmac_ops = { 1067 .fix_mac_speed = px30_gmac_fix_mac_speed, 1068 .set_to_rmii = px30_gmac_set_to_rmii, 1069 }; 1070 1071 const struct rk_gmac_ops rk1808_gmac_ops = { 1072 .fix_mac_speed = rk1808_gmac_fix_mac_speed, 1073 .set_to_rgmii = rk1808_gmac_set_to_rgmii, 1074 }; 1075 1076 const struct rk_gmac_ops rk3228_gmac_ops = { 1077 .fix_mac_speed = rk3228_gmac_fix_mac_speed, 1078 .set_to_rgmii = rk3228_gmac_set_to_rgmii, 1079 }; 1080 1081 const struct rk_gmac_ops rk3288_gmac_ops = { 1082 .fix_mac_speed = rk3288_gmac_fix_mac_speed, 1083 .set_to_rgmii = rk3288_gmac_set_to_rgmii, 1084 }; 1085 1086 const struct rk_gmac_ops rk3308_gmac_ops = { 1087 .fix_mac_speed = rk3308_gmac_fix_mac_speed, 1088 .set_to_rmii = rk3308_gmac_set_to_rmii, 1089 }; 1090 1091 const struct rk_gmac_ops rk3328_gmac_ops = { 1092 .fix_mac_speed = rk3328_gmac_fix_mac_speed, 1093 .set_to_rgmii = rk3328_gmac_set_to_rgmii, 1094 }; 1095 1096 const struct rk_gmac_ops rk3368_gmac_ops = { 1097 .fix_mac_speed = rk3368_gmac_fix_mac_speed, 1098 .set_to_rgmii = rk3368_gmac_set_to_rgmii, 1099 }; 1100 1101 const struct rk_gmac_ops rk3399_gmac_ops = { 1102 .fix_mac_speed = rk3399_gmac_fix_mac_speed, 1103 .set_to_rgmii = rk3399_gmac_set_to_rgmii, 1104 }; 1105 1106 const struct rk_gmac_ops rv1108_gmac_ops = { 1107 .fix_mac_speed = rv1108_set_rmii_speed, 1108 .set_to_rmii = rv1108_gmac_set_to_rmii, 1109 }; 1110 #else 1111 const struct rk_gmac_ops rk3568_gmac_ops = { 1112 .fix_mac_speed = rv1126_set_rgmii_speed, 1113 .set_to_rgmii = rk3568_set_to_rgmii, 1114 .set_to_rmii = rk3568_set_to_rmii, 1115 }; 1116 1117 const struct rk_gmac_ops rv1126_gmac_ops = { 1118 .fix_mac_speed = rv1126_set_rgmii_speed, 1119 .set_to_rgmii = rv1126_set_to_rgmii, 1120 .set_to_rmii = rv1126_set_to_rmii, 1121 }; 1122 #endif 1123 1124 static const struct udevice_id rockchip_gmac_ids[] = { 1125 #ifndef CONFIG_DWC_ETH_QOS 1126 { .compatible = "rockchip,px30-gmac", 1127 .data = (ulong)&px30_gmac_ops }, 1128 { .compatible = "rockchip,rk1808-gmac", 1129 .data = (ulong)&rk1808_gmac_ops }, 1130 { .compatible = "rockchip,rk3228-gmac", 1131 .data = (ulong)&rk3228_gmac_ops }, 1132 { .compatible = "rockchip,rk3288-gmac", 1133 .data = (ulong)&rk3288_gmac_ops }, 1134 { .compatible = "rockchip,rk3308-mac", 1135 .data = (ulong)&rk3308_gmac_ops }, 1136 { .compatible = "rockchip,rk3328-gmac", 1137 .data = (ulong)&rk3328_gmac_ops }, 1138 { .compatible = "rockchip,rk3368-gmac", 1139 .data = (ulong)&rk3368_gmac_ops }, 1140 { .compatible = "rockchip,rk3399-gmac", 1141 .data = (ulong)&rk3399_gmac_ops }, 1142 { .compatible = "rockchip,rv1108-gmac", 1143 .data = (ulong)&rv1108_gmac_ops }, 1144 #else 1145 { .compatible = "rockchip,rk3568-gmac", 1146 .data = (ulong)&rk3568_gmac_ops }, 1147 { .compatible = "rockchip,rv1126-gmac", 1148 .data = (ulong)&rv1126_gmac_ops }, 1149 #endif 1150 { } 1151 }; 1152 1153 U_BOOT_DRIVER(eth_gmac_rockchip) = { 1154 .name = "gmac_rockchip", 1155 .id = UCLASS_ETH, 1156 .of_match = rockchip_gmac_ids, 1157 .ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata, 1158 .probe = gmac_rockchip_probe, 1159 .ops = &gmac_rockchip_eth_ops, 1160 .priv_auto_alloc_size = sizeof(struct rockchip_eth_dev), 1161 .platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata), 1162 .flags = DM_FLAG_ALLOC_PRIV_DMA, 1163 }; 1164