1 /* 2 * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Rockchip GMAC ethernet IP driver for U-Boot 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <clk.h> 12 #include <misc.h> 13 #include <phy.h> 14 #include <reset.h> 15 #include <syscon.h> 16 #include <asm/io.h> 17 #include <asm/arch/periph.h> 18 #include <asm/arch/clock.h> 19 #include <asm/arch/hardware.h> 20 #ifdef CONFIG_DWC_ETH_QOS 21 #include <asm/arch/grf_rk3528.h> 22 #include <asm/arch/grf_rk3562.h> 23 #include <asm/arch/ioc_rk3562.h> 24 #include <asm/arch/grf_rk3568.h> 25 #include <asm/arch/grf_rk3588.h> 26 #include <asm/arch/grf_rv1103b.h> 27 #include <asm/arch/grf_rv1106.h> 28 #include <asm/arch/grf_rv1126.h> 29 #include "dwc_eth_qos.h" 30 #else 31 #include <asm/arch/grf_px30.h> 32 #include <asm/arch/grf_rk1808.h> 33 #include <asm/arch/grf_rk322x.h> 34 #include <asm/arch/grf_rk3288.h> 35 #include <asm/arch/grf_rk3308.h> 36 #include <asm/arch/grf_rk3328.h> 37 #include <asm/arch/grf_rk3368.h> 38 #include <asm/arch/grf_rk3399.h> 39 #include <asm/arch/grf_rv1108.h> 40 #include "designware.h" 41 #include <dt-bindings/clock/rk3288-cru.h> 42 #endif 43 #include <dm/pinctrl.h> 44 #include <dm/of_access.h> 45 46 DECLARE_GLOBAL_DATA_PTR; 47 48 struct rockchip_eth_dev { 49 #ifdef CONFIG_DWC_ETH_QOS 50 struct eqos_priv eqos; 51 #else 52 struct dw_eth_dev dw; 53 #endif 54 int phy_interface; 55 }; 56 57 /* 58 * Platform data for the gmac 59 * 60 * dw_eth_pdata: Required platform data for designware driver (must be first) 61 */ 62 struct gmac_rockchip_platdata { 63 #ifndef CONFIG_DWC_ETH_QOS 64 struct dw_eth_pdata dw_eth_pdata; 65 #else 66 struct eth_pdata eth_pdata; 67 #endif 68 struct reset_ctl phy_reset; 69 bool integrated_phy; 70 bool clock_input; 71 int phy_interface; 72 int tx_delay; 73 int rx_delay; 74 int bus_id; 75 }; 76 77 struct rk_gmac_ops { 78 #ifdef CONFIG_DWC_ETH_QOS 79 const struct eqos_config config; 80 #endif 81 int (*fix_mac_speed)(struct gmac_rockchip_platdata *pdata, 82 struct rockchip_eth_dev *dev); 83 void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata); 84 void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata); 85 void (*set_clock_selection)(struct gmac_rockchip_platdata *pdata); 86 void (*integrated_phy_powerup)(struct gmac_rockchip_platdata *pdata); 87 }; 88 89 #ifdef CONFIG_DWC_ETH_QOS 90 static const struct eqos_config eqos_rockchip_config = { 91 .reg_access_always_ok = false, 92 .mdio_wait = 10000, 93 .swr_wait = 200, 94 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED, 95 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_100_150, 96 .ops = &eqos_rockchip_ops, 97 }; 98 #endif 99 100 void gmac_set_rgmii(struct udevice *dev, u32 tx_delay, u32 rx_delay) 101 { 102 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 103 struct rk_gmac_ops *ops = 104 (struct rk_gmac_ops *)dev_get_driver_data(dev); 105 106 pdata->tx_delay = tx_delay; 107 pdata->rx_delay = rx_delay; 108 109 ops->set_to_rgmii(pdata); 110 } 111 112 static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) 113 { 114 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 115 struct ofnode_phandle_args args; 116 struct udevice *phydev; 117 const char *string; 118 int ret; 119 120 string = dev_read_string(dev, "clock_in_out"); 121 if (!strcmp(string, "input")) 122 pdata->clock_input = true; 123 else 124 pdata->clock_input = false; 125 126 /* If phy-handle property is passed from DT, use it as the PHY */ 127 ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &args); 128 if (ret) { 129 debug("Cannot get phy phandle: ret=%d\n", ret); 130 pdata->integrated_phy = dev_read_bool(dev, "phy-is-integrated"); 131 } else { 132 debug("Found phy-handle subnode\n"); 133 pdata->integrated_phy = ofnode_read_bool(args.node, 134 "phy-is-integrated"); 135 } 136 137 if (pdata->integrated_phy) { 138 ret = reset_get_by_name(dev, "mac-phy", &pdata->phy_reset); 139 if (ret) { 140 ret = uclass_get_device_by_ofnode(UCLASS_ETH_PHY, args.node, &phydev); 141 if (ret) { 142 debug("Get phydev by ofnode failed: err=%d\n", ret); 143 return ret; 144 } 145 146 ret = reset_get_by_index(phydev, 0, &pdata->phy_reset); 147 if (ret) { 148 debug("No PHY reset control found: ret=%d\n", ret); 149 return ret; 150 } 151 } 152 } 153 154 /* Check the new naming-style first... */ 155 pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT); 156 pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT); 157 158 /* ... and fall back to the old naming style or default, if necessary */ 159 if (pdata->tx_delay == -ENOENT) 160 pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30); 161 if (pdata->rx_delay == -ENOENT) 162 pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10); 163 164 #ifdef CONFIG_DWC_ETH_QOS 165 return 0; 166 #else 167 return designware_eth_ofdata_to_platdata(dev); 168 #endif 169 } 170 171 #ifndef CONFIG_DWC_ETH_QOS 172 static int px30_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 173 struct rockchip_eth_dev *dev) 174 { 175 struct dw_eth_dev *priv = &dev->dw; 176 struct px30_grf *grf; 177 struct clk clk_speed; 178 int speed, ret; 179 enum { 180 PX30_GMAC_SPEED_SHIFT = 0x2, 181 PX30_GMAC_SPEED_MASK = BIT(2), 182 PX30_GMAC_SPEED_10M = 0, 183 PX30_GMAC_SPEED_100M = BIT(2), 184 }; 185 186 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 187 &clk_speed); 188 if (ret) 189 return ret; 190 191 switch (priv->phydev->speed) { 192 case 10: 193 speed = PX30_GMAC_SPEED_10M; 194 ret = clk_set_rate(&clk_speed, 2500000); 195 if (ret) 196 return ret; 197 break; 198 case 100: 199 speed = PX30_GMAC_SPEED_100M; 200 ret = clk_set_rate(&clk_speed, 25000000); 201 if (ret) 202 return ret; 203 break; 204 default: 205 debug("Unknown phy speed: %d\n", priv->phydev->speed); 206 return -EINVAL; 207 } 208 209 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 210 rk_clrsetreg(&grf->mac_con1, PX30_GMAC_SPEED_MASK, speed); 211 212 return 0; 213 } 214 215 static int rk1808_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 216 struct rockchip_eth_dev *dev) 217 { 218 struct dw_eth_dev *priv = &dev->dw; 219 struct clk clk_speed; 220 int ret; 221 222 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 223 &clk_speed); 224 if (ret) 225 return ret; 226 227 switch (priv->phydev->speed) { 228 case 10: 229 ret = clk_set_rate(&clk_speed, 2500000); 230 if (ret) 231 return ret; 232 break; 233 case 100: 234 ret = clk_set_rate(&clk_speed, 25000000); 235 if (ret) 236 return ret; 237 break; 238 case 1000: 239 ret = clk_set_rate(&clk_speed, 125000000); 240 if (ret) 241 return ret; 242 break; 243 default: 244 debug("Unknown phy speed: %d\n", priv->phydev->speed); 245 return -EINVAL; 246 } 247 248 return 0; 249 } 250 251 static int rk3228_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 252 struct rockchip_eth_dev *dev) 253 { 254 struct dw_eth_dev *priv = &dev->dw; 255 struct rk322x_grf *grf; 256 int clk; 257 enum { 258 RK3228_GMAC_CLK_SEL_SHIFT = 8, 259 RK3228_GMAC_CLK_SEL_MASK = GENMASK(9, 8), 260 RK3228_GMAC_CLK_SEL_125M = 0 << 8, 261 RK3228_GMAC_CLK_SEL_25M = 3 << 8, 262 RK3228_GMAC_CLK_SEL_2_5M = 2 << 8, 263 264 RK3228_GMAC_RMII_CLK_MASK = BIT(7), 265 RK3228_GMAC_RMII_CLK_2_5M = 0, 266 RK3228_GMAC_RMII_CLK_25M = BIT(7), 267 268 RK3228_GMAC_RMII_SPEED_MASK = BIT(2), 269 RK3228_GMAC_RMII_SPEED_10 = 0, 270 RK3228_GMAC_RMII_SPEED_100 = BIT(2), 271 }; 272 273 switch (priv->phydev->speed) { 274 case 10: 275 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 276 (RK3228_GMAC_RMII_CLK_2_5M | RK3228_GMAC_RMII_SPEED_10) : 277 RK3228_GMAC_CLK_SEL_2_5M; 278 break; 279 case 100: 280 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 281 (RK3228_GMAC_RMII_CLK_25M | RK3228_GMAC_RMII_SPEED_100) : 282 RK3228_GMAC_CLK_SEL_25M; 283 break; 284 case 1000: 285 clk = RK3228_GMAC_CLK_SEL_125M; 286 break; 287 default: 288 debug("Unknown phy speed: %d\n", priv->phydev->speed); 289 return -EINVAL; 290 } 291 292 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 293 rk_clrsetreg(&grf->mac_con[1], 294 RK3228_GMAC_CLK_SEL_MASK | 295 RK3228_GMAC_RMII_CLK_MASK | 296 RK3228_GMAC_RMII_SPEED_MASK, 297 clk); 298 299 return 0; 300 } 301 302 static int rk3288_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 303 struct rockchip_eth_dev *dev) 304 { 305 struct dw_eth_dev *priv = &dev->dw; 306 struct rk3288_grf *grf; 307 int clk; 308 309 switch (priv->phydev->speed) { 310 case 10: 311 clk = RK3288_GMAC_CLK_SEL_2_5M; 312 break; 313 case 100: 314 clk = RK3288_GMAC_CLK_SEL_25M; 315 break; 316 case 1000: 317 clk = RK3288_GMAC_CLK_SEL_125M; 318 break; 319 default: 320 debug("Unknown phy speed: %d\n", priv->phydev->speed); 321 return -EINVAL; 322 } 323 324 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 325 rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk); 326 327 return 0; 328 } 329 330 static int rk3308_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 331 struct rockchip_eth_dev *dev) 332 { 333 struct dw_eth_dev *priv = &dev->dw; 334 struct rk3308_grf *grf; 335 struct clk clk_speed; 336 int speed, ret; 337 enum { 338 RK3308_GMAC_SPEED_SHIFT = 0x0, 339 RK3308_GMAC_SPEED_MASK = BIT(0), 340 RK3308_GMAC_SPEED_10M = 0, 341 RK3308_GMAC_SPEED_100M = BIT(0), 342 }; 343 344 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 345 &clk_speed); 346 if (ret) 347 return ret; 348 349 switch (priv->phydev->speed) { 350 case 10: 351 speed = RK3308_GMAC_SPEED_10M; 352 ret = clk_set_rate(&clk_speed, 2500000); 353 if (ret) 354 return ret; 355 break; 356 case 100: 357 speed = RK3308_GMAC_SPEED_100M; 358 ret = clk_set_rate(&clk_speed, 25000000); 359 if (ret) 360 return ret; 361 break; 362 default: 363 debug("Unknown phy speed: %d\n", priv->phydev->speed); 364 return -EINVAL; 365 } 366 367 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 368 rk_clrsetreg(&grf->mac_con0, RK3308_GMAC_SPEED_MASK, speed); 369 370 return 0; 371 } 372 373 static int rk3328_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 374 struct rockchip_eth_dev *dev) 375 { 376 struct dw_eth_dev *priv = &dev->dw; 377 struct rk3328_grf_regs *grf; 378 int clk; 379 enum { 380 RK3328_GMAC_CLK_SEL_SHIFT = 11, 381 RK3328_GMAC_CLK_SEL_MASK = GENMASK(12, 11), 382 RK3328_GMAC_CLK_SEL_125M = 0 << 11, 383 RK3328_GMAC_CLK_SEL_25M = 3 << 11, 384 RK3328_GMAC_CLK_SEL_2_5M = 2 << 11, 385 386 RK3328_GMAC_RMII_CLK_MASK = BIT(7), 387 RK3328_GMAC_RMII_CLK_2_5M = 0, 388 RK3328_GMAC_RMII_CLK_25M = BIT(7), 389 390 RK3328_GMAC_RMII_SPEED_MASK = BIT(2), 391 RK3328_GMAC_RMII_SPEED_10 = 0, 392 RK3328_GMAC_RMII_SPEED_100 = BIT(2), 393 }; 394 395 switch (priv->phydev->speed) { 396 case 10: 397 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 398 (RK3328_GMAC_RMII_CLK_2_5M | RK3328_GMAC_RMII_SPEED_10) : 399 RK3328_GMAC_CLK_SEL_2_5M; 400 break; 401 case 100: 402 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 403 (RK3328_GMAC_RMII_CLK_25M | RK3328_GMAC_RMII_SPEED_100) : 404 RK3328_GMAC_CLK_SEL_25M; 405 break; 406 case 1000: 407 clk = RK3328_GMAC_CLK_SEL_125M; 408 break; 409 default: 410 debug("Unknown phy speed: %d\n", priv->phydev->speed); 411 return -EINVAL; 412 } 413 414 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 415 rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1], 416 RK3328_GMAC_CLK_SEL_MASK | 417 RK3328_GMAC_RMII_CLK_MASK | 418 RK3328_GMAC_RMII_SPEED_MASK, 419 clk); 420 421 return 0; 422 } 423 424 static int rk3368_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 425 struct rockchip_eth_dev *dev) 426 { 427 struct dw_eth_dev *priv = &dev->dw; 428 struct rk3368_grf *grf; 429 int clk; 430 enum { 431 RK3368_GMAC_CLK_SEL_2_5M = 2 << 4, 432 RK3368_GMAC_CLK_SEL_25M = 3 << 4, 433 RK3368_GMAC_CLK_SEL_125M = 0 << 4, 434 RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4), 435 }; 436 437 switch (priv->phydev->speed) { 438 case 10: 439 clk = RK3368_GMAC_CLK_SEL_2_5M; 440 break; 441 case 100: 442 clk = RK3368_GMAC_CLK_SEL_25M; 443 break; 444 case 1000: 445 clk = RK3368_GMAC_CLK_SEL_125M; 446 break; 447 default: 448 debug("Unknown phy speed: %d\n", priv->phydev->speed); 449 return -EINVAL; 450 } 451 452 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 453 rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk); 454 455 return 0; 456 } 457 458 static int rk3399_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 459 struct rockchip_eth_dev *dev) 460 { 461 struct dw_eth_dev *priv = &dev->dw; 462 struct rk3399_grf_regs *grf; 463 int clk; 464 465 switch (priv->phydev->speed) { 466 case 10: 467 clk = RK3399_GMAC_CLK_SEL_2_5M; 468 break; 469 case 100: 470 clk = RK3399_GMAC_CLK_SEL_25M; 471 break; 472 case 1000: 473 clk = RK3399_GMAC_CLK_SEL_125M; 474 break; 475 default: 476 debug("Unknown phy speed: %d\n", priv->phydev->speed); 477 return -EINVAL; 478 } 479 480 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 481 rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk); 482 483 return 0; 484 } 485 486 static int rv1108_set_rmii_speed(struct gmac_rockchip_platdata *pdata, 487 struct rockchip_eth_dev *dev) 488 { 489 struct dw_eth_dev *priv = &dev->dw; 490 struct rv1108_grf *grf; 491 int clk, speed; 492 enum { 493 RV1108_GMAC_SPEED_MASK = BIT(2), 494 RV1108_GMAC_SPEED_10M = 0 << 2, 495 RV1108_GMAC_SPEED_100M = 1 << 2, 496 RV1108_GMAC_CLK_SEL_MASK = BIT(7), 497 RV1108_GMAC_CLK_SEL_2_5M = 0 << 7, 498 RV1108_GMAC_CLK_SEL_25M = 1 << 7, 499 }; 500 501 switch (priv->phydev->speed) { 502 case 10: 503 clk = RV1108_GMAC_CLK_SEL_2_5M; 504 speed = RV1108_GMAC_SPEED_10M; 505 break; 506 case 100: 507 clk = RV1108_GMAC_CLK_SEL_25M; 508 speed = RV1108_GMAC_SPEED_100M; 509 break; 510 default: 511 debug("Unknown phy speed: %d\n", priv->phydev->speed); 512 return -EINVAL; 513 } 514 515 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 516 rk_clrsetreg(&grf->gmac_con0, 517 RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK, 518 clk | speed); 519 520 return 0; 521 } 522 #else 523 static int rk3528_set_rgmii_speed(struct gmac_rockchip_platdata *pdata, 524 struct rockchip_eth_dev *dev) 525 { 526 struct eqos_priv *priv = &dev->eqos; 527 struct rk3528_grf *grf; 528 unsigned int div; 529 530 enum { 531 RK3528_GMAC0_CLK_RMII_DIV_SHIFT = 3, 532 RK3528_GMAC0_CLK_RMII_DIV_MASK = GENMASK(4, 3), 533 RK3528_GMAC0_CLK_RMII_DIV2 = BIT(3), 534 RK3528_GMAC0_CLK_RMII_DIV20 = 0, 535 }; 536 537 enum { 538 RK3528_GMAC1_CLK_RGMII_DIV_SHIFT = 10, 539 RK3528_GMAC1_CLK_RGMII_DIV_MASK = GENMASK(11, 10), 540 RK3528_GMAC1_CLK_RGMII_DIV1 = 0, 541 RK3528_GMAC1_CLK_RGMII_DIV5 = GENMASK(11, 10), 542 RK3528_GMAC1_CLK_RGMII_DIV50 = BIT(11), 543 RK3528_GMAC1_CLK_RMII_DIV2 = BIT(11), 544 RK3528_GMAC1_CLK_RMII_DIV20 = 0, 545 }; 546 547 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 548 549 switch (priv->phy->speed) { 550 case 10: 551 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) 552 div = pdata->bus_id ? RK3528_GMAC1_CLK_RMII_DIV20 : 553 RK3528_GMAC0_CLK_RMII_DIV20; 554 else 555 div = RK3528_GMAC1_CLK_RGMII_DIV50; 556 break; 557 case 100: 558 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) 559 div = pdata->bus_id ? RK3528_GMAC1_CLK_RMII_DIV2 : 560 RK3528_GMAC0_CLK_RMII_DIV2; 561 else 562 div = RK3528_GMAC1_CLK_RGMII_DIV5; 563 break; 564 case 1000: 565 if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII) 566 div = RK3528_GMAC1_CLK_RGMII_DIV1; 567 else 568 return -EINVAL; 569 break; 570 default: 571 debug("Unknown phy speed: %d\n", priv->phy->speed); 572 return -EINVAL; 573 } 574 575 if (pdata->bus_id) 576 rk_clrsetreg(&grf->gmac1_con0, RK3528_GMAC1_CLK_RGMII_DIV_MASK, div); 577 else 578 rk_clrsetreg(&grf->gmac0_con, RK3528_GMAC0_CLK_RMII_DIV_MASK, div); 579 580 return 0; 581 } 582 583 static int rk3562_set_gmac_speed(struct gmac_rockchip_platdata *pdata, 584 struct rockchip_eth_dev *dev) 585 { 586 struct eqos_priv *priv = &dev->eqos; 587 struct rk3562_grf *grf; 588 unsigned int div; 589 590 enum { 591 RK3562_GMAC0_CLK_RGMII_DIV_SHIFT = 7, 592 RK3562_GMAC0_CLK_RGMII_DIV_MASK = GENMASK(8, 7), 593 RK3562_GMAC0_CLK_RGMII_DIV1 = 0, 594 RK3562_GMAC0_CLK_RGMII_DIV5 = GENMASK(8, 7), 595 RK3562_GMAC0_CLK_RGMII_DIV50 = BIT(8), 596 RK3562_GMAC0_CLK_RMII_DIV2 = BIT(7), 597 RK3562_GMAC0_CLK_RMII_DIV20 = 0, 598 }; 599 600 enum { 601 RK3562_GMAC1_SPEED_SHIFT = 0x0, 602 RK3562_GMAC1_SPEED_MASK = BIT(0), 603 RK3562_GMAC1_SPEED_10M = 0, 604 RK3562_GMAC1_SPEED_100M = BIT(0), 605 }; 606 607 enum { 608 RK3562_GMAC1_CLK_RMII_DIV_SHIFT = 13, 609 RK3562_GMAC1_CLK_RMII_DIV_MASK = BIT(13), 610 RK3562_GMAC1_CLK_RMII_DIV2 = BIT(13), 611 RK3562_GMAC1_CLK_RMII_DIV20 = 0, 612 }; 613 614 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 615 616 switch (priv->phy->speed) { 617 case 10: 618 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) { 619 if (pdata->bus_id > 0) { 620 div = RK3562_GMAC1_CLK_RMII_DIV20; 621 rk_clrsetreg(&grf->soc_con[0], 622 RK3562_GMAC1_SPEED_MASK, 623 RK3562_GMAC1_SPEED_10M); 624 } else { 625 div = RK3562_GMAC0_CLK_RMII_DIV20; 626 } 627 } else { 628 div = RK3562_GMAC0_CLK_RGMII_DIV50; 629 } 630 break; 631 case 100: 632 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) { 633 if (pdata->bus_id > 0) { 634 div = RK3562_GMAC1_CLK_RMII_DIV2; 635 rk_clrsetreg(&grf->soc_con[0], 636 RK3562_GMAC1_SPEED_MASK, 637 RK3562_GMAC1_SPEED_100M); 638 } else { 639 div = RK3562_GMAC0_CLK_RMII_DIV2; 640 } 641 } else { 642 div = RK3562_GMAC0_CLK_RGMII_DIV5; 643 } 644 break; 645 case 1000: 646 if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII) 647 div = RK3562_GMAC0_CLK_RGMII_DIV1; 648 else 649 return -EINVAL; 650 break; 651 default: 652 debug("Unknown phy speed: %d\n", priv->phy->speed); 653 return -EINVAL; 654 } 655 656 if (pdata->bus_id) 657 rk_clrsetreg(&grf->soc_con[1], RK3562_GMAC1_CLK_RMII_DIV_MASK, div); 658 else 659 rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_CLK_RGMII_DIV_MASK, div); 660 661 return 0; 662 } 663 664 static int rk3588_set_rgmii_speed(struct gmac_rockchip_platdata *pdata, 665 struct rockchip_eth_dev *dev) 666 { 667 struct eqos_priv *priv = &dev->eqos; 668 struct rk3588_php_grf *php_grf; 669 unsigned int div, div_mask; 670 671 enum { 672 RK3588_GMAC_CLK_RGMII_DIV_SHIFT = 2, 673 RK3588_GMAC_CLK_RGMII_DIV_MASK = GENMASK(3, 2), 674 RK3588_GMAC_CLK_RGMII_DIV1 = 0, 675 RK3588_GMAC_CLK_RGMII_DIV5 = GENMASK(3, 2), 676 RK3588_GMAC_CLK_RGMII_DIV50 = BIT(3), 677 RK3588_GMAC_CLK_RMII_DIV2 = BIT(2), 678 RK3588_GMAC_CLK_RMII_DIV20 = 0, 679 RK3588_GMAC1_ID_SHIFT = 5, 680 }; 681 682 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 683 684 switch (priv->phy->speed) { 685 case 10: 686 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) 687 div = RK3588_GMAC_CLK_RMII_DIV20; 688 else 689 div = RK3588_GMAC_CLK_RGMII_DIV50; 690 break; 691 case 100: 692 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) 693 div = RK3588_GMAC_CLK_RMII_DIV2; 694 else 695 div = RK3588_GMAC_CLK_RGMII_DIV5; 696 break; 697 case 1000: 698 if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII) 699 div = RK3588_GMAC_CLK_RGMII_DIV1; 700 else 701 return -EINVAL; 702 break; 703 default: 704 debug("Unknown phy speed: %d\n", priv->phy->speed); 705 return -EINVAL; 706 } 707 708 if (pdata->bus_id == 1) { 709 div <<= 5; 710 div_mask = RK3588_GMAC_CLK_RGMII_DIV_MASK << 5; 711 } 712 713 div <<= pdata->bus_id ? RK3588_GMAC1_ID_SHIFT : 0; 714 div_mask = pdata->bus_id ? (RK3588_GMAC_CLK_RGMII_DIV_MASK << 5) : 715 RK3588_GMAC_CLK_RGMII_DIV_MASK; 716 717 rk_clrsetreg(&php_grf->clk_con1, div_mask, div); 718 719 return 0; 720 } 721 722 static int rv1106_set_rmii_speed(struct gmac_rockchip_platdata *pdata, 723 struct rockchip_eth_dev *dev) 724 { 725 struct eqos_priv *priv = &dev->eqos; 726 #ifdef CONFIG_ROCKCHIP_RV1103B 727 struct rv1103b_grf *grf; 728 #else 729 struct rv1106_grf *grf; 730 #endif 731 unsigned int div; 732 733 enum { 734 RV1106_GMAC_CLK_RMII_DIV_SHIFT = 2, 735 RV1106_GMAC_CLK_RMII_DIV_MASK = GENMASK(3, 2), 736 RV1106_GMAC_CLK_RMII_DIV2 = BIT(2), 737 RV1106_GMAC_CLK_RMII_DIV20 = 0, 738 }; 739 740 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 741 742 switch (priv->phy->speed) { 743 case 10: 744 div = RV1106_GMAC_CLK_RMII_DIV20; 745 break; 746 case 100: 747 div = RV1106_GMAC_CLK_RMII_DIV2; 748 break; 749 default: 750 debug("Unknown phy speed: %d\n", priv->phy->speed); 751 return -EINVAL; 752 } 753 754 rk_clrsetreg(&grf->gmac_clk_con, RV1106_GMAC_CLK_RMII_DIV_MASK, div); 755 756 return 0; 757 } 758 759 static int rv1126_set_rgmii_speed(struct gmac_rockchip_platdata *pdata, 760 struct rockchip_eth_dev *dev) 761 { 762 struct eqos_priv *priv = &dev->eqos; 763 struct clk clk_speed; 764 int ret; 765 766 ret = clk_get_by_name(priv->phy->dev, "clk_mac_speed", 767 &clk_speed); 768 if (ret) { 769 printf("%s can't get clk_mac_speed clock (ret=%d):\n", 770 __func__, ret); 771 return ret; 772 } 773 774 switch ( priv->phy->speed) { 775 case 10: 776 ret = clk_set_rate(&clk_speed, 2500000); 777 if (ret) 778 return ret; 779 break; 780 case 100: 781 ret = clk_set_rate(&clk_speed, 25000000); 782 if (ret) 783 return ret; 784 break; 785 case 1000: 786 ret = clk_set_rate(&clk_speed, 125000000); 787 if (ret) 788 return ret; 789 break; 790 default: 791 debug("Unknown phy speed: %d\n", priv->phy->speed); 792 return -EINVAL; 793 } 794 795 return 0; 796 } 797 #endif 798 799 #ifndef CONFIG_DWC_ETH_QOS 800 static void px30_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 801 { 802 struct px30_grf *grf; 803 enum { 804 px30_GMAC_PHY_INTF_SEL_SHIFT = 4, 805 px30_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 6), 806 px30_GMAC_PHY_INTF_SEL_RMII = BIT(6), 807 }; 808 809 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 810 811 rk_clrsetreg(&grf->mac_con1, 812 px30_GMAC_PHY_INTF_SEL_MASK, 813 px30_GMAC_PHY_INTF_SEL_RMII); 814 } 815 816 static void rk1808_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 817 { 818 struct rk1808_grf *grf; 819 enum { 820 RK1808_GMAC_PHY_INTF_SEL_SHIFT = 4, 821 RK1808_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 822 RK1808_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 823 824 RK1808_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 825 RK1808_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 826 RK1808_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 827 828 RK1808_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 829 RK1808_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 830 RK1808_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 831 }; 832 enum { 833 RK1808_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 834 RK1808_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 7), 835 836 RK1808_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 837 RK1808_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 838 }; 839 840 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 841 rk_clrsetreg(&grf->mac_con1, 842 RK1808_GMAC_PHY_INTF_SEL_MASK | 843 RK1808_RXCLK_DLY_ENA_GMAC_MASK | 844 RK1808_TXCLK_DLY_ENA_GMAC_MASK, 845 RK1808_GMAC_PHY_INTF_SEL_RGMII | 846 RK1808_RXCLK_DLY_ENA_GMAC_ENABLE | 847 RK1808_TXCLK_DLY_ENA_GMAC_ENABLE); 848 849 rk_clrsetreg(&grf->mac_con0, 850 RK1808_CLK_RX_DL_CFG_GMAC_MASK | 851 RK1808_CLK_TX_DL_CFG_GMAC_MASK, 852 (pdata->rx_delay << RK1808_CLK_RX_DL_CFG_GMAC_SHIFT) | 853 (pdata->tx_delay << RK1808_CLK_TX_DL_CFG_GMAC_SHIFT)); 854 } 855 856 static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 857 { 858 struct rk322x_grf *grf; 859 enum { 860 RK3228_RMII_MODE_SHIFT = 10, 861 RK3228_RMII_MODE_MASK = BIT(10), 862 863 RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4, 864 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 865 RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 866 867 RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 868 RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 869 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 870 871 RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 872 RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 873 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 874 }; 875 enum { 876 RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 877 RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 878 879 RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 880 RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 881 }; 882 883 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 884 rk_clrsetreg(&grf->mac_con[1], 885 RK3228_RMII_MODE_MASK | 886 RK3228_GMAC_PHY_INTF_SEL_MASK | 887 RK3228_RXCLK_DLY_ENA_GMAC_MASK | 888 RK3228_TXCLK_DLY_ENA_GMAC_MASK, 889 RK3228_GMAC_PHY_INTF_SEL_RGMII | 890 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE | 891 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE); 892 893 rk_clrsetreg(&grf->mac_con[0], 894 RK3228_CLK_RX_DL_CFG_GMAC_MASK | 895 RK3228_CLK_TX_DL_CFG_GMAC_MASK, 896 pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT | 897 pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT); 898 } 899 900 static void rk3228_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 901 { 902 struct rk322x_grf *grf; 903 enum { 904 RK3228_GRF_CON_RMII_MODE_MASK = BIT(11), 905 RK3228_GRF_CON_RMII_MODE_SEL = BIT(11), 906 RK3228_RMII_MODE_MASK = BIT(10), 907 RK3228_RMII_MODE_SEL = BIT(10), 908 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 909 RK3228_GMAC_PHY_INTF_SEL_RMII = BIT(6), 910 }; 911 912 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 913 rk_clrsetreg(&grf->mac_con[1], 914 RK3228_GRF_CON_RMII_MODE_MASK | 915 RK3228_RMII_MODE_MASK | 916 RK3228_GMAC_PHY_INTF_SEL_MASK, 917 RK3228_GRF_CON_RMII_MODE_SEL | 918 RK3228_RMII_MODE_SEL | 919 RK3228_GMAC_PHY_INTF_SEL_RMII); 920 } 921 922 static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 923 { 924 struct rk3288_grf *grf; 925 926 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 927 rk_clrsetreg(&grf->soc_con1, 928 RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK, 929 RK3288_GMAC_PHY_INTF_SEL_RGMII); 930 931 rk_clrsetreg(&grf->soc_con3, 932 RK3288_RXCLK_DLY_ENA_GMAC_MASK | 933 RK3288_TXCLK_DLY_ENA_GMAC_MASK | 934 RK3288_CLK_RX_DL_CFG_GMAC_MASK | 935 RK3288_CLK_TX_DL_CFG_GMAC_MASK, 936 RK3288_RXCLK_DLY_ENA_GMAC_ENABLE | 937 RK3288_TXCLK_DLY_ENA_GMAC_ENABLE | 938 pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT | 939 pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT); 940 } 941 942 static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 943 { 944 struct rk3308_grf *grf; 945 enum { 946 RK3308_GMAC_PHY_INTF_SEL_SHIFT = 2, 947 RK3308_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 2), 948 RK3308_GMAC_PHY_INTF_SEL_RMII = BIT(4), 949 }; 950 951 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 952 953 rk_clrsetreg(&grf->mac_con0, 954 RK3308_GMAC_PHY_INTF_SEL_MASK, 955 RK3308_GMAC_PHY_INTF_SEL_RMII); 956 } 957 958 static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 959 { 960 struct rk3328_grf_regs *grf; 961 enum { 962 RK3328_RMII_MODE_SHIFT = 9, 963 RK3328_RMII_MODE_MASK = BIT(9), 964 965 RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4, 966 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 967 RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 968 969 RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 970 RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 971 RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 972 973 RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 974 RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 975 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 976 }; 977 enum { 978 RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 979 RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 980 981 RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 982 RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 983 }; 984 985 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 986 rk_clrsetreg(&grf->mac_con[1], 987 RK3328_RMII_MODE_MASK | 988 RK3328_GMAC_PHY_INTF_SEL_MASK | 989 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 990 RK3328_TXCLK_DLY_ENA_GMAC_MASK, 991 RK3328_GMAC_PHY_INTF_SEL_RGMII | 992 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 993 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE); 994 995 rk_clrsetreg(&grf->mac_con[0], 996 RK3328_CLK_RX_DL_CFG_GMAC_MASK | 997 RK3328_CLK_TX_DL_CFG_GMAC_MASK, 998 pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT | 999 pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT); 1000 } 1001 1002 static void rk3328_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1003 { 1004 struct rk3328_grf_regs *grf; 1005 enum { 1006 RK3328_RMII_MODE_MASK = BIT(9), 1007 RK3328_RMII_MODE = BIT(9), 1008 1009 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1010 RK3328_GMAC_PHY_INTF_SEL_RMII = BIT(6), 1011 }; 1012 1013 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1014 rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1], 1015 RK3328_RMII_MODE_MASK | 1016 RK3328_GMAC_PHY_INTF_SEL_MASK, 1017 RK3328_GMAC_PHY_INTF_SEL_RMII | 1018 RK3328_RMII_MODE); 1019 } 1020 1021 static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1022 { 1023 struct rk3368_grf *grf; 1024 enum { 1025 RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9, 1026 RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9), 1027 RK3368_RMII_MODE_MASK = BIT(6), 1028 RK3368_RMII_MODE = BIT(6), 1029 }; 1030 enum { 1031 RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15), 1032 RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 1033 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15), 1034 RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7), 1035 RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 1036 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7), 1037 RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8, 1038 RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 1039 RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0, 1040 RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 1041 }; 1042 1043 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1044 rk_clrsetreg(&grf->soc_con15, 1045 RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK, 1046 RK3368_GMAC_PHY_INTF_SEL_RGMII); 1047 1048 rk_clrsetreg(&grf->soc_con16, 1049 RK3368_RXCLK_DLY_ENA_GMAC_MASK | 1050 RK3368_TXCLK_DLY_ENA_GMAC_MASK | 1051 RK3368_CLK_RX_DL_CFG_GMAC_MASK | 1052 RK3368_CLK_TX_DL_CFG_GMAC_MASK, 1053 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE | 1054 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE | 1055 (pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT) | 1056 (pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT)); 1057 } 1058 1059 static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1060 { 1061 struct rk3399_grf_regs *grf; 1062 1063 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1064 1065 rk_clrsetreg(&grf->soc_con5, 1066 RK3399_GMAC_PHY_INTF_SEL_MASK, 1067 RK3399_GMAC_PHY_INTF_SEL_RGMII); 1068 1069 rk_clrsetreg(&grf->soc_con6, 1070 RK3399_RXCLK_DLY_ENA_GMAC_MASK | 1071 RK3399_TXCLK_DLY_ENA_GMAC_MASK | 1072 RK3399_CLK_RX_DL_CFG_GMAC_MASK | 1073 RK3399_CLK_TX_DL_CFG_GMAC_MASK, 1074 RK3399_RXCLK_DLY_ENA_GMAC_ENABLE | 1075 RK3399_TXCLK_DLY_ENA_GMAC_ENABLE | 1076 (pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT) | 1077 (pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT)); 1078 } 1079 1080 static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1081 { 1082 struct rv1108_grf *grf; 1083 1084 enum { 1085 RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1086 RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4, 1087 }; 1088 1089 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1090 rk_clrsetreg(&grf->gmac_con0, 1091 RV1108_GMAC_PHY_INTF_SEL_MASK, 1092 RV1108_GMAC_PHY_INTF_SEL_RMII); 1093 } 1094 1095 static void rk3228_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 1096 { 1097 struct rk322x_grf *grf; 1098 enum { 1099 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK = BIT(15), 1100 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY = BIT(15), 1101 }; 1102 enum { 1103 RK3228_MACPHY_CFG_CLK_50M_MASK = BIT(14), 1104 RK3228_MACPHY_CFG_CLK_50M = BIT(14), 1105 1106 RK3228_MACPHY_RMII_MODE_MASK = GENMASK(7, 6), 1107 RK3228_MACPHY_RMII_MODE = BIT(6), 1108 1109 RK3228_MACPHY_ENABLE_MASK = BIT(0), 1110 RK3228_MACPHY_DISENABLE = 0, 1111 RK3228_MACPHY_ENABLE = BIT(0), 1112 }; 1113 enum { 1114 RK3228_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0), 1115 RK3228_RK_GRF_CON2_MACPHY_ID = 0x1234, 1116 }; 1117 enum { 1118 RK3228_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0), 1119 RK3228_RK_GRF_CON3_MACPHY_ID = 0x35, 1120 }; 1121 1122 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1123 rk_clrsetreg(&grf->con_iomux, 1124 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK, 1125 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY); 1126 1127 rk_clrsetreg(&grf->macphy_con[2], 1128 RK3228_RK_GRF_CON2_MACPHY_ID_MASK, 1129 RK3228_RK_GRF_CON2_MACPHY_ID); 1130 1131 rk_clrsetreg(&grf->macphy_con[3], 1132 RK3228_RK_GRF_CON3_MACPHY_ID_MASK, 1133 RK3228_RK_GRF_CON3_MACPHY_ID); 1134 1135 /* disabled before trying to reset it &*/ 1136 rk_clrsetreg(&grf->macphy_con[0], 1137 RK3228_MACPHY_CFG_CLK_50M_MASK | 1138 RK3228_MACPHY_RMII_MODE_MASK | 1139 RK3228_MACPHY_ENABLE_MASK, 1140 RK3228_MACPHY_CFG_CLK_50M | 1141 RK3228_MACPHY_RMII_MODE | 1142 RK3228_MACPHY_DISENABLE); 1143 1144 reset_assert(&pdata->phy_reset); 1145 udelay(10); 1146 reset_deassert(&pdata->phy_reset); 1147 udelay(10); 1148 1149 rk_clrsetreg(&grf->macphy_con[0], 1150 RK3228_MACPHY_ENABLE_MASK, 1151 RK3228_MACPHY_ENABLE); 1152 udelay(30 * 1000); 1153 } 1154 1155 static void rk3328_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 1156 { 1157 struct rk3328_grf_regs *grf; 1158 enum { 1159 RK3328_GRF_CON_RMII_MODE_MASK = BIT(9), 1160 RK3328_GRF_CON_RMII_MODE = BIT(9), 1161 }; 1162 enum { 1163 RK3328_MACPHY_CFG_CLK_50M_MASK = BIT(14), 1164 RK3328_MACPHY_CFG_CLK_50M = BIT(14), 1165 1166 RK3328_MACPHY_RMII_MODE_MASK = GENMASK(7, 6), 1167 RK3328_MACPHY_RMII_MODE = BIT(6), 1168 1169 RK3328_MACPHY_ENABLE_MASK = BIT(0), 1170 RK3328_MACPHY_DISENABLE = 0, 1171 RK3328_MACPHY_ENABLE = BIT(0), 1172 }; 1173 enum { 1174 RK3328_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0), 1175 RK3328_RK_GRF_CON2_MACPHY_ID = 0x1234, 1176 }; 1177 enum { 1178 RK3328_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0), 1179 RK3328_RK_GRF_CON3_MACPHY_ID = 0x35, 1180 }; 1181 1182 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1183 rk_clrsetreg(&grf->macphy_con[1], 1184 RK3328_GRF_CON_RMII_MODE_MASK, 1185 RK3328_GRF_CON_RMII_MODE); 1186 1187 rk_clrsetreg(&grf->macphy_con[2], 1188 RK3328_RK_GRF_CON2_MACPHY_ID_MASK, 1189 RK3328_RK_GRF_CON2_MACPHY_ID); 1190 1191 rk_clrsetreg(&grf->macphy_con[3], 1192 RK3328_RK_GRF_CON3_MACPHY_ID_MASK, 1193 RK3328_RK_GRF_CON3_MACPHY_ID); 1194 1195 /* disabled before trying to reset it &*/ 1196 rk_clrsetreg(&grf->macphy_con[0], 1197 RK3328_MACPHY_CFG_CLK_50M_MASK | 1198 RK3328_MACPHY_RMII_MODE_MASK | 1199 RK3328_MACPHY_ENABLE_MASK, 1200 RK3328_MACPHY_CFG_CLK_50M | 1201 RK3328_MACPHY_RMII_MODE | 1202 RK3328_MACPHY_DISENABLE); 1203 1204 reset_assert(&pdata->phy_reset); 1205 udelay(10); 1206 reset_deassert(&pdata->phy_reset); 1207 udelay(10); 1208 1209 rk_clrsetreg(&grf->macphy_con[0], 1210 RK3328_MACPHY_ENABLE_MASK, 1211 RK3328_MACPHY_ENABLE); 1212 udelay(30 * 1000); 1213 } 1214 1215 #else 1216 static void rk3528_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 1217 { 1218 struct rk3528_grf *grf; 1219 unsigned char bgs[1] = {0}; 1220 1221 enum { 1222 RK3528_MACPHY_ENABLE_MASK = BIT(1), 1223 RK3528_MACPHY_DISENABLE = BIT(1), 1224 RK3528_MACPHY_ENABLE = 0, 1225 RK3528_MACPHY_XMII_SEL_MASK = GENMASK(6, 5), 1226 RK3528_MACPHY_XMII_SEL = BIT(6), 1227 RK3528_MACPHY_24M_CLK_SEL_MASK = GENMASK(9, 7), 1228 RK3528_MACPHY_24M_CLK_SEL_24M = (BIT(8) | BIT(9)), 1229 RK3528_MACPHY_PHY_ID_MASK = GENMASK(14, 10), 1230 RK3528_MACPHY_PHY_ID = BIT(11), 1231 }; 1232 1233 enum { 1234 RK3528_MACPHY_BGS_MASK = GENMASK(3, 0), 1235 }; 1236 1237 #if defined(CONFIG_ROCKCHIP_EFUSE) || defined(CONFIG_ROCKCHIP_OTP) 1238 struct udevice *dev; 1239 u32 regs[2] = {0}; 1240 ofnode node; 1241 int ret = 0; 1242 1243 /* retrieve the device */ 1244 if (IS_ENABLED(CONFIG_ROCKCHIP_EFUSE)) 1245 ret = uclass_get_device_by_driver(UCLASS_MISC, 1246 DM_GET_DRIVER(rockchip_efuse), 1247 &dev); 1248 else 1249 ret = uclass_get_device_by_driver(UCLASS_MISC, 1250 DM_GET_DRIVER(rockchip_otp), 1251 &dev); 1252 if (!ret) { 1253 node = dev_read_subnode(dev, "macphy-bgs"); 1254 if (ofnode_valid(node)) { 1255 if (!ofnode_read_u32_array(node, "reg", regs, 2)) { 1256 /* read the bgs from the efuses */ 1257 ret = misc_read(dev, regs[0], &bgs, 1); 1258 if (ret) { 1259 printf("read bgs from efuse/otp failed, ret=%d\n", 1260 ret); 1261 bgs[0] = 0; 1262 } 1263 } 1264 } 1265 } 1266 #endif 1267 1268 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1269 1270 reset_assert(&pdata->phy_reset); 1271 udelay(20); 1272 rk_clrsetreg(&grf->macphy_con0, 1273 RK3528_MACPHY_ENABLE_MASK | 1274 RK3528_MACPHY_XMII_SEL_MASK | 1275 RK3528_MACPHY_24M_CLK_SEL_MASK | 1276 RK3528_MACPHY_PHY_ID_MASK, 1277 RK3528_MACPHY_ENABLE | 1278 RK3528_MACPHY_XMII_SEL | 1279 RK3528_MACPHY_24M_CLK_SEL_24M | 1280 RK3528_MACPHY_PHY_ID); 1281 1282 rk_clrsetreg(&grf->macphy_con1, 1283 RK3528_MACPHY_BGS_MASK, 1284 bgs[0]); 1285 udelay(20); 1286 reset_deassert(&pdata->phy_reset); 1287 udelay(30 * 1000); 1288 } 1289 1290 static void rk3528_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1291 { 1292 unsigned int clk_mode; 1293 struct rk3528_grf *grf; 1294 1295 enum { 1296 RK3528_GMAC0_CLK_RMII_MODE_SHIFT = 0x1, 1297 RK3528_GMAC0_CLK_RMII_MODE_MASK = BIT(1), 1298 RK3528_GMAC0_CLK_RMII_MODE = 0x1, 1299 }; 1300 1301 enum { 1302 RK3528_GMAC1_CLK_RMII_MODE_SHIFT = 0x8, 1303 RK3528_GMAC1_CLK_RMII_MODE_MASK = BIT(8), 1304 RK3528_GMAC1_CLK_RMII_MODE = 0x1, 1305 }; 1306 1307 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1308 1309 if (pdata->bus_id == 1) { 1310 clk_mode = RK3528_GMAC1_CLK_RMII_MODE << RK3528_GMAC1_CLK_RMII_MODE_SHIFT; 1311 rk_clrsetreg(&grf->gmac1_con1, RK3528_GMAC1_CLK_RMII_MODE_MASK, clk_mode); 1312 } else { 1313 clk_mode = RK3528_GMAC0_CLK_RMII_MODE << RK3528_GMAC0_CLK_RMII_MODE_SHIFT; 1314 rk_clrsetreg(&grf->gmac0_con, RK3528_GMAC0_CLK_RMII_MODE_MASK, clk_mode); 1315 } 1316 } 1317 1318 static void rk3528_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1319 { 1320 unsigned int rx_enable; 1321 unsigned int rx_delay; 1322 struct rk3528_grf *grf; 1323 1324 enum { 1325 RK3528_GMAC1_RGMII_MODE_SHIFT = 0x8, 1326 RK3528_GMAC1_RGMII_MODE_MASK = BIT(8), 1327 RK3528_GMAC1_RGMII_MODE = 0x0, 1328 1329 RK3528_GMAC1_TXCLK_DLY_ENA_MASK = BIT(14), 1330 RK3528_GMAC1_TXCLK_DLY_ENA_DISABLE = 0, 1331 RK3528_GMAC1_TXCLK_DLY_ENA_ENABLE = BIT(14), 1332 1333 RK3528_GMAC1_RXCLK_DLY_ENA_MASK = BIT(15), 1334 RK3528_GMAC1_RXCLK_DLY_ENA_DISABLE = 0, 1335 RK3528_GMAC1_RXCLK_DLY_ENA_ENABLE = BIT(15), 1336 }; 1337 1338 enum { 1339 RK3528_GMAC1_RX_DL_CFG_SHIFT = 0x8, 1340 RK3528_GMAC1_RX_DL_CFG_MASK = GENMASK(15, 8), 1341 1342 RK3528_GMAC1_TX_DL_CFG_SHIFT = 0x0, 1343 RK3528_GMAC1_TX_DL_CFG_MASK = GENMASK(7, 0), 1344 }; 1345 1346 if (!pdata->bus_id) 1347 return; 1348 1349 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1350 1351 if (pdata->rx_delay < 0) { 1352 rx_enable = RK3528_GMAC1_RXCLK_DLY_ENA_DISABLE; 1353 rx_delay = 0; 1354 } else { 1355 rx_enable = RK3528_GMAC1_RXCLK_DLY_ENA_ENABLE; 1356 rx_delay = pdata->rx_delay << RK3528_GMAC1_RX_DL_CFG_SHIFT; 1357 } 1358 1359 rk_clrsetreg(&grf->gmac1_con0, 1360 RK3528_GMAC1_TXCLK_DLY_ENA_MASK | 1361 RK3528_GMAC1_RXCLK_DLY_ENA_MASK | 1362 RK3528_GMAC1_RGMII_MODE_MASK, 1363 rx_enable | RK3528_GMAC1_TXCLK_DLY_ENA_ENABLE | 1364 (RK3528_GMAC1_RGMII_MODE << RK3528_GMAC1_RGMII_MODE_SHIFT)); 1365 1366 rk_clrsetreg(&grf->gmac1_con1, 1367 RK3528_GMAC1_RX_DL_CFG_MASK | 1368 RK3528_GMAC1_TX_DL_CFG_MASK, 1369 (pdata->tx_delay << RK3528_GMAC1_TX_DL_CFG_SHIFT) | 1370 rx_delay); 1371 } 1372 1373 static void rk3562_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1374 { 1375 struct rk3562_grf *grf; 1376 unsigned int mode; 1377 1378 enum { 1379 RK3562_GMAC0_RMII_MODE_SHIFT = 0x5, 1380 RK3562_GMAC0_RMII_MODE_MASK = BIT(5), 1381 RK3562_GMAC0_RMII_MODE = 0x1, 1382 }; 1383 1384 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1385 1386 if (!pdata->bus_id) { 1387 mode = RK3562_GMAC0_RMII_MODE << RK3562_GMAC0_RMII_MODE_SHIFT; 1388 rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_RMII_MODE_MASK, mode); 1389 } 1390 } 1391 1392 static void rk3562_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1393 { 1394 struct rk3562_grf *grf; 1395 struct rk3562_ioc *ioc; 1396 unsigned int rx_enable; 1397 unsigned int rx_delay; 1398 1399 enum { 1400 RK3562_GMAC0_RGMII_MODE_SHIFT = 0x5, 1401 RK3562_GMAC0_RGMII_MODE_MASK = BIT(5), 1402 RK3562_GMAC0_RGMII_MODE = 0x0, 1403 1404 RK3562_GMAC0_TXCLK_DLY_ENA_MASK = BIT(0), 1405 RK3562_GMAC0_TXCLK_DLY_ENA_DISABLE = 0, 1406 RK3562_GMAC0_TXCLK_DLY_ENA_ENABLE = BIT(0), 1407 1408 RK3562_GMAC0_RXCLK_DLY_ENA_MASK = BIT(1), 1409 RK3562_GMAC0_RXCLK_DLY_ENA_DISABLE = 0, 1410 RK3562_GMAC0_RXCLK_DLY_ENA_ENABLE = BIT(1), 1411 }; 1412 1413 enum { 1414 RK3562_GMAC0_RX_DL_CFG_SHIFT = 0x8, 1415 RK3562_GMAC0_RX_DL_CFG_MASK = GENMASK(15, 8), 1416 1417 RK3562_GMAC0_TX_DL_CFG_SHIFT = 0x0, 1418 RK3562_GMAC0_TX_DL_CFG_MASK = GENMASK(7, 0), 1419 }; 1420 1421 if (pdata->bus_id) 1422 return; 1423 1424 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1425 ioc = syscon_get_first_range(ROCKCHIP_SYSCON_IOC); 1426 1427 rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_RGMII_MODE_MASK, 1428 RK3562_GMAC0_RGMII_MODE << RK3562_GMAC0_RGMII_MODE_SHIFT); 1429 1430 if (pdata->rx_delay < 0) { 1431 rx_enable = RK3562_GMAC0_RXCLK_DLY_ENA_DISABLE; 1432 rx_delay = 0; 1433 } else { 1434 rx_enable = RK3562_GMAC0_RXCLK_DLY_ENA_ENABLE; 1435 rx_delay = pdata->rx_delay << RK3562_GMAC0_RX_DL_CFG_SHIFT; 1436 } 1437 1438 rk_clrsetreg(&ioc->mac0_io_con1, 1439 RK3562_GMAC0_TXCLK_DLY_ENA_MASK | 1440 RK3562_GMAC0_RXCLK_DLY_ENA_MASK, 1441 rx_enable | RK3562_GMAC0_TXCLK_DLY_ENA_ENABLE); 1442 1443 rk_clrsetreg(&ioc->mac0_io_con0, 1444 RK3562_GMAC0_RX_DL_CFG_MASK | 1445 RK3562_GMAC0_TX_DL_CFG_MASK, 1446 (pdata->tx_delay << RK3562_GMAC0_TX_DL_CFG_SHIFT) | 1447 rx_delay); 1448 1449 rk_clrsetreg(&ioc->mac1_io_con1, 1450 RK3562_GMAC0_TXCLK_DLY_ENA_MASK | 1451 RK3562_GMAC0_RXCLK_DLY_ENA_MASK, 1452 rx_enable | RK3562_GMAC0_TXCLK_DLY_ENA_ENABLE); 1453 1454 rk_clrsetreg(&ioc->mac1_io_con0, 1455 RK3562_GMAC0_RX_DL_CFG_MASK | 1456 RK3562_GMAC0_TX_DL_CFG_MASK, 1457 (pdata->tx_delay << RK3562_GMAC0_TX_DL_CFG_SHIFT) | 1458 rx_delay); 1459 } 1460 1461 static void rk3568_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1462 { 1463 struct rk3568_grf *grf; 1464 void *con1; 1465 1466 enum { 1467 RK3568_GMAC_PHY_INTF_SEL_SHIFT = 4, 1468 RK3568_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1469 RK3568_GMAC_PHY_INTF_SEL_RMII = BIT(6), 1470 }; 1471 1472 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1473 1474 if (pdata->bus_id == 1) 1475 con1 = &grf->mac1_con1; 1476 else 1477 con1 = &grf->mac0_con1; 1478 1479 rk_clrsetreg(con1, 1480 RK3568_GMAC_PHY_INTF_SEL_MASK, 1481 RK3568_GMAC_PHY_INTF_SEL_RMII); 1482 } 1483 1484 static void rk3568_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1485 { 1486 struct rk3568_grf *grf; 1487 void *con0, *con1; 1488 1489 enum { 1490 RK3568_GMAC_PHY_INTF_SEL_SHIFT = 4, 1491 RK3568_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1492 RK3568_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 1493 1494 RK3568_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 1495 RK3568_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 1496 RK3568_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 1497 1498 RK3568_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 1499 RK3568_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 1500 RK3568_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 1501 }; 1502 1503 enum { 1504 RK3568_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1505 RK3568_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 8), 1506 1507 RK3568_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1508 RK3568_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 1509 }; 1510 1511 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1512 1513 if (pdata->bus_id == 1) { 1514 con0 = &grf->mac1_con0; 1515 con1 = &grf->mac1_con1; 1516 } else { 1517 con0 = &grf->mac0_con0; 1518 con1 = &grf->mac0_con1; 1519 } 1520 1521 rk_clrsetreg(con0, 1522 RK3568_CLK_RX_DL_CFG_GMAC_MASK | 1523 RK3568_CLK_TX_DL_CFG_GMAC_MASK, 1524 (pdata->rx_delay << RK3568_CLK_RX_DL_CFG_GMAC_SHIFT) | 1525 (pdata->tx_delay << RK3568_CLK_TX_DL_CFG_GMAC_SHIFT)); 1526 1527 rk_clrsetreg(con1, 1528 RK3568_TXCLK_DLY_ENA_GMAC_MASK | 1529 RK3568_RXCLK_DLY_ENA_GMAC_MASK | 1530 RK3568_GMAC_PHY_INTF_SEL_MASK, 1531 RK3568_TXCLK_DLY_ENA_GMAC_ENABLE | 1532 RK3568_RXCLK_DLY_ENA_GMAC_ENABLE | 1533 RK3568_GMAC_PHY_INTF_SEL_RGMII); 1534 } 1535 1536 static void rk3588_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1537 { 1538 unsigned int intf_sel, intf_sel_mask; 1539 unsigned int clk_mode, clk_mode_mask; 1540 struct rk3588_php_grf *php_grf; 1541 1542 enum { 1543 RK3588_GMAC_PHY_INTF_SEL_SHIFT = 3, 1544 RK3588_GMAC_PHY_INTF_SEL_MASK = GENMASK(5, 3), 1545 RK3588_GMAC_PHY_INTF_SEL_RMII = BIT(5), 1546 }; 1547 1548 enum { 1549 RK3588_GMAC_CLK_RMII_MODE_SHIFT = 0x0, 1550 RK3588_GMAC_CLK_RMII_MODE_MASK = BIT(0), 1551 RK3588_GMAC_CLK_RMII_MODE = 0x1, 1552 }; 1553 1554 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 1555 1556 if (pdata->bus_id == 1) { 1557 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RMII << 6; 1558 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK << 6; 1559 clk_mode = RK3588_GMAC_CLK_RMII_MODE << 5; 1560 clk_mode_mask = RK3588_GMAC_CLK_RMII_MODE_MASK << 5; 1561 } else { 1562 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RMII; 1563 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK; 1564 clk_mode = RK3588_GMAC_CLK_RMII_MODE; 1565 clk_mode_mask = RK3588_GMAC_CLK_RMII_MODE_MASK; 1566 } 1567 1568 rk_clrsetreg(&php_grf->gmac_con0, intf_sel_mask, intf_sel); 1569 rk_clrsetreg(&php_grf->clk_con1, clk_mode_mask, clk_mode); 1570 } 1571 1572 static void rk3588_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1573 { 1574 unsigned int rx_enable, rx_enable_mask, tx_enable, tx_enable_mask; 1575 unsigned int intf_sel, intf_sel_mask; 1576 unsigned int clk_mode, clk_mode_mask; 1577 unsigned int rx_delay; 1578 struct rk3588_php_grf *php_grf; 1579 struct rk3588_sys_grf *grf; 1580 void *offset_con; 1581 1582 enum { 1583 RK3588_GMAC_PHY_INTF_SEL_SHIFT = 3, 1584 RK3588_GMAC_PHY_INTF_SEL_MASK = GENMASK(5, 3), 1585 RK3588_GMAC_PHY_INTF_SEL_RGMII = BIT(3), 1586 1587 RK3588_RXCLK_DLY_ENA_GMAC_MASK = BIT(3), 1588 RK3588_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 1589 RK3588_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(3), 1590 1591 RK3588_TXCLK_DLY_ENA_GMAC_MASK = BIT(2), 1592 RK3588_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 1593 RK3588_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(2), 1594 }; 1595 1596 enum { 1597 RK3588_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1598 RK3588_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 8), 1599 1600 RK3588_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1601 RK3588_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 1602 }; 1603 1604 enum { 1605 RK3588_GMAC_CLK_RGMII_MODE_SHIFT = 0x0, 1606 RK3588_GMAC_CLK_RGMII_MODE_MASK = BIT(0), 1607 RK3588_GMAC_CLK_RGMII_MODE = 0x0, 1608 }; 1609 1610 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1611 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 1612 1613 if (pdata->rx_delay < 0) { 1614 rx_enable = RK3588_RXCLK_DLY_ENA_GMAC_DISABLE; 1615 rx_delay = 0; 1616 } else { 1617 rx_enable = RK3588_RXCLK_DLY_ENA_GMAC_ENABLE; 1618 rx_delay = pdata->rx_delay << RK3588_CLK_RX_DL_CFG_GMAC_SHIFT; 1619 } 1620 1621 if (pdata->bus_id == 1) { 1622 offset_con = &grf->soc_con9; 1623 rx_enable = rx_delay << 2; 1624 rx_enable_mask = RK3588_RXCLK_DLY_ENA_GMAC_MASK << 2; 1625 tx_enable = RK3588_TXCLK_DLY_ENA_GMAC_ENABLE << 2; 1626 tx_enable_mask = RK3588_TXCLK_DLY_ENA_GMAC_MASK << 2; 1627 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RGMII << 6; 1628 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK << 6; 1629 clk_mode = RK3588_GMAC_CLK_RGMII_MODE << 5; 1630 clk_mode_mask = RK3588_GMAC_CLK_RGMII_MODE_MASK << 5; 1631 } else { 1632 offset_con = &grf->soc_con8; 1633 rx_enable_mask = RK3588_RXCLK_DLY_ENA_GMAC_MASK; 1634 tx_enable = RK3588_TXCLK_DLY_ENA_GMAC_ENABLE; 1635 tx_enable_mask = RK3588_TXCLK_DLY_ENA_GMAC_MASK; 1636 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RGMII; 1637 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK; 1638 clk_mode = RK3588_GMAC_CLK_RGMII_MODE; 1639 clk_mode_mask = RK3588_GMAC_CLK_RGMII_MODE_MASK; 1640 } 1641 1642 rk_clrsetreg(offset_con, 1643 RK3588_CLK_TX_DL_CFG_GMAC_MASK | 1644 RK3588_CLK_RX_DL_CFG_GMAC_MASK, 1645 (pdata->tx_delay << RK3588_CLK_TX_DL_CFG_GMAC_SHIFT) | 1646 rx_delay); 1647 1648 rk_clrsetreg(&grf->soc_con7, tx_enable_mask | rx_enable_mask, 1649 tx_enable | rx_enable); 1650 1651 rk_clrsetreg(&php_grf->gmac_con0, intf_sel_mask, intf_sel); 1652 rk_clrsetreg(&php_grf->clk_con1, clk_mode_mask, clk_mode); 1653 } 1654 1655 static void rv1103b_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1656 { 1657 struct rv1103b_grf *grf; 1658 enum { 1659 RV1103B_SYSGRF_GMAC_CLK_RMII_50M_MASK = BIT(2), 1660 RV1103B_SYSGRF_GMAC_CLK_RMII_50M = BIT(2), 1661 }; 1662 1663 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1664 rk_clrsetreg(&grf->gmac_clk_con, 1665 RV1103B_SYSGRF_GMAC_CLK_RMII_50M_MASK, 1666 RV1103B_SYSGRF_GMAC_CLK_RMII_50M); 1667 }; 1668 1669 static void rv1106_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 1670 { 1671 #ifdef CONFIG_ROCKCHIP_RV1103B 1672 struct rv1103b_grf *grf; 1673 #else 1674 struct rv1106_grf *grf; 1675 #endif 1676 unsigned char bgs[1] = {0}; 1677 1678 enum { 1679 RV1106_VOGRF_GMAC_CLK_RMII_MODE_MASK = BIT(0), 1680 RV1106_VOGRF_GMAC_CLK_RMII_MODE = BIT(0), 1681 }; 1682 1683 enum { 1684 RV1106_MACPHY_ENABLE_MASK = BIT(1), 1685 RV1106_MACPHY_DISENABLE = BIT(1), 1686 RV1106_MACPHY_ENABLE = 0, 1687 RV1106_MACPHY_XMII_SEL_MASK = GENMASK(6, 5), 1688 RV1106_MACPHY_XMII_SEL = BIT(6), 1689 RV1106_MACPHY_24M_CLK_SEL_MASK = GENMASK(9, 7), 1690 RV1106_MACPHY_24M_CLK_SEL_24M = (BIT(8) | BIT(9)), 1691 RV1106_MACPHY_PHY_ID_MASK = GENMASK(14, 10), 1692 RV1106_MACPHY_PHY_ID = BIT(11), 1693 }; 1694 1695 enum { 1696 RV1106_MACPHY_BGS_MASK = GENMASK(3, 0), 1697 RV1106_MACPHY_BGS = BIT(2), 1698 }; 1699 1700 #if defined(CONFIG_ROCKCHIP_EFUSE) || defined(CONFIG_ROCKCHIP_OTP) 1701 struct udevice *dev; 1702 u32 regs[2] = {0}; 1703 ofnode node; 1704 int ret = 0; 1705 1706 /* retrieve the device */ 1707 if (IS_ENABLED(CONFIG_ROCKCHIP_EFUSE)) 1708 ret = uclass_get_device_by_driver(UCLASS_MISC, 1709 DM_GET_DRIVER(rockchip_efuse), 1710 &dev); 1711 else 1712 ret = uclass_get_device_by_driver(UCLASS_MISC, 1713 DM_GET_DRIVER(rockchip_otp), 1714 &dev); 1715 if (!ret) { 1716 node = dev_read_subnode(dev, "macphy-bgs"); 1717 if (ofnode_valid(node)) { 1718 if (!ofnode_read_u32_array(node, "reg", regs, 2)) { 1719 /* read the bgs from the efuses */ 1720 ret = misc_read(dev, regs[0], &bgs, 1); 1721 if (ret) { 1722 printf("read bgs from efuse/otp failed, ret=%d\n", 1723 ret); 1724 bgs[0] = 0; 1725 } 1726 } 1727 } 1728 } 1729 #endif 1730 1731 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1732 1733 reset_assert(&pdata->phy_reset); 1734 udelay(20); 1735 rk_clrsetreg(&grf->macphy_con0, 1736 RV1106_MACPHY_ENABLE_MASK | 1737 RV1106_MACPHY_XMII_SEL_MASK | 1738 RV1106_MACPHY_24M_CLK_SEL_MASK | 1739 RV1106_MACPHY_PHY_ID_MASK, 1740 RV1106_MACPHY_ENABLE | 1741 RV1106_MACPHY_XMII_SEL | 1742 RV1106_MACPHY_24M_CLK_SEL_24M | 1743 RV1106_MACPHY_PHY_ID); 1744 1745 rk_clrsetreg(&grf->macphy_con1, 1746 RV1106_MACPHY_BGS_MASK, 1747 bgs[0]); 1748 udelay(20); 1749 reset_deassert(&pdata->phy_reset); 1750 udelay(30 * 1000); 1751 } 1752 1753 static void rv1106_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1754 { 1755 struct rv1106_grf *grf; 1756 enum { 1757 RV1106_VOGRF_GMAC_CLK_RMII_MODE_MASK = BIT(0), 1758 RV1106_VOGRF_GMAC_CLK_RMII_MODE = BIT(0), 1759 }; 1760 1761 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1762 rk_clrsetreg(&grf->gmac_clk_con, 1763 RV1106_VOGRF_GMAC_CLK_RMII_MODE_MASK, 1764 RV1106_VOGRF_GMAC_CLK_RMII_MODE); 1765 }; 1766 1767 static void rv1126_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1768 { 1769 struct rv1126_grf *grf; 1770 1771 enum { 1772 RV1126_GMAC_PHY_INTF_SEL_SHIFT = 4, 1773 RV1126_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1774 RV1126_GMAC_PHY_INTF_SEL_RMII = BIT(6), 1775 }; 1776 1777 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1778 1779 rk_clrsetreg(&grf->mac_con0, 1780 RV1126_GMAC_PHY_INTF_SEL_MASK, 1781 RV1126_GMAC_PHY_INTF_SEL_RMII); 1782 } 1783 1784 static void rv1126_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1785 { 1786 struct rv1126_grf *grf; 1787 1788 enum { 1789 RV1126_GMAC_PHY_INTF_SEL_SHIFT = 4, 1790 RV1126_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1791 RV1126_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 1792 1793 RV1126_RXCLK_M1_DLY_ENA_GMAC_MASK = BIT(3), 1794 RV1126_RXCLK_M1_DLY_ENA_GMAC_DISABLE = 0, 1795 RV1126_RXCLK_M1_DLY_ENA_GMAC_ENABLE = BIT(3), 1796 1797 RV1126_TXCLK_M1_DLY_ENA_GMAC_MASK = BIT(2), 1798 RV1126_TXCLK_M1_DLY_ENA_GMAC_DISABLE = 0, 1799 RV1126_TXCLK_M1_DLY_ENA_GMAC_ENABLE = BIT(2), 1800 1801 RV1126_RXCLK_M0_DLY_ENA_GMAC_MASK = BIT(1), 1802 RV1126_RXCLK_M0_DLY_ENA_GMAC_DISABLE = 0, 1803 RV1126_RXCLK_M0_DLY_ENA_GMAC_ENABLE = BIT(1), 1804 1805 RV1126_TXCLK_M0_DLY_ENA_GMAC_MASK = BIT(0), 1806 RV1126_TXCLK_M0_DLY_ENA_GMAC_DISABLE = 0, 1807 RV1126_TXCLK_M0_DLY_ENA_GMAC_ENABLE = BIT(0), 1808 }; 1809 enum { 1810 RV1126_M0_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1811 RV1126_M0_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 1812 1813 RV1126_M0_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1814 RV1126_M0_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 1815 }; 1816 enum { 1817 RV1126_M1_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1818 RV1126_M1_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 1819 1820 RV1126_M1_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1821 RV1126_M1_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 1822 }; 1823 1824 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1825 1826 rk_clrsetreg(&grf->mac_con0, 1827 RV1126_TXCLK_M0_DLY_ENA_GMAC_MASK | 1828 RV1126_RXCLK_M0_DLY_ENA_GMAC_MASK | 1829 RV1126_TXCLK_M1_DLY_ENA_GMAC_MASK | 1830 RV1126_RXCLK_M1_DLY_ENA_GMAC_MASK | 1831 RV1126_GMAC_PHY_INTF_SEL_MASK, 1832 RV1126_TXCLK_M0_DLY_ENA_GMAC_ENABLE | 1833 RV1126_RXCLK_M0_DLY_ENA_GMAC_ENABLE | 1834 RV1126_TXCLK_M1_DLY_ENA_GMAC_ENABLE | 1835 RV1126_RXCLK_M1_DLY_ENA_GMAC_ENABLE | 1836 RV1126_GMAC_PHY_INTF_SEL_RGMII); 1837 1838 rk_clrsetreg(&grf->mac_con1, 1839 RV1126_M0_CLK_RX_DL_CFG_GMAC_MASK | 1840 RV1126_M0_CLK_TX_DL_CFG_GMAC_MASK, 1841 (pdata->rx_delay << RV1126_M0_CLK_RX_DL_CFG_GMAC_SHIFT) | 1842 (pdata->tx_delay << RV1126_M0_CLK_TX_DL_CFG_GMAC_SHIFT)); 1843 1844 rk_clrsetreg(&grf->mac_con2, 1845 RV1126_M1_CLK_RX_DL_CFG_GMAC_MASK | 1846 RV1126_M1_CLK_TX_DL_CFG_GMAC_MASK, 1847 (pdata->rx_delay << RV1126_M1_CLK_RX_DL_CFG_GMAC_SHIFT) | 1848 (pdata->tx_delay << RV1126_M1_CLK_TX_DL_CFG_GMAC_SHIFT)); 1849 } 1850 #endif 1851 1852 #ifdef CONFIG_DWC_ETH_QOS 1853 static void rk3528_set_clock_selection(struct gmac_rockchip_platdata *pdata) 1854 { 1855 struct rk3528_grf *grf; 1856 unsigned int val; 1857 1858 enum { 1859 RK3528_GMAC1_CLK_SELET_SHIFT = 0x12, 1860 RK3528_GMAC1_CLK_SELET_MASK = BIT(12), 1861 RK3528_GMAC1_CLK_SELET_CRU = 0, 1862 RK3528_GMAC1_CLK_SELET_IO = BIT(12), 1863 }; 1864 1865 if (!pdata->bus_id) 1866 return; 1867 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1868 1869 val = pdata->clock_input ? RK3528_GMAC1_CLK_SELET_IO : 1870 RK3528_GMAC1_CLK_SELET_CRU; 1871 rk_clrsetreg(&grf->gmac1_con0, RK3528_GMAC1_CLK_SELET_MASK, val); 1872 } 1873 1874 static void rk3562_set_clock_selection(struct gmac_rockchip_platdata *pdata) 1875 { 1876 struct rk3562_grf *grf; 1877 struct rk3562_ioc *ioc; 1878 unsigned int val; 1879 1880 enum { 1881 RK3562_GMAC0_CLK_SELET_SHIFT = 0x9, 1882 RK3562_GMAC0_CLK_SELET_MASK = BIT(9), 1883 RK3562_GMAC0_CLK_SELET_CRU = 0, 1884 RK3562_GMAC0_CLK_SELET_IO = BIT(9), 1885 }; 1886 1887 enum { 1888 RK3562_GMAC1_CLK_SELET_SHIFT = 15, 1889 RK3562_GMAC1_CLK_SELET_MASK = BIT(15), 1890 RK3562_GMAC1_CLK_SELET_CRU = 0, 1891 RK3562_GMAC1_CLK_SELET_IO = BIT(15), 1892 }; 1893 1894 enum { 1895 RK3562_GMAC0_IO_EXTCLK_SELET_SHIFT = 0x2, 1896 RK3562_GMAC0_IO_EXTCLK_SELET_MASK = BIT(2), 1897 RK3562_GMAC0_IO_EXTCLK_SELET_CRU = 0, 1898 RK3562_GMAC0_IO_EXTCLK_SELET_IO = BIT(2), 1899 }; 1900 1901 enum { 1902 RK3562_GMAC1_IO_EXTCLK_SELET_SHIFT = 0x3, 1903 RK3562_GMAC1_IO_EXTCLK_SELET_MASK = BIT(3), 1904 RK3562_GMAC1_IO_EXTCLK_SELET_CRU = 0, 1905 RK3562_GMAC1_IO_EXTCLK_SELET_IO = BIT(3), 1906 }; 1907 1908 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1909 ioc = syscon_get_first_range(ROCKCHIP_SYSCON_IOC); 1910 1911 if (!pdata->bus_id) { 1912 val = pdata->clock_input ? RK3562_GMAC0_CLK_SELET_IO : 1913 RK3562_GMAC0_CLK_SELET_CRU; 1914 rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_CLK_SELET_MASK, val); 1915 val = pdata->clock_input ? RK3562_GMAC0_IO_EXTCLK_SELET_IO : 1916 RK3562_GMAC0_IO_EXTCLK_SELET_CRU; 1917 rk_clrsetreg(&ioc->mac1_io_con1, 1918 RK3562_GMAC0_IO_EXTCLK_SELET_MASK, val); 1919 rk_clrsetreg(&ioc->mac0_io_con1, 1920 RK3562_GMAC0_IO_EXTCLK_SELET_MASK, val); 1921 1922 } else { 1923 val = pdata->clock_input ? RK3562_GMAC1_CLK_SELET_IO : 1924 RK3562_GMAC1_CLK_SELET_CRU; 1925 rk_clrsetreg(&grf->soc_con[1], RK3562_GMAC1_CLK_SELET_MASK, val); 1926 val = pdata->clock_input ? RK3562_GMAC1_IO_EXTCLK_SELET_IO : 1927 RK3562_GMAC1_IO_EXTCLK_SELET_CRU; 1928 rk_clrsetreg(&ioc->mac1_io_con1, 1929 RK3562_GMAC1_IO_EXTCLK_SELET_MASK, val); 1930 } 1931 } 1932 1933 static void rk3588_set_clock_selection(struct gmac_rockchip_platdata *pdata) 1934 { 1935 struct rk3588_php_grf *php_grf; 1936 unsigned int val, mask; 1937 1938 enum { 1939 RK3588_GMAC_CLK_SELET_SHIFT = 0x4, 1940 RK3588_GMAC_CLK_SELET_MASK = BIT(4), 1941 RK3588_GMAC_CLK_SELET_CRU = BIT(4), 1942 RK3588_GMAC_CLK_SELET_IO = 0, 1943 }; 1944 1945 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 1946 val = pdata->clock_input ? RK3588_GMAC_CLK_SELET_IO : 1947 RK3588_GMAC_CLK_SELET_CRU; 1948 mask = RK3588_GMAC_CLK_SELET_MASK; 1949 1950 if (pdata->bus_id == 1) { 1951 val <<= 5; 1952 mask <<= 5; 1953 } 1954 1955 rk_clrsetreg(&php_grf->clk_con1, mask, val); 1956 } 1957 #endif 1958 1959 static int gmac_rockchip_probe(struct udevice *dev) 1960 { 1961 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 1962 struct rk_gmac_ops *ops = 1963 (struct rk_gmac_ops *)dev_get_driver_data(dev); 1964 #ifdef CONFIG_DWC_ETH_QOS 1965 struct eqos_config *config; 1966 #else 1967 struct dw_eth_pdata *dw_pdata; 1968 #endif 1969 struct eth_pdata *eth_pdata; 1970 struct clk clk; 1971 ulong rate; 1972 int ret; 1973 1974 #ifdef CONFIG_DWC_ETH_QOS 1975 eth_pdata = &pdata->eth_pdata; 1976 config = (struct eqos_config *)&ops->config; 1977 memcpy(config, &eqos_rockchip_config, sizeof(struct eqos_config)); 1978 eth_pdata->phy_interface = config->ops->eqos_get_interface(dev); 1979 #else 1980 dw_pdata = &pdata->dw_eth_pdata; 1981 eth_pdata = &dw_pdata->eth_pdata; 1982 #endif 1983 pdata->bus_id = dev->seq; 1984 1985 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 1986 ret = clk_set_defaults(dev); 1987 if (ret) 1988 debug("%s clk_set_defaults failed %d\n", __func__, ret); 1989 1990 ret = clk_get_by_index(dev, 0, &clk); 1991 if (ret) 1992 debug("%s clk_get_by_index failed %d\n", __func__, ret); 1993 1994 pdata->phy_interface = eth_pdata->phy_interface; 1995 1996 if (ops->set_clock_selection) 1997 ops->set_clock_selection(pdata); 1998 1999 if (pdata->integrated_phy && ops->integrated_phy_powerup) 2000 ops->integrated_phy_powerup(pdata); 2001 2002 switch (eth_pdata->phy_interface) { 2003 case PHY_INTERFACE_MODE_RGMII: 2004 case PHY_INTERFACE_MODE_RGMII_RXID: 2005 /* 2006 * If the gmac clock is from internal pll, need to set and 2007 * check the return value for gmac clock at RGMII mode. If 2008 * the gmac clock is from external source, the clock rate 2009 * is not set, because of it is bypassed. 2010 */ 2011 if (!pdata->clock_input) { 2012 if (clk.id) { 2013 rate = clk_set_rate(&clk, 125000000); 2014 if (rate != 125000000) 2015 return -EINVAL; 2016 } 2017 } 2018 2019 if (eth_pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) 2020 pdata->rx_delay = -1; 2021 2022 /* Set to RGMII mode */ 2023 if (ops->set_to_rgmii) 2024 ops->set_to_rgmii(pdata); 2025 else 2026 return -EPERM; 2027 2028 break; 2029 case PHY_INTERFACE_MODE_RMII: 2030 /* The commet is the same as RGMII mode */ 2031 if (!pdata->clock_input) { 2032 if (clk.id) { 2033 rate = clk_set_rate(&clk, 50000000); 2034 if (rate != 50000000) 2035 return -EINVAL; 2036 } 2037 } 2038 2039 /* Set to RMII mode */ 2040 if (ops->set_to_rmii) 2041 ops->set_to_rmii(pdata); 2042 2043 break; 2044 default: 2045 debug("NO interface defined!\n"); 2046 return -ENXIO; 2047 } 2048 2049 #ifdef CONFIG_DWC_ETH_QOS 2050 return eqos_probe(dev); 2051 #else 2052 return designware_eth_probe(dev); 2053 #endif 2054 } 2055 2056 static int gmac_rockchip_eth_write_hwaddr(struct udevice *dev) 2057 { 2058 #if defined(CONFIG_DWC_ETH_QOS) 2059 return eqos_write_hwaddr(dev); 2060 #else 2061 return designware_eth_write_hwaddr(dev); 2062 #endif 2063 } 2064 2065 static int gmac_rockchip_eth_free_pkt(struct udevice *dev, uchar *packet, 2066 int length) 2067 { 2068 #ifdef CONFIG_DWC_ETH_QOS 2069 return eqos_free_pkt(dev, packet, length); 2070 #else 2071 return designware_eth_free_pkt(dev, packet, length); 2072 #endif 2073 } 2074 2075 static int gmac_rockchip_eth_send(struct udevice *dev, void *packet, 2076 int length) 2077 { 2078 #ifdef CONFIG_DWC_ETH_QOS 2079 return eqos_send(dev, packet, length); 2080 #else 2081 return designware_eth_send(dev, packet, length); 2082 #endif 2083 } 2084 2085 static int gmac_rockchip_eth_recv(struct udevice *dev, int flags, 2086 uchar **packetp) 2087 { 2088 #ifdef CONFIG_DWC_ETH_QOS 2089 return eqos_recv(dev, flags, packetp); 2090 #else 2091 return designware_eth_recv(dev, flags, packetp); 2092 #endif 2093 } 2094 2095 static int gmac_rockchip_eth_start(struct udevice *dev) 2096 { 2097 struct rockchip_eth_dev *priv = dev_get_priv(dev); 2098 struct rk_gmac_ops *ops = 2099 (struct rk_gmac_ops *)dev_get_driver_data(dev); 2100 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 2101 #ifndef CONFIG_DWC_ETH_QOS 2102 struct dw_eth_pdata *dw_pdata; 2103 struct eth_pdata *eth_pdata; 2104 #endif 2105 int ret; 2106 2107 #ifdef CONFIG_DWC_ETH_QOS 2108 ret = eqos_init(dev); 2109 #else 2110 dw_pdata = &pdata->dw_eth_pdata; 2111 eth_pdata = &dw_pdata->eth_pdata; 2112 ret = designware_eth_init((struct dw_eth_dev *)priv, 2113 eth_pdata->enetaddr); 2114 #endif 2115 if (ret) 2116 return ret; 2117 ret = ops->fix_mac_speed(pdata, priv); 2118 if (ret) 2119 return ret; 2120 2121 #ifdef CONFIG_DWC_ETH_QOS 2122 eqos_enable(dev); 2123 #else 2124 ret = designware_eth_enable((struct dw_eth_dev *)priv); 2125 if (ret) 2126 return ret; 2127 #endif 2128 2129 return 0; 2130 } 2131 2132 static void gmac_rockchip_eth_stop(struct udevice *dev) 2133 { 2134 #ifdef CONFIG_DWC_ETH_QOS 2135 eqos_stop(dev); 2136 #else 2137 designware_eth_stop(dev); 2138 #endif 2139 } 2140 2141 const struct eth_ops gmac_rockchip_eth_ops = { 2142 .start = gmac_rockchip_eth_start, 2143 .send = gmac_rockchip_eth_send, 2144 .recv = gmac_rockchip_eth_recv, 2145 .free_pkt = gmac_rockchip_eth_free_pkt, 2146 .stop = gmac_rockchip_eth_stop, 2147 .write_hwaddr = gmac_rockchip_eth_write_hwaddr, 2148 }; 2149 2150 #ifndef CONFIG_DWC_ETH_QOS 2151 const struct rk_gmac_ops px30_gmac_ops = { 2152 .fix_mac_speed = px30_gmac_fix_mac_speed, 2153 .set_to_rmii = px30_gmac_set_to_rmii, 2154 }; 2155 2156 const struct rk_gmac_ops rk1808_gmac_ops = { 2157 .fix_mac_speed = rk1808_gmac_fix_mac_speed, 2158 .set_to_rgmii = rk1808_gmac_set_to_rgmii, 2159 }; 2160 2161 const struct rk_gmac_ops rk3228_gmac_ops = { 2162 .fix_mac_speed = rk3228_gmac_fix_mac_speed, 2163 .set_to_rmii = rk3228_gmac_set_to_rmii, 2164 .set_to_rgmii = rk3228_gmac_set_to_rgmii, 2165 .integrated_phy_powerup = rk3228_gmac_integrated_phy_powerup, 2166 }; 2167 2168 const struct rk_gmac_ops rk3288_gmac_ops = { 2169 .fix_mac_speed = rk3288_gmac_fix_mac_speed, 2170 .set_to_rgmii = rk3288_gmac_set_to_rgmii, 2171 }; 2172 2173 const struct rk_gmac_ops rk3308_gmac_ops = { 2174 .fix_mac_speed = rk3308_gmac_fix_mac_speed, 2175 .set_to_rmii = rk3308_gmac_set_to_rmii, 2176 }; 2177 2178 const struct rk_gmac_ops rk3328_gmac_ops = { 2179 .fix_mac_speed = rk3328_gmac_fix_mac_speed, 2180 .set_to_rmii = rk3328_gmac_set_to_rmii, 2181 .set_to_rgmii = rk3328_gmac_set_to_rgmii, 2182 .integrated_phy_powerup = rk3328_gmac_integrated_phy_powerup, 2183 }; 2184 2185 const struct rk_gmac_ops rk3368_gmac_ops = { 2186 .fix_mac_speed = rk3368_gmac_fix_mac_speed, 2187 .set_to_rgmii = rk3368_gmac_set_to_rgmii, 2188 }; 2189 2190 const struct rk_gmac_ops rk3399_gmac_ops = { 2191 .fix_mac_speed = rk3399_gmac_fix_mac_speed, 2192 .set_to_rgmii = rk3399_gmac_set_to_rgmii, 2193 }; 2194 2195 const struct rk_gmac_ops rv1108_gmac_ops = { 2196 .fix_mac_speed = rv1108_set_rmii_speed, 2197 .set_to_rmii = rv1108_gmac_set_to_rmii, 2198 }; 2199 #else 2200 const struct rk_gmac_ops rk3528_gmac_ops = { 2201 .fix_mac_speed = rk3528_set_rgmii_speed, 2202 .set_to_rgmii = rk3528_set_to_rgmii, 2203 .set_to_rmii = rk3528_set_to_rmii, 2204 .set_clock_selection = rk3528_set_clock_selection, 2205 .integrated_phy_powerup = rk3528_gmac_integrated_phy_powerup, 2206 }; 2207 2208 const struct rk_gmac_ops rk3562_gmac_ops = { 2209 .fix_mac_speed = rk3562_set_gmac_speed, 2210 .set_to_rgmii = rk3562_set_to_rgmii, 2211 .set_to_rmii = rk3562_set_to_rmii, 2212 .set_clock_selection = rk3562_set_clock_selection, 2213 }; 2214 2215 const struct rk_gmac_ops rk3568_gmac_ops = { 2216 .fix_mac_speed = rv1126_set_rgmii_speed, 2217 .set_to_rgmii = rk3568_set_to_rgmii, 2218 .set_to_rmii = rk3568_set_to_rmii, 2219 }; 2220 2221 const struct rk_gmac_ops rk3588_gmac_ops = { 2222 .fix_mac_speed = rk3588_set_rgmii_speed, 2223 .set_to_rgmii = rk3588_set_to_rgmii, 2224 .set_to_rmii = rk3588_set_to_rmii, 2225 .set_clock_selection = rk3588_set_clock_selection, 2226 }; 2227 2228 const struct rk_gmac_ops rv1103b_gmac_ops = { 2229 .fix_mac_speed = rv1106_set_rmii_speed, 2230 .set_to_rmii = rv1103b_set_to_rmii, 2231 .integrated_phy_powerup = rv1106_gmac_integrated_phy_powerup, 2232 }; 2233 2234 const struct rk_gmac_ops rv1106_gmac_ops = { 2235 .fix_mac_speed = rv1106_set_rmii_speed, 2236 .set_to_rmii = rv1106_set_to_rmii, 2237 .integrated_phy_powerup = rv1106_gmac_integrated_phy_powerup, 2238 }; 2239 2240 const struct rk_gmac_ops rv1126_gmac_ops = { 2241 .fix_mac_speed = rv1126_set_rgmii_speed, 2242 .set_to_rgmii = rv1126_set_to_rgmii, 2243 .set_to_rmii = rv1126_set_to_rmii, 2244 }; 2245 #endif 2246 2247 static const struct udevice_id rockchip_gmac_ids[] = { 2248 #ifndef CONFIG_DWC_ETH_QOS 2249 #ifdef CONFIG_ROCKCHIP_PX30 2250 { .compatible = "rockchip,px30-gmac", 2251 .data = (ulong)&px30_gmac_ops }, 2252 #endif 2253 2254 #ifdef CONFIG_ROCKCHIP_RK1808 2255 { .compatible = "rockchip,rk1808-gmac", 2256 .data = (ulong)&rk1808_gmac_ops }, 2257 #endif 2258 2259 #ifdef CONFIG_ROCKCHIP_RK3228 2260 { .compatible = "rockchip,rk3228-gmac", 2261 .data = (ulong)&rk3228_gmac_ops }, 2262 #endif 2263 2264 #ifdef CONFIG_ROCKCHIP_RK3288 2265 { .compatible = "rockchip,rk3288-gmac", 2266 .data = (ulong)&rk3288_gmac_ops }, 2267 #endif 2268 2269 #ifdef CONFIG_ROCKCHIP_RK3308 2270 { .compatible = "rockchip,rk3308-mac", 2271 .data = (ulong)&rk3308_gmac_ops }, 2272 #endif 2273 2274 #ifdef CONFIG_ROCKCHIP_RK3328 2275 { .compatible = "rockchip,rk3328-gmac", 2276 .data = (ulong)&rk3328_gmac_ops }, 2277 #endif 2278 2279 #ifdef CONFIG_ROCKCHIP_RK3368 2280 { .compatible = "rockchip,rk3368-gmac", 2281 .data = (ulong)&rk3368_gmac_ops }, 2282 #endif 2283 2284 #ifdef CONFIG_ROCKCHIP_RK3399 2285 { .compatible = "rockchip,rk3399-gmac", 2286 .data = (ulong)&rk3399_gmac_ops }, 2287 #endif 2288 2289 #ifdef CONFIG_ROCKCHIP_RV1108 2290 { .compatible = "rockchip,rv1108-gmac", 2291 .data = (ulong)&rv1108_gmac_ops }, 2292 #endif 2293 #else 2294 #ifdef CONFIG_ROCKCHIP_RK3528 2295 { .compatible = "rockchip,rk3528-gmac", 2296 .data = (ulong)&rk3528_gmac_ops }, 2297 #endif 2298 2299 #ifdef CONFIG_ROCKCHIP_RK3562 2300 { .compatible = "rockchip,rk3562-gmac", 2301 .data = (ulong)&rk3562_gmac_ops }, 2302 #endif 2303 2304 #ifdef CONFIG_ROCKCHIP_RK3568 2305 { .compatible = "rockchip,rk3568-gmac", 2306 .data = (ulong)&rk3568_gmac_ops }, 2307 #endif 2308 2309 #ifdef CONFIG_ROCKCHIP_RK3588 2310 { .compatible = "rockchip,rk3588-gmac", 2311 .data = (ulong)&rk3588_gmac_ops }, 2312 #endif 2313 2314 #ifdef CONFIG_ROCKCHIP_RV1103B 2315 { .compatible = "rockchip,rv1103b-gmac", 2316 .data = (ulong)&rv1103b_gmac_ops }, 2317 #endif 2318 2319 #ifdef CONFIG_ROCKCHIP_RV1106 2320 { .compatible = "rockchip,rv1106-gmac", 2321 .data = (ulong)&rv1106_gmac_ops }, 2322 #endif 2323 2324 #ifdef CONFIG_ROCKCHIP_RV1126 2325 { .compatible = "rockchip,rv1126-gmac", 2326 .data = (ulong)&rv1126_gmac_ops }, 2327 #endif 2328 #endif 2329 { } 2330 }; 2331 2332 U_BOOT_DRIVER(eth_gmac_rockchip) = { 2333 .name = "gmac_rockchip", 2334 .id = UCLASS_ETH, 2335 .of_match = rockchip_gmac_ids, 2336 .ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata, 2337 .probe = gmac_rockchip_probe, 2338 .ops = &gmac_rockchip_eth_ops, 2339 .priv_auto_alloc_size = sizeof(struct rockchip_eth_dev), 2340 .platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata), 2341 .flags = DM_FLAG_ALLOC_PRIV_DMA, 2342 }; 2343