1 /* 2 * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Rockchip GMAC ethernet IP driver for U-Boot 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <clk.h> 12 #include <phy.h> 13 #include <reset.h> 14 #include <syscon.h> 15 #include <asm/io.h> 16 #include <asm/arch/periph.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/hardware.h> 19 #ifdef CONFIG_DWC_ETH_QOS 20 #include <asm/arch/grf_rk3568.h> 21 #include <asm/arch/grf_rk3588.h> 22 #include <asm/arch/grf_rv1106.h> 23 #include <asm/arch/grf_rv1126.h> 24 #include "dwc_eth_qos.h" 25 #else 26 #include <asm/arch/grf_px30.h> 27 #include <asm/arch/grf_rk1808.h> 28 #include <asm/arch/grf_rk322x.h> 29 #include <asm/arch/grf_rk3288.h> 30 #include <asm/arch/grf_rk3308.h> 31 #include <asm/arch/grf_rk3328.h> 32 #include <asm/arch/grf_rk3368.h> 33 #include <asm/arch/grf_rk3399.h> 34 #include <asm/arch/grf_rv1108.h> 35 #include "designware.h" 36 #include <dt-bindings/clock/rk3288-cru.h> 37 #endif 38 #include <dm/pinctrl.h> 39 #include <dm/of_access.h> 40 41 DECLARE_GLOBAL_DATA_PTR; 42 43 struct rockchip_eth_dev { 44 #ifdef CONFIG_DWC_ETH_QOS 45 struct eqos_priv eqos; 46 #else 47 struct dw_eth_dev dw; 48 #endif 49 int phy_interface; 50 }; 51 52 /* 53 * Platform data for the gmac 54 * 55 * dw_eth_pdata: Required platform data for designware driver (must be first) 56 */ 57 struct gmac_rockchip_platdata { 58 #ifndef CONFIG_DWC_ETH_QOS 59 struct dw_eth_pdata dw_eth_pdata; 60 #else 61 struct eth_pdata eth_pdata; 62 #endif 63 struct reset_ctl phy_reset; 64 bool integrated_phy; 65 bool clock_input; 66 int phy_interface; 67 int tx_delay; 68 int rx_delay; 69 int bus_id; 70 }; 71 72 struct rk_gmac_ops { 73 #ifdef CONFIG_DWC_ETH_QOS 74 const struct eqos_config config; 75 #endif 76 int (*fix_mac_speed)(struct gmac_rockchip_platdata *pdata, 77 struct rockchip_eth_dev *dev); 78 void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata); 79 void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata); 80 void (*set_clock_selection)(struct gmac_rockchip_platdata *pdata); 81 void (*integrated_phy_powerup)(struct gmac_rockchip_platdata *pdata); 82 }; 83 84 #ifdef CONFIG_DWC_ETH_QOS 85 static const struct eqos_config eqos_rockchip_config = { 86 .reg_access_always_ok = false, 87 .mdio_wait = 10000, 88 .swr_wait = 200, 89 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED, 90 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_100_150, 91 .ops = &eqos_rockchip_ops, 92 }; 93 #endif 94 95 void gmac_set_rgmii(struct udevice *dev, u32 tx_delay, u32 rx_delay) 96 { 97 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 98 struct rk_gmac_ops *ops = 99 (struct rk_gmac_ops *)dev_get_driver_data(dev); 100 101 pdata->tx_delay = tx_delay; 102 pdata->rx_delay = rx_delay; 103 104 ops->set_to_rgmii(pdata); 105 } 106 107 static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) 108 { 109 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 110 struct ofnode_phandle_args args; 111 const char *string; 112 int ret; 113 114 string = dev_read_string(dev, "clock_in_out"); 115 if (!strcmp(string, "input")) 116 pdata->clock_input = true; 117 else 118 pdata->clock_input = false; 119 120 /* If phy-handle property is passed from DT, use it as the PHY */ 121 ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &args); 122 if (ret) { 123 debug("Cannot get phy phandle: ret=%d\n", ret); 124 pdata->integrated_phy = dev_read_bool(dev, "phy-is-integrated"); 125 } else { 126 debug("Found phy-handle subnode\n"); 127 pdata->integrated_phy = ofnode_read_bool(args.node, 128 "phy-is-integrated"); 129 } 130 131 if (pdata->integrated_phy) { 132 ret = reset_get_by_name(dev, "mac-phy", &pdata->phy_reset); 133 if (ret) { 134 debug("No PHY reset control found: ret=%d\n", ret); 135 return ret; 136 } 137 } 138 139 /* Check the new naming-style first... */ 140 pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT); 141 pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT); 142 143 /* ... and fall back to the old naming style or default, if necessary */ 144 if (pdata->tx_delay == -ENOENT) 145 pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30); 146 if (pdata->rx_delay == -ENOENT) 147 pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10); 148 149 #ifdef CONFIG_DWC_ETH_QOS 150 return 0; 151 #else 152 return designware_eth_ofdata_to_platdata(dev); 153 #endif 154 } 155 156 #ifndef CONFIG_DWC_ETH_QOS 157 static int px30_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 158 struct rockchip_eth_dev *dev) 159 { 160 struct dw_eth_dev *priv = &dev->dw; 161 struct px30_grf *grf; 162 struct clk clk_speed; 163 int speed, ret; 164 enum { 165 PX30_GMAC_SPEED_SHIFT = 0x2, 166 PX30_GMAC_SPEED_MASK = BIT(2), 167 PX30_GMAC_SPEED_10M = 0, 168 PX30_GMAC_SPEED_100M = BIT(2), 169 }; 170 171 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 172 &clk_speed); 173 if (ret) 174 return ret; 175 176 switch (priv->phydev->speed) { 177 case 10: 178 speed = PX30_GMAC_SPEED_10M; 179 ret = clk_set_rate(&clk_speed, 2500000); 180 if (ret) 181 return ret; 182 break; 183 case 100: 184 speed = PX30_GMAC_SPEED_100M; 185 ret = clk_set_rate(&clk_speed, 25000000); 186 if (ret) 187 return ret; 188 break; 189 default: 190 debug("Unknown phy speed: %d\n", priv->phydev->speed); 191 return -EINVAL; 192 } 193 194 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 195 rk_clrsetreg(&grf->mac_con1, PX30_GMAC_SPEED_MASK, speed); 196 197 return 0; 198 } 199 200 static int rk1808_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 201 struct rockchip_eth_dev *dev) 202 { 203 struct dw_eth_dev *priv = &dev->dw; 204 struct clk clk_speed; 205 int ret; 206 207 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 208 &clk_speed); 209 if (ret) 210 return ret; 211 212 switch (priv->phydev->speed) { 213 case 10: 214 ret = clk_set_rate(&clk_speed, 2500000); 215 if (ret) 216 return ret; 217 break; 218 case 100: 219 ret = clk_set_rate(&clk_speed, 25000000); 220 if (ret) 221 return ret; 222 break; 223 case 1000: 224 ret = clk_set_rate(&clk_speed, 125000000); 225 if (ret) 226 return ret; 227 break; 228 default: 229 debug("Unknown phy speed: %d\n", priv->phydev->speed); 230 return -EINVAL; 231 } 232 233 return 0; 234 } 235 236 static int rk3228_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 237 struct rockchip_eth_dev *dev) 238 { 239 struct dw_eth_dev *priv = &dev->dw; 240 struct rk322x_grf *grf; 241 int clk; 242 enum { 243 RK3228_GMAC_CLK_SEL_SHIFT = 8, 244 RK3228_GMAC_CLK_SEL_MASK = GENMASK(9, 8), 245 RK3228_GMAC_CLK_SEL_125M = 0 << 8, 246 RK3228_GMAC_CLK_SEL_25M = 3 << 8, 247 RK3228_GMAC_CLK_SEL_2_5M = 2 << 8, 248 249 RK3228_GMAC_RMII_CLK_MASK = BIT(7), 250 RK3228_GMAC_RMII_CLK_2_5M = 0, 251 RK3228_GMAC_RMII_CLK_25M = BIT(7), 252 253 RK3228_GMAC_RMII_SPEED_MASK = BIT(2), 254 RK3228_GMAC_RMII_SPEED_10 = 0, 255 RK3228_GMAC_RMII_SPEED_100 = BIT(2), 256 }; 257 258 switch (priv->phydev->speed) { 259 case 10: 260 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 261 (RK3228_GMAC_RMII_CLK_2_5M | RK3228_GMAC_RMII_SPEED_10) : 262 RK3228_GMAC_CLK_SEL_2_5M; 263 break; 264 case 100: 265 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 266 (RK3228_GMAC_RMII_CLK_25M | RK3228_GMAC_RMII_SPEED_100) : 267 RK3228_GMAC_CLK_SEL_25M; 268 break; 269 case 1000: 270 clk = RK3228_GMAC_CLK_SEL_125M; 271 break; 272 default: 273 debug("Unknown phy speed: %d\n", priv->phydev->speed); 274 return -EINVAL; 275 } 276 277 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 278 rk_clrsetreg(&grf->mac_con[1], 279 RK3228_GMAC_CLK_SEL_MASK | 280 RK3228_GMAC_RMII_CLK_MASK | 281 RK3228_GMAC_RMII_SPEED_MASK, 282 clk); 283 284 return 0; 285 } 286 287 static int rk3288_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 288 struct rockchip_eth_dev *dev) 289 { 290 struct dw_eth_dev *priv = &dev->dw; 291 struct rk3288_grf *grf; 292 int clk; 293 294 switch (priv->phydev->speed) { 295 case 10: 296 clk = RK3288_GMAC_CLK_SEL_2_5M; 297 break; 298 case 100: 299 clk = RK3288_GMAC_CLK_SEL_25M; 300 break; 301 case 1000: 302 clk = RK3288_GMAC_CLK_SEL_125M; 303 break; 304 default: 305 debug("Unknown phy speed: %d\n", priv->phydev->speed); 306 return -EINVAL; 307 } 308 309 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 310 rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk); 311 312 return 0; 313 } 314 315 static int rk3308_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 316 struct rockchip_eth_dev *dev) 317 { 318 struct dw_eth_dev *priv = &dev->dw; 319 struct rk3308_grf *grf; 320 struct clk clk_speed; 321 int speed, ret; 322 enum { 323 RK3308_GMAC_SPEED_SHIFT = 0x0, 324 RK3308_GMAC_SPEED_MASK = BIT(0), 325 RK3308_GMAC_SPEED_10M = 0, 326 RK3308_GMAC_SPEED_100M = BIT(0), 327 }; 328 329 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 330 &clk_speed); 331 if (ret) 332 return ret; 333 334 switch (priv->phydev->speed) { 335 case 10: 336 speed = RK3308_GMAC_SPEED_10M; 337 ret = clk_set_rate(&clk_speed, 2500000); 338 if (ret) 339 return ret; 340 break; 341 case 100: 342 speed = RK3308_GMAC_SPEED_100M; 343 ret = clk_set_rate(&clk_speed, 25000000); 344 if (ret) 345 return ret; 346 break; 347 default: 348 debug("Unknown phy speed: %d\n", priv->phydev->speed); 349 return -EINVAL; 350 } 351 352 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 353 rk_clrsetreg(&grf->mac_con0, RK3308_GMAC_SPEED_MASK, speed); 354 355 return 0; 356 } 357 358 static int rk3328_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 359 struct rockchip_eth_dev *dev) 360 { 361 struct dw_eth_dev *priv = &dev->dw; 362 struct rk3328_grf_regs *grf; 363 int clk; 364 enum { 365 RK3328_GMAC_CLK_SEL_SHIFT = 11, 366 RK3328_GMAC_CLK_SEL_MASK = GENMASK(12, 11), 367 RK3328_GMAC_CLK_SEL_125M = 0 << 11, 368 RK3328_GMAC_CLK_SEL_25M = 3 << 11, 369 RK3328_GMAC_CLK_SEL_2_5M = 2 << 11, 370 371 RK3328_GMAC_RMII_CLK_MASK = BIT(7), 372 RK3328_GMAC_RMII_CLK_2_5M = 0, 373 RK3328_GMAC_RMII_CLK_25M = BIT(7), 374 375 RK3328_GMAC_RMII_SPEED_MASK = BIT(2), 376 RK3328_GMAC_RMII_SPEED_10 = 0, 377 RK3328_GMAC_RMII_SPEED_100 = BIT(2), 378 }; 379 380 switch (priv->phydev->speed) { 381 case 10: 382 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 383 (RK3328_GMAC_RMII_CLK_2_5M | RK3328_GMAC_RMII_SPEED_10) : 384 RK3328_GMAC_CLK_SEL_2_5M; 385 break; 386 case 100: 387 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 388 (RK3328_GMAC_RMII_CLK_25M | RK3328_GMAC_RMII_SPEED_100) : 389 RK3328_GMAC_CLK_SEL_25M; 390 break; 391 case 1000: 392 clk = RK3328_GMAC_CLK_SEL_125M; 393 break; 394 default: 395 debug("Unknown phy speed: %d\n", priv->phydev->speed); 396 return -EINVAL; 397 } 398 399 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 400 rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1], 401 RK3328_GMAC_CLK_SEL_MASK | 402 RK3328_GMAC_RMII_CLK_MASK | 403 RK3328_GMAC_RMII_SPEED_MASK, 404 clk); 405 406 return 0; 407 } 408 409 static int rk3368_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 410 struct rockchip_eth_dev *dev) 411 { 412 struct dw_eth_dev *priv = &dev->dw; 413 struct rk3368_grf *grf; 414 int clk; 415 enum { 416 RK3368_GMAC_CLK_SEL_2_5M = 2 << 4, 417 RK3368_GMAC_CLK_SEL_25M = 3 << 4, 418 RK3368_GMAC_CLK_SEL_125M = 0 << 4, 419 RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4), 420 }; 421 422 switch (priv->phydev->speed) { 423 case 10: 424 clk = RK3368_GMAC_CLK_SEL_2_5M; 425 break; 426 case 100: 427 clk = RK3368_GMAC_CLK_SEL_25M; 428 break; 429 case 1000: 430 clk = RK3368_GMAC_CLK_SEL_125M; 431 break; 432 default: 433 debug("Unknown phy speed: %d\n", priv->phydev->speed); 434 return -EINVAL; 435 } 436 437 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 438 rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk); 439 440 return 0; 441 } 442 443 static int rk3399_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 444 struct rockchip_eth_dev *dev) 445 { 446 struct dw_eth_dev *priv = &dev->dw; 447 struct rk3399_grf_regs *grf; 448 int clk; 449 450 switch (priv->phydev->speed) { 451 case 10: 452 clk = RK3399_GMAC_CLK_SEL_2_5M; 453 break; 454 case 100: 455 clk = RK3399_GMAC_CLK_SEL_25M; 456 break; 457 case 1000: 458 clk = RK3399_GMAC_CLK_SEL_125M; 459 break; 460 default: 461 debug("Unknown phy speed: %d\n", priv->phydev->speed); 462 return -EINVAL; 463 } 464 465 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 466 rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk); 467 468 return 0; 469 } 470 471 static int rv1108_set_rmii_speed(struct gmac_rockchip_platdata *pdata, 472 struct rockchip_eth_dev *dev) 473 { 474 struct dw_eth_dev *priv = &dev->dw; 475 struct rv1108_grf *grf; 476 int clk, speed; 477 enum { 478 RV1108_GMAC_SPEED_MASK = BIT(2), 479 RV1108_GMAC_SPEED_10M = 0 << 2, 480 RV1108_GMAC_SPEED_100M = 1 << 2, 481 RV1108_GMAC_CLK_SEL_MASK = BIT(7), 482 RV1108_GMAC_CLK_SEL_2_5M = 0 << 7, 483 RV1108_GMAC_CLK_SEL_25M = 1 << 7, 484 }; 485 486 switch (priv->phydev->speed) { 487 case 10: 488 clk = RV1108_GMAC_CLK_SEL_2_5M; 489 speed = RV1108_GMAC_SPEED_10M; 490 break; 491 case 100: 492 clk = RV1108_GMAC_CLK_SEL_25M; 493 speed = RV1108_GMAC_SPEED_100M; 494 break; 495 default: 496 debug("Unknown phy speed: %d\n", priv->phydev->speed); 497 return -EINVAL; 498 } 499 500 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 501 rk_clrsetreg(&grf->gmac_con0, 502 RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK, 503 clk | speed); 504 505 return 0; 506 } 507 #else 508 static int rk3588_set_rgmii_speed(struct gmac_rockchip_platdata *pdata, 509 struct rockchip_eth_dev *dev) 510 { 511 struct eqos_priv *priv = &dev->eqos; 512 struct rk3588_php_grf *php_grf; 513 unsigned int div, div_mask; 514 515 enum { 516 RK3588_GMAC_CLK_RGMII_DIV_SHIFT = 2, 517 RK3588_GMAC_CLK_RGMII_DIV_MASK = GENMASK(3, 2), 518 RK3588_GMAC_CLK_RGMII_DIV1 = 0, 519 RK3588_GMAC_CLK_RGMII_DIV5 = GENMASK(3, 2), 520 RK3588_GMAC_CLK_RGMII_DIV50 = BIT(3), 521 RK3588_GMA_CLK_RMII_DIV2 = BIT(2), 522 RK3588_GMAC_CLK_RMII_DIV20 = 0, 523 }; 524 525 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 526 527 switch (priv->phy->speed) { 528 case 10: 529 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) 530 div = RK3588_GMAC_CLK_RMII_DIV20; 531 else 532 div = RK3588_GMAC_CLK_RGMII_DIV50; 533 break; 534 case 100: 535 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) 536 div = RK3588_GMA_CLK_RMII_DIV2; 537 else 538 div = RK3588_GMAC_CLK_RGMII_DIV5; 539 break; 540 case 1000: 541 if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII) 542 div = RK3588_GMAC_CLK_RGMII_DIV1; 543 else 544 return -EINVAL; 545 break; 546 default: 547 debug("Unknown phy speed: %d\n", priv->phy->speed); 548 return -EINVAL; 549 } 550 551 if (pdata->bus_id == 1) { 552 div <<= 5; 553 div_mask = RK3588_GMAC_CLK_RGMII_DIV_MASK << 5; 554 } 555 556 rk_clrsetreg(&php_grf->clk_con1, div_mask, div); 557 558 return 0; 559 } 560 561 static int rv1106_set_rmii_speed(struct gmac_rockchip_platdata *pdata, 562 struct rockchip_eth_dev *dev) 563 { 564 struct eqos_priv *priv = &dev->eqos; 565 struct rv1106_grf *grf; 566 unsigned int div; 567 568 enum { 569 RV1106_GMAC_CLK_RMII_DIV_SHIFT = 2, 570 RV1106_GMAC_CLK_RMII_DIV_MASK = GENMASK(3, 2), 571 RV1106_GMAC_CLK_RMII_DIV2 = BIT(2), 572 RV1106_GMAC_CLK_RMII_DIV20 = 0, 573 }; 574 575 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 576 577 switch (priv->phy->speed) { 578 case 10: 579 div = RV1106_GMAC_CLK_RMII_DIV20; 580 break; 581 case 100: 582 div = RV1106_GMAC_CLK_RMII_DIV2; 583 break; 584 default: 585 debug("Unknown phy speed: %d\n", priv->phy->speed); 586 return -EINVAL; 587 } 588 589 rk_clrsetreg(&grf->gmac_clk_con, RV1106_GMAC_CLK_RMII_DIV_MASK, div); 590 591 return 0; 592 } 593 594 static int rv1126_set_rgmii_speed(struct gmac_rockchip_platdata *pdata, 595 struct rockchip_eth_dev *dev) 596 { 597 struct eqos_priv *priv = &dev->eqos; 598 struct clk clk_speed; 599 int ret; 600 601 ret = clk_get_by_name(priv->phy->dev, "clk_mac_speed", 602 &clk_speed); 603 if (ret) { 604 printf("%s can't get clk_mac_speed clock (ret=%d):\n", 605 __func__, ret); 606 return ret; 607 } 608 609 switch ( priv->phy->speed) { 610 case 10: 611 ret = clk_set_rate(&clk_speed, 2500000); 612 if (ret) 613 return ret; 614 break; 615 case 100: 616 ret = clk_set_rate(&clk_speed, 25000000); 617 if (ret) 618 return ret; 619 break; 620 case 1000: 621 ret = clk_set_rate(&clk_speed, 125000000); 622 if (ret) 623 return ret; 624 break; 625 default: 626 debug("Unknown phy speed: %d\n", priv->phy->speed); 627 return -EINVAL; 628 } 629 630 return 0; 631 } 632 #endif 633 634 #ifndef CONFIG_DWC_ETH_QOS 635 static void px30_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 636 { 637 struct px30_grf *grf; 638 enum { 639 px30_GMAC_PHY_INTF_SEL_SHIFT = 4, 640 px30_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 6), 641 px30_GMAC_PHY_INTF_SEL_RMII = BIT(6), 642 }; 643 644 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 645 646 rk_clrsetreg(&grf->mac_con1, 647 px30_GMAC_PHY_INTF_SEL_MASK, 648 px30_GMAC_PHY_INTF_SEL_RMII); 649 } 650 651 static void rk1808_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 652 { 653 struct rk1808_grf *grf; 654 enum { 655 RK1808_GMAC_PHY_INTF_SEL_SHIFT = 4, 656 RK1808_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 657 RK1808_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 658 659 RK1808_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 660 RK1808_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 661 RK1808_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 662 663 RK1808_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 664 RK1808_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 665 RK1808_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 666 }; 667 enum { 668 RK1808_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 669 RK1808_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 7), 670 671 RK1808_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 672 RK1808_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 673 }; 674 675 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 676 rk_clrsetreg(&grf->mac_con1, 677 RK1808_GMAC_PHY_INTF_SEL_MASK | 678 RK1808_RXCLK_DLY_ENA_GMAC_MASK | 679 RK1808_TXCLK_DLY_ENA_GMAC_MASK, 680 RK1808_GMAC_PHY_INTF_SEL_RGMII | 681 RK1808_RXCLK_DLY_ENA_GMAC_ENABLE | 682 RK1808_TXCLK_DLY_ENA_GMAC_ENABLE); 683 684 rk_clrsetreg(&grf->mac_con0, 685 RK1808_CLK_RX_DL_CFG_GMAC_MASK | 686 RK1808_CLK_TX_DL_CFG_GMAC_MASK, 687 pdata->rx_delay << RK1808_CLK_RX_DL_CFG_GMAC_SHIFT | 688 pdata->tx_delay << RK1808_CLK_TX_DL_CFG_GMAC_SHIFT); 689 } 690 691 static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 692 { 693 struct rk322x_grf *grf; 694 enum { 695 RK3228_RMII_MODE_SHIFT = 10, 696 RK3228_RMII_MODE_MASK = BIT(10), 697 698 RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4, 699 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 700 RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 701 702 RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 703 RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 704 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 705 706 RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 707 RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 708 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 709 }; 710 enum { 711 RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 712 RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 713 714 RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 715 RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 716 }; 717 718 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 719 rk_clrsetreg(&grf->mac_con[1], 720 RK3228_RMII_MODE_MASK | 721 RK3228_GMAC_PHY_INTF_SEL_MASK | 722 RK3228_RXCLK_DLY_ENA_GMAC_MASK | 723 RK3228_TXCLK_DLY_ENA_GMAC_MASK, 724 RK3228_GMAC_PHY_INTF_SEL_RGMII | 725 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE | 726 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE); 727 728 rk_clrsetreg(&grf->mac_con[0], 729 RK3228_CLK_RX_DL_CFG_GMAC_MASK | 730 RK3228_CLK_TX_DL_CFG_GMAC_MASK, 731 pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT | 732 pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT); 733 } 734 735 static void rk3228_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 736 { 737 struct rk322x_grf *grf; 738 enum { 739 RK3228_GRF_CON_RMII_MODE_MASK = BIT(11), 740 RK3228_GRF_CON_RMII_MODE_SEL = BIT(11), 741 RK3228_RMII_MODE_MASK = BIT(10), 742 RK3228_RMII_MODE_SEL = BIT(10), 743 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 744 RK3228_GMAC_PHY_INTF_SEL_RMII = BIT(6), 745 }; 746 747 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 748 rk_clrsetreg(&grf->mac_con[1], 749 RK3228_GRF_CON_RMII_MODE_MASK | 750 RK3228_RMII_MODE_MASK | 751 RK3228_GMAC_PHY_INTF_SEL_MASK, 752 RK3228_GRF_CON_RMII_MODE_SEL | 753 RK3228_RMII_MODE_SEL | 754 RK3228_GMAC_PHY_INTF_SEL_RMII); 755 } 756 757 static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 758 { 759 struct rk3288_grf *grf; 760 761 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 762 rk_clrsetreg(&grf->soc_con1, 763 RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK, 764 RK3288_GMAC_PHY_INTF_SEL_RGMII); 765 766 rk_clrsetreg(&grf->soc_con3, 767 RK3288_RXCLK_DLY_ENA_GMAC_MASK | 768 RK3288_TXCLK_DLY_ENA_GMAC_MASK | 769 RK3288_CLK_RX_DL_CFG_GMAC_MASK | 770 RK3288_CLK_TX_DL_CFG_GMAC_MASK, 771 RK3288_RXCLK_DLY_ENA_GMAC_ENABLE | 772 RK3288_TXCLK_DLY_ENA_GMAC_ENABLE | 773 pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT | 774 pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT); 775 } 776 777 static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 778 { 779 struct rk3308_grf *grf; 780 enum { 781 RK3308_GMAC_PHY_INTF_SEL_SHIFT = 2, 782 RK3308_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 2), 783 RK3308_GMAC_PHY_INTF_SEL_RMII = BIT(4), 784 }; 785 786 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 787 788 rk_clrsetreg(&grf->mac_con0, 789 RK3308_GMAC_PHY_INTF_SEL_MASK, 790 RK3308_GMAC_PHY_INTF_SEL_RMII); 791 } 792 793 static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 794 { 795 struct rk3328_grf_regs *grf; 796 enum { 797 RK3328_RMII_MODE_SHIFT = 9, 798 RK3328_RMII_MODE_MASK = BIT(9), 799 800 RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4, 801 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 802 RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 803 804 RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 805 RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 806 RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 807 808 RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 809 RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 810 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 811 }; 812 enum { 813 RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 814 RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 815 816 RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 817 RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 818 }; 819 820 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 821 rk_clrsetreg(&grf->mac_con[1], 822 RK3328_RMII_MODE_MASK | 823 RK3328_GMAC_PHY_INTF_SEL_MASK | 824 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 825 RK3328_TXCLK_DLY_ENA_GMAC_MASK, 826 RK3328_GMAC_PHY_INTF_SEL_RGMII | 827 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 828 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE); 829 830 rk_clrsetreg(&grf->mac_con[0], 831 RK3328_CLK_RX_DL_CFG_GMAC_MASK | 832 RK3328_CLK_TX_DL_CFG_GMAC_MASK, 833 pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT | 834 pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT); 835 } 836 837 static void rk3328_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 838 { 839 struct rk3328_grf_regs *grf; 840 enum { 841 RK3328_RMII_MODE_MASK = BIT(9), 842 RK3328_RMII_MODE = BIT(9), 843 844 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 845 RK3328_GMAC_PHY_INTF_SEL_RMII = BIT(6), 846 }; 847 848 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 849 rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1], 850 RK3328_RMII_MODE_MASK | 851 RK3328_GMAC_PHY_INTF_SEL_MASK, 852 RK3328_GMAC_PHY_INTF_SEL_RMII | 853 RK3328_RMII_MODE); 854 } 855 856 static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 857 { 858 struct rk3368_grf *grf; 859 enum { 860 RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9, 861 RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9), 862 RK3368_RMII_MODE_MASK = BIT(6), 863 RK3368_RMII_MODE = BIT(6), 864 }; 865 enum { 866 RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15), 867 RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 868 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15), 869 RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7), 870 RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 871 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7), 872 RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8, 873 RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 874 RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0, 875 RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 876 }; 877 878 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 879 rk_clrsetreg(&grf->soc_con15, 880 RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK, 881 RK3368_GMAC_PHY_INTF_SEL_RGMII); 882 883 rk_clrsetreg(&grf->soc_con16, 884 RK3368_RXCLK_DLY_ENA_GMAC_MASK | 885 RK3368_TXCLK_DLY_ENA_GMAC_MASK | 886 RK3368_CLK_RX_DL_CFG_GMAC_MASK | 887 RK3368_CLK_TX_DL_CFG_GMAC_MASK, 888 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE | 889 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE | 890 pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT | 891 pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT); 892 } 893 894 static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 895 { 896 struct rk3399_grf_regs *grf; 897 898 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 899 900 rk_clrsetreg(&grf->soc_con5, 901 RK3399_GMAC_PHY_INTF_SEL_MASK, 902 RK3399_GMAC_PHY_INTF_SEL_RGMII); 903 904 rk_clrsetreg(&grf->soc_con6, 905 RK3399_RXCLK_DLY_ENA_GMAC_MASK | 906 RK3399_TXCLK_DLY_ENA_GMAC_MASK | 907 RK3399_CLK_RX_DL_CFG_GMAC_MASK | 908 RK3399_CLK_TX_DL_CFG_GMAC_MASK, 909 RK3399_RXCLK_DLY_ENA_GMAC_ENABLE | 910 RK3399_TXCLK_DLY_ENA_GMAC_ENABLE | 911 pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT | 912 pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT); 913 } 914 915 static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 916 { 917 struct rv1108_grf *grf; 918 919 enum { 920 RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 921 RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4, 922 }; 923 924 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 925 rk_clrsetreg(&grf->gmac_con0, 926 RV1108_GMAC_PHY_INTF_SEL_MASK, 927 RV1108_GMAC_PHY_INTF_SEL_RMII); 928 } 929 930 static void rk3228_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 931 { 932 struct rk322x_grf *grf; 933 enum { 934 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK = BIT(15), 935 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY = BIT(15), 936 }; 937 enum { 938 RK3228_MACPHY_CFG_CLK_50M_MASK = BIT(14), 939 RK3228_MACPHY_CFG_CLK_50M = BIT(14), 940 941 RK3228_MACPHY_RMII_MODE_MASK = GENMASK(7, 6), 942 RK3228_MACPHY_RMII_MODE = BIT(6), 943 944 RK3228_MACPHY_ENABLE_MASK = BIT(0), 945 RK3228_MACPHY_DISENABLE = 0, 946 RK3228_MACPHY_ENABLE = BIT(0), 947 }; 948 enum { 949 RK3228_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0), 950 RK3228_RK_GRF_CON2_MACPHY_ID = 0x1234, 951 }; 952 enum { 953 RK3228_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0), 954 RK3228_RK_GRF_CON3_MACPHY_ID = 0x35, 955 }; 956 957 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 958 rk_clrsetreg(&grf->con_iomux, 959 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK, 960 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY); 961 962 rk_clrsetreg(&grf->macphy_con[2], 963 RK3228_RK_GRF_CON2_MACPHY_ID_MASK, 964 RK3228_RK_GRF_CON2_MACPHY_ID); 965 966 rk_clrsetreg(&grf->macphy_con[3], 967 RK3228_RK_GRF_CON3_MACPHY_ID_MASK, 968 RK3228_RK_GRF_CON3_MACPHY_ID); 969 970 /* disabled before trying to reset it &*/ 971 rk_clrsetreg(&grf->macphy_con[0], 972 RK3228_MACPHY_CFG_CLK_50M_MASK | 973 RK3228_MACPHY_RMII_MODE_MASK | 974 RK3228_MACPHY_ENABLE_MASK, 975 RK3228_MACPHY_CFG_CLK_50M | 976 RK3228_MACPHY_RMII_MODE | 977 RK3228_MACPHY_DISENABLE); 978 979 reset_assert(&pdata->phy_reset); 980 udelay(10); 981 reset_deassert(&pdata->phy_reset); 982 udelay(10); 983 984 rk_clrsetreg(&grf->macphy_con[0], 985 RK3228_MACPHY_ENABLE_MASK, 986 RK3228_MACPHY_ENABLE); 987 udelay(30 * 1000); 988 } 989 990 static void rk3328_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 991 { 992 struct rk3328_grf_regs *grf; 993 enum { 994 RK3328_GRF_CON_RMII_MODE_MASK = BIT(9), 995 RK3328_GRF_CON_RMII_MODE = BIT(9), 996 }; 997 enum { 998 RK3328_MACPHY_CFG_CLK_50M_MASK = BIT(14), 999 RK3328_MACPHY_CFG_CLK_50M = BIT(14), 1000 1001 RK3328_MACPHY_RMII_MODE_MASK = GENMASK(7, 6), 1002 RK3328_MACPHY_RMII_MODE = BIT(6), 1003 1004 RK3328_MACPHY_ENABLE_MASK = BIT(0), 1005 RK3328_MACPHY_DISENABLE = 0, 1006 RK3328_MACPHY_ENABLE = BIT(0), 1007 }; 1008 enum { 1009 RK3328_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0), 1010 RK3328_RK_GRF_CON2_MACPHY_ID = 0x1234, 1011 }; 1012 enum { 1013 RK3328_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0), 1014 RK3328_RK_GRF_CON3_MACPHY_ID = 0x35, 1015 }; 1016 1017 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1018 rk_clrsetreg(&grf->macphy_con[1], 1019 RK3328_GRF_CON_RMII_MODE_MASK, 1020 RK3328_GRF_CON_RMII_MODE); 1021 1022 rk_clrsetreg(&grf->macphy_con[2], 1023 RK3328_RK_GRF_CON2_MACPHY_ID_MASK, 1024 RK3328_RK_GRF_CON2_MACPHY_ID); 1025 1026 rk_clrsetreg(&grf->macphy_con[3], 1027 RK3328_RK_GRF_CON3_MACPHY_ID_MASK, 1028 RK3328_RK_GRF_CON3_MACPHY_ID); 1029 1030 /* disabled before trying to reset it &*/ 1031 rk_clrsetreg(&grf->macphy_con[0], 1032 RK3328_MACPHY_CFG_CLK_50M_MASK | 1033 RK3328_MACPHY_RMII_MODE_MASK | 1034 RK3328_MACPHY_ENABLE_MASK, 1035 RK3328_MACPHY_CFG_CLK_50M | 1036 RK3328_MACPHY_RMII_MODE | 1037 RK3328_MACPHY_DISENABLE); 1038 1039 reset_assert(&pdata->phy_reset); 1040 udelay(10); 1041 reset_deassert(&pdata->phy_reset); 1042 udelay(10); 1043 1044 rk_clrsetreg(&grf->macphy_con[0], 1045 RK3328_MACPHY_ENABLE_MASK, 1046 RK3328_MACPHY_ENABLE); 1047 udelay(30 * 1000); 1048 } 1049 1050 #else 1051 static void rk3568_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1052 { 1053 struct rk3568_grf *grf; 1054 void *con1; 1055 1056 enum { 1057 RK3568_GMAC_PHY_INTF_SEL_SHIFT = 4, 1058 RK3568_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1059 RK3568_GMAC_PHY_INTF_SEL_RMII = BIT(6), 1060 }; 1061 1062 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1063 1064 if (pdata->bus_id == 1) 1065 con1 = &grf->mac1_con1; 1066 else 1067 con1 = &grf->mac0_con1; 1068 1069 rk_clrsetreg(con1, 1070 RK3568_GMAC_PHY_INTF_SEL_MASK, 1071 RK3568_GMAC_PHY_INTF_SEL_RMII); 1072 } 1073 1074 static void rk3568_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1075 { 1076 struct rk3568_grf *grf; 1077 void *con0, *con1; 1078 1079 enum { 1080 RK3568_GMAC_PHY_INTF_SEL_SHIFT = 4, 1081 RK3568_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1082 RK3568_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 1083 1084 RK3568_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 1085 RK3568_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 1086 RK3568_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 1087 1088 RK3568_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 1089 RK3568_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 1090 RK3568_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 1091 }; 1092 1093 enum { 1094 RK3568_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1095 RK3568_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 8), 1096 1097 RK3568_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1098 RK3568_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 1099 }; 1100 1101 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1102 1103 if (pdata->bus_id == 1) { 1104 con0 = &grf->mac1_con0; 1105 con1 = &grf->mac1_con1; 1106 } else { 1107 con0 = &grf->mac0_con0; 1108 con1 = &grf->mac0_con1; 1109 } 1110 1111 rk_clrsetreg(con0, 1112 RK3568_CLK_RX_DL_CFG_GMAC_MASK | 1113 RK3568_CLK_TX_DL_CFG_GMAC_MASK, 1114 pdata->rx_delay << RK3568_CLK_RX_DL_CFG_GMAC_SHIFT | 1115 pdata->tx_delay << RK3568_CLK_TX_DL_CFG_GMAC_SHIFT); 1116 1117 rk_clrsetreg(con1, 1118 RK3568_TXCLK_DLY_ENA_GMAC_MASK | 1119 RK3568_RXCLK_DLY_ENA_GMAC_MASK | 1120 RK3568_GMAC_PHY_INTF_SEL_MASK, 1121 RK3568_TXCLK_DLY_ENA_GMAC_ENABLE | 1122 RK3568_RXCLK_DLY_ENA_GMAC_ENABLE | 1123 RK3568_GMAC_PHY_INTF_SEL_RGMII); 1124 } 1125 1126 static void rk3588_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1127 { 1128 unsigned int intf_sel, intf_sel_mask; 1129 unsigned int clk_mode, clk_mode_mask; 1130 struct rk3588_php_grf *php_grf; 1131 1132 enum { 1133 RK3588_GMAC_PHY_INTF_SEL_SHIFT = 3, 1134 RK3588_GMAC_PHY_INTF_SEL_MASK = GENMASK(5, 3), 1135 RK3588_GMAC_PHY_INTF_SEL_RMII = BIT(5), 1136 }; 1137 1138 enum { 1139 RK3588_GMAC_CLK_RMII_MODE_SHIFT = 0x0, 1140 RK3588_GMAC_CLK_RMII_MODE_MASK = BIT(0), 1141 RK3588_GMAC_CLK_RMII_MODE = 0x1, 1142 }; 1143 1144 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 1145 1146 if (pdata->bus_id == 1) { 1147 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RMII << 6; 1148 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK << 6; 1149 clk_mode = RK3588_GMAC_CLK_RMII_MODE << 5; 1150 clk_mode_mask = RK3588_GMAC_CLK_RMII_MODE_MASK << 5; 1151 } else { 1152 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RMII; 1153 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK; 1154 clk_mode = RK3588_GMAC_CLK_RMII_MODE; 1155 clk_mode_mask = RK3588_GMAC_CLK_RMII_MODE_MASK; 1156 } 1157 1158 rk_clrsetreg(&php_grf->gmac_con0, intf_sel_mask, intf_sel); 1159 rk_clrsetreg(&php_grf->clk_con1, clk_mode_mask, clk_mode); 1160 } 1161 1162 static void rk3588_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1163 { 1164 unsigned int rx_enable, rx_enable_mask, tx_enable, tx_enable_mask; 1165 unsigned int intf_sel, intf_sel_mask; 1166 unsigned int clk_mode, clk_mode_mask; 1167 unsigned int rx_delay; 1168 struct rk3588_php_grf *php_grf; 1169 struct rk3588_sys_grf *grf; 1170 void *offset_con; 1171 1172 enum { 1173 RK3588_GMAC_PHY_INTF_SEL_SHIFT = 3, 1174 RK3588_GMAC_PHY_INTF_SEL_MASK = GENMASK(5, 3), 1175 RK3588_GMAC_PHY_INTF_SEL_RGMII = BIT(3), 1176 1177 RK3588_RXCLK_DLY_ENA_GMAC_MASK = BIT(3), 1178 RK3588_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 1179 RK3588_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(3), 1180 1181 RK3588_TXCLK_DLY_ENA_GMAC_MASK = BIT(2), 1182 RK3588_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 1183 RK3588_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(2), 1184 }; 1185 1186 enum { 1187 RK3588_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1188 RK3588_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 8), 1189 1190 RK3588_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1191 RK3588_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 1192 }; 1193 1194 enum { 1195 RK3588_GMAC_CLK_RGMII_MODE_SHIFT = 0x0, 1196 RK3588_GMAC_CLK_RGMII_MODE_MASK = BIT(0), 1197 RK3588_GMAC_CLK_RGMII_MODE = 0x0, 1198 }; 1199 1200 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1201 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 1202 1203 if (pdata->rx_delay < 0) { 1204 rx_enable = RK3588_RXCLK_DLY_ENA_GMAC_DISABLE; 1205 rx_delay = 0; 1206 } else { 1207 rx_enable = RK3588_RXCLK_DLY_ENA_GMAC_ENABLE; 1208 rx_delay = pdata->rx_delay << RK3588_CLK_RX_DL_CFG_GMAC_SHIFT; 1209 } 1210 1211 if (pdata->bus_id == 1) { 1212 offset_con = &grf->soc_con9; 1213 rx_enable = rx_delay << 2; 1214 rx_enable_mask = RK3588_RXCLK_DLY_ENA_GMAC_MASK << 2; 1215 tx_enable = RK3588_TXCLK_DLY_ENA_GMAC_ENABLE << 2; 1216 tx_enable_mask = RK3588_TXCLK_DLY_ENA_GMAC_MASK << 2; 1217 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RGMII << 6; 1218 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK << 6; 1219 clk_mode = RK3588_GMAC_CLK_RGMII_MODE << 5; 1220 clk_mode_mask = RK3588_GMAC_CLK_RGMII_MODE_MASK << 5; 1221 } else { 1222 offset_con = &grf->soc_con8; 1223 rx_enable_mask = RK3588_RXCLK_DLY_ENA_GMAC_MASK; 1224 tx_enable = RK3588_TXCLK_DLY_ENA_GMAC_ENABLE; 1225 tx_enable_mask = RK3588_TXCLK_DLY_ENA_GMAC_MASK; 1226 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RGMII; 1227 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK; 1228 clk_mode = RK3588_GMAC_CLK_RGMII_MODE; 1229 clk_mode_mask = RK3588_GMAC_CLK_RGMII_MODE_MASK; 1230 } 1231 1232 rk_clrsetreg(offset_con, 1233 RK3588_CLK_TX_DL_CFG_GMAC_MASK | 1234 RK3588_CLK_RX_DL_CFG_GMAC_MASK, 1235 pdata->tx_delay << RK3588_CLK_TX_DL_CFG_GMAC_SHIFT | 1236 rx_delay); 1237 1238 rk_clrsetreg(&grf->soc_con7, tx_enable_mask | rx_enable_mask, 1239 tx_enable | rx_enable); 1240 1241 rk_clrsetreg(&php_grf->gmac_con0, intf_sel_mask, intf_sel); 1242 rk_clrsetreg(&php_grf->clk_con1, clk_mode_mask, clk_mode); 1243 } 1244 1245 static void rv1106_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 1246 { 1247 struct rv1106_grf *grf; 1248 enum { 1249 RV1106_MACPHY_ENABLE_MASK = BIT(1), 1250 RV1106_MACPHY_DISENABLE = 0, 1251 RV1106_MACPHY_ENABLE = BIT(1), 1252 RV1106_MACPHY_MODE_MASK = GENMASK(3, 2), 1253 RV1106_MACPHY_RMII_MODE = BIT(2), 1254 RV1106_MACPHY_XMII_SEL_MASK = GENMASK(6, 5), 1255 RV1106_MACPHY_XMII_SEL = BIT(6), 1256 RV1106_MACPHY_24M_CLK_SEL_MASK = GENMASK(9, 7), 1257 RV1106_MACPHY_24M_CLK_SEL_24M = (BIT(8) | BIT(9)), 1258 RV1106_MACPHY_PHY_ID_MASK = GENMASK(14, 10), 1259 RV1106_MACPHY_PHY_ID = BIT(11), 1260 }; 1261 1262 enum { 1263 RV1106_MACPHY_BGS_MASK = GENMASK(3, 0), 1264 RV1106_MACPHY_BGS = BIT(1), 1265 }; 1266 1267 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1268 1269 reset_assert(&pdata->phy_reset); 1270 udelay(20); 1271 1272 rk_clrsetreg(&grf->macphy_con0, 1273 RV1106_MACPHY_ENABLE_MASK | 1274 RV1106_MACPHY_MODE_MASK | 1275 RV1106_MACPHY_XMII_SEL_MASK | 1276 RV1106_MACPHY_24M_CLK_SEL_MASK | 1277 RV1106_MACPHY_PHY_ID_MASK, 1278 RV1106_MACPHY_ENABLE | 1279 RV1106_MACPHY_RMII_MODE | 1280 RV1106_MACPHY_XMII_SEL | 1281 RV1106_MACPHY_24M_CLK_SEL_24M | 1282 RV1106_MACPHY_PHY_ID); 1283 1284 rk_clrsetreg(&grf->macphy_con1, 1285 RV1106_MACPHY_BGS_MASK, 1286 RV1106_MACPHY_BGS); 1287 1288 reset_deassert(&pdata->phy_reset); 1289 1290 udelay(30 * 1000); 1291 } 1292 1293 static void rv1126_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1294 { 1295 struct rv1126_grf *grf; 1296 1297 enum { 1298 RV1126_GMAC_PHY_INTF_SEL_SHIFT = 4, 1299 RV1126_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1300 RV1126_GMAC_PHY_INTF_SEL_RMII = BIT(6), 1301 }; 1302 1303 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1304 1305 rk_clrsetreg(&grf->mac_con0, 1306 RV1126_GMAC_PHY_INTF_SEL_MASK, 1307 RV1126_GMAC_PHY_INTF_SEL_RMII); 1308 } 1309 1310 static void rv1126_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1311 { 1312 struct rv1126_grf *grf; 1313 1314 enum { 1315 RV1126_GMAC_PHY_INTF_SEL_SHIFT = 4, 1316 RV1126_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1317 RV1126_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 1318 1319 RV1126_RXCLK_M1_DLY_ENA_GMAC_MASK = BIT(3), 1320 RV1126_RXCLK_M1_DLY_ENA_GMAC_DISABLE = 0, 1321 RV1126_RXCLK_M1_DLY_ENA_GMAC_ENABLE = BIT(3), 1322 1323 RV1126_TXCLK_M1_DLY_ENA_GMAC_MASK = BIT(2), 1324 RV1126_TXCLK_M1_DLY_ENA_GMAC_DISABLE = 0, 1325 RV1126_TXCLK_M1_DLY_ENA_GMAC_ENABLE = BIT(2), 1326 1327 RV1126_RXCLK_M0_DLY_ENA_GMAC_MASK = BIT(1), 1328 RV1126_RXCLK_M0_DLY_ENA_GMAC_DISABLE = 0, 1329 RV1126_RXCLK_M0_DLY_ENA_GMAC_ENABLE = BIT(1), 1330 1331 RV1126_TXCLK_M0_DLY_ENA_GMAC_MASK = BIT(0), 1332 RV1126_TXCLK_M0_DLY_ENA_GMAC_DISABLE = 0, 1333 RV1126_TXCLK_M0_DLY_ENA_GMAC_ENABLE = BIT(0), 1334 }; 1335 enum { 1336 RV1126_M0_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1337 RV1126_M0_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 1338 1339 RV1126_M0_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1340 RV1126_M0_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 1341 }; 1342 enum { 1343 RV1126_M1_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1344 RV1126_M1_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 1345 1346 RV1126_M1_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1347 RV1126_M1_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 1348 }; 1349 1350 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1351 1352 rk_clrsetreg(&grf->mac_con0, 1353 RV1126_TXCLK_M0_DLY_ENA_GMAC_MASK | 1354 RV1126_RXCLK_M0_DLY_ENA_GMAC_MASK | 1355 RV1126_TXCLK_M1_DLY_ENA_GMAC_MASK | 1356 RV1126_RXCLK_M1_DLY_ENA_GMAC_MASK | 1357 RV1126_GMAC_PHY_INTF_SEL_MASK, 1358 RV1126_TXCLK_M0_DLY_ENA_GMAC_ENABLE | 1359 RV1126_RXCLK_M0_DLY_ENA_GMAC_ENABLE | 1360 RV1126_TXCLK_M1_DLY_ENA_GMAC_ENABLE | 1361 RV1126_RXCLK_M1_DLY_ENA_GMAC_ENABLE | 1362 RV1126_GMAC_PHY_INTF_SEL_RGMII); 1363 1364 rk_clrsetreg(&grf->mac_con1, 1365 RV1126_M0_CLK_RX_DL_CFG_GMAC_MASK | 1366 RV1126_M0_CLK_TX_DL_CFG_GMAC_MASK, 1367 pdata->rx_delay << RV1126_M0_CLK_RX_DL_CFG_GMAC_SHIFT | 1368 pdata->tx_delay << RV1126_M0_CLK_TX_DL_CFG_GMAC_SHIFT); 1369 1370 rk_clrsetreg(&grf->mac_con2, 1371 RV1126_M1_CLK_RX_DL_CFG_GMAC_MASK | 1372 RV1126_M1_CLK_TX_DL_CFG_GMAC_MASK, 1373 pdata->rx_delay << RV1126_M1_CLK_RX_DL_CFG_GMAC_SHIFT | 1374 pdata->tx_delay << RV1126_M1_CLK_TX_DL_CFG_GMAC_SHIFT); 1375 } 1376 #endif 1377 1378 #ifdef CONFIG_DWC_ETH_QOS 1379 static void rk3588_set_clock_selection(struct gmac_rockchip_platdata *pdata) 1380 { 1381 struct rk3588_php_grf *php_grf; 1382 unsigned int val, mask; 1383 1384 enum { 1385 RK3588_GMAC_CLK_SELET_SHIFT = 0x4, 1386 RK3588_GMAC_CLK_SELET_MASK = BIT(4), 1387 RK3588_GMAC_CLK_SELET_CRU = BIT(4), 1388 RK3588_GMAC_CLK_SELET_IO = 0, 1389 }; 1390 1391 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 1392 val = pdata->clock_input ? RK3588_GMAC_CLK_SELET_IO : 1393 RK3588_GMAC_CLK_SELET_CRU; 1394 mask = RK3588_GMAC_CLK_SELET_MASK; 1395 1396 if (pdata->bus_id == 1) { 1397 val <<= 5; 1398 mask <<= 5; 1399 } 1400 1401 rk_clrsetreg(&php_grf->clk_con1, mask, val); 1402 } 1403 #endif 1404 1405 static int gmac_rockchip_probe(struct udevice *dev) 1406 { 1407 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 1408 struct rk_gmac_ops *ops = 1409 (struct rk_gmac_ops *)dev_get_driver_data(dev); 1410 #ifdef CONFIG_DWC_ETH_QOS 1411 struct eqos_config *config; 1412 #else 1413 struct dw_eth_pdata *dw_pdata; 1414 #endif 1415 struct eth_pdata *eth_pdata; 1416 struct clk clk; 1417 ulong rate; 1418 int ret; 1419 1420 #ifdef CONFIG_DWC_ETH_QOS 1421 eth_pdata = &pdata->eth_pdata; 1422 config = (struct eqos_config *)&ops->config; 1423 memcpy(config, &eqos_rockchip_config, sizeof(struct eqos_config)); 1424 eth_pdata->phy_interface = config->ops->eqos_get_interface(dev); 1425 #else 1426 dw_pdata = &pdata->dw_eth_pdata; 1427 eth_pdata = &dw_pdata->eth_pdata; 1428 #endif 1429 pdata->bus_id = dev->seq; 1430 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 1431 ret = clk_set_defaults(dev); 1432 if (ret) 1433 debug("%s clk_set_defaults failed %d\n", __func__, ret); 1434 1435 ret = clk_get_by_index(dev, 0, &clk); 1436 if (ret) 1437 return ret; 1438 1439 pdata->phy_interface = eth_pdata->phy_interface; 1440 1441 if (ops->set_clock_selection) 1442 ops->set_clock_selection(pdata); 1443 1444 if (pdata->integrated_phy && ops->integrated_phy_powerup) 1445 ops->integrated_phy_powerup(pdata); 1446 1447 switch (eth_pdata->phy_interface) { 1448 case PHY_INTERFACE_MODE_RGMII: 1449 case PHY_INTERFACE_MODE_RGMII_RXID: 1450 /* 1451 * If the gmac clock is from internal pll, need to set and 1452 * check the return value for gmac clock at RGMII mode. If 1453 * the gmac clock is from external source, the clock rate 1454 * is not set, because of it is bypassed. 1455 */ 1456 if (!pdata->clock_input) { 1457 rate = clk_set_rate(&clk, 125000000); 1458 if (rate != 125000000) 1459 return -EINVAL; 1460 } 1461 1462 if (eth_pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) 1463 pdata->rx_delay = -1; 1464 1465 /* Set to RGMII mode */ 1466 if (ops->set_to_rgmii) 1467 ops->set_to_rgmii(pdata); 1468 else 1469 return -EPERM; 1470 1471 break; 1472 case PHY_INTERFACE_MODE_RMII: 1473 /* The commet is the same as RGMII mode */ 1474 if (!pdata->clock_input) { 1475 rate = clk_set_rate(&clk, 50000000); 1476 if (rate != 50000000) 1477 return -EINVAL; 1478 } 1479 1480 /* Set to RMII mode */ 1481 if (ops->set_to_rmii) 1482 ops->set_to_rmii(pdata); 1483 else 1484 return -EPERM; 1485 1486 break; 1487 default: 1488 debug("NO interface defined!\n"); 1489 return -ENXIO; 1490 } 1491 1492 #ifdef CONFIG_DWC_ETH_QOS 1493 return eqos_probe(dev); 1494 #else 1495 return designware_eth_probe(dev); 1496 #endif 1497 } 1498 1499 static int gmac_rockchip_eth_write_hwaddr(struct udevice *dev) 1500 { 1501 #if defined(CONFIG_DWC_ETH_QOS) 1502 return eqos_write_hwaddr(dev); 1503 #else 1504 return designware_eth_write_hwaddr(dev); 1505 #endif 1506 } 1507 1508 static int gmac_rockchip_eth_free_pkt(struct udevice *dev, uchar *packet, 1509 int length) 1510 { 1511 #ifdef CONFIG_DWC_ETH_QOS 1512 return eqos_free_pkt(dev, packet, length); 1513 #else 1514 return designware_eth_free_pkt(dev, packet, length); 1515 #endif 1516 } 1517 1518 static int gmac_rockchip_eth_send(struct udevice *dev, void *packet, 1519 int length) 1520 { 1521 #ifdef CONFIG_DWC_ETH_QOS 1522 return eqos_send(dev, packet, length); 1523 #else 1524 return designware_eth_send(dev, packet, length); 1525 #endif 1526 } 1527 1528 static int gmac_rockchip_eth_recv(struct udevice *dev, int flags, 1529 uchar **packetp) 1530 { 1531 #ifdef CONFIG_DWC_ETH_QOS 1532 return eqos_recv(dev, flags, packetp); 1533 #else 1534 return designware_eth_recv(dev, flags, packetp); 1535 #endif 1536 } 1537 1538 static int gmac_rockchip_eth_start(struct udevice *dev) 1539 { 1540 struct rockchip_eth_dev *priv = dev_get_priv(dev); 1541 struct rk_gmac_ops *ops = 1542 (struct rk_gmac_ops *)dev_get_driver_data(dev); 1543 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 1544 #ifndef CONFIG_DWC_ETH_QOS 1545 struct dw_eth_pdata *dw_pdata; 1546 struct eth_pdata *eth_pdata; 1547 #endif 1548 int ret; 1549 1550 #ifdef CONFIG_DWC_ETH_QOS 1551 ret = eqos_init(dev); 1552 #else 1553 dw_pdata = &pdata->dw_eth_pdata; 1554 eth_pdata = &dw_pdata->eth_pdata; 1555 ret = designware_eth_init((struct dw_eth_dev *)priv, 1556 eth_pdata->enetaddr); 1557 #endif 1558 if (ret) 1559 return ret; 1560 ret = ops->fix_mac_speed(pdata, priv); 1561 if (ret) 1562 return ret; 1563 1564 #ifdef CONFIG_DWC_ETH_QOS 1565 eqos_enable(dev); 1566 #else 1567 ret = designware_eth_enable((struct dw_eth_dev *)priv); 1568 if (ret) 1569 return ret; 1570 #endif 1571 1572 return 0; 1573 } 1574 1575 static void gmac_rockchip_eth_stop(struct udevice *dev) 1576 { 1577 #ifdef CONFIG_DWC_ETH_QOS 1578 eqos_stop(dev); 1579 #else 1580 designware_eth_stop(dev); 1581 #endif 1582 } 1583 1584 const struct eth_ops gmac_rockchip_eth_ops = { 1585 .start = gmac_rockchip_eth_start, 1586 .send = gmac_rockchip_eth_send, 1587 .recv = gmac_rockchip_eth_recv, 1588 .free_pkt = gmac_rockchip_eth_free_pkt, 1589 .stop = gmac_rockchip_eth_stop, 1590 .write_hwaddr = gmac_rockchip_eth_write_hwaddr, 1591 }; 1592 1593 #ifndef CONFIG_DWC_ETH_QOS 1594 const struct rk_gmac_ops px30_gmac_ops = { 1595 .fix_mac_speed = px30_gmac_fix_mac_speed, 1596 .set_to_rmii = px30_gmac_set_to_rmii, 1597 }; 1598 1599 const struct rk_gmac_ops rk1808_gmac_ops = { 1600 .fix_mac_speed = rk1808_gmac_fix_mac_speed, 1601 .set_to_rgmii = rk1808_gmac_set_to_rgmii, 1602 }; 1603 1604 const struct rk_gmac_ops rk3228_gmac_ops = { 1605 .fix_mac_speed = rk3228_gmac_fix_mac_speed, 1606 .set_to_rmii = rk3228_gmac_set_to_rmii, 1607 .set_to_rgmii = rk3228_gmac_set_to_rgmii, 1608 .integrated_phy_powerup = rk3228_gmac_integrated_phy_powerup, 1609 }; 1610 1611 const struct rk_gmac_ops rk3288_gmac_ops = { 1612 .fix_mac_speed = rk3288_gmac_fix_mac_speed, 1613 .set_to_rgmii = rk3288_gmac_set_to_rgmii, 1614 }; 1615 1616 const struct rk_gmac_ops rk3308_gmac_ops = { 1617 .fix_mac_speed = rk3308_gmac_fix_mac_speed, 1618 .set_to_rmii = rk3308_gmac_set_to_rmii, 1619 }; 1620 1621 const struct rk_gmac_ops rk3328_gmac_ops = { 1622 .fix_mac_speed = rk3328_gmac_fix_mac_speed, 1623 .set_to_rmii = rk3328_gmac_set_to_rmii, 1624 .set_to_rgmii = rk3328_gmac_set_to_rgmii, 1625 .integrated_phy_powerup = rk3328_gmac_integrated_phy_powerup, 1626 }; 1627 1628 const struct rk_gmac_ops rk3368_gmac_ops = { 1629 .fix_mac_speed = rk3368_gmac_fix_mac_speed, 1630 .set_to_rgmii = rk3368_gmac_set_to_rgmii, 1631 }; 1632 1633 const struct rk_gmac_ops rk3399_gmac_ops = { 1634 .fix_mac_speed = rk3399_gmac_fix_mac_speed, 1635 .set_to_rgmii = rk3399_gmac_set_to_rgmii, 1636 }; 1637 1638 const struct rk_gmac_ops rv1108_gmac_ops = { 1639 .fix_mac_speed = rv1108_set_rmii_speed, 1640 .set_to_rmii = rv1108_gmac_set_to_rmii, 1641 }; 1642 #else 1643 const struct rk_gmac_ops rk3568_gmac_ops = { 1644 .fix_mac_speed = rv1126_set_rgmii_speed, 1645 .set_to_rgmii = rk3568_set_to_rgmii, 1646 .set_to_rmii = rk3568_set_to_rmii, 1647 }; 1648 1649 const struct rk_gmac_ops rk3588_gmac_ops = { 1650 .fix_mac_speed = rk3588_set_rgmii_speed, 1651 .set_to_rgmii = rk3588_set_to_rgmii, 1652 .set_to_rmii = rk3588_set_to_rmii, 1653 .set_clock_selection = rk3588_set_clock_selection, 1654 }; 1655 1656 const struct rk_gmac_ops rv1106_gmac_ops = { 1657 .fix_mac_speed = rv1106_set_rmii_speed, 1658 .integrated_phy_powerup = rv1106_gmac_integrated_phy_powerup, 1659 }; 1660 1661 const struct rk_gmac_ops rv1126_gmac_ops = { 1662 .fix_mac_speed = rv1126_set_rgmii_speed, 1663 .set_to_rgmii = rv1126_set_to_rgmii, 1664 .set_to_rmii = rv1126_set_to_rmii, 1665 }; 1666 #endif 1667 1668 static const struct udevice_id rockchip_gmac_ids[] = { 1669 #ifndef CONFIG_DWC_ETH_QOS 1670 #ifdef CONFIG_ROCKCHIP_PX30 1671 { .compatible = "rockchip,px30-gmac", 1672 .data = (ulong)&px30_gmac_ops }, 1673 #endif 1674 1675 #ifdef CONFIG_ROCKCHIP_RK1808 1676 { .compatible = "rockchip,rk1808-gmac", 1677 .data = (ulong)&rk1808_gmac_ops }, 1678 #endif 1679 1680 #ifdef CONFIG_ROCKCHIP_RK3228 1681 { .compatible = "rockchip,rk3228-gmac", 1682 .data = (ulong)&rk3228_gmac_ops }, 1683 #endif 1684 1685 #ifdef CONFIG_ROCKCHIP_RK3288 1686 { .compatible = "rockchip,rk3288-gmac", 1687 .data = (ulong)&rk3288_gmac_ops }, 1688 #endif 1689 1690 #ifdef CONFIG_ROCKCHIP_RK3308 1691 { .compatible = "rockchip,rk3308-mac", 1692 .data = (ulong)&rk3308_gmac_ops }, 1693 #endif 1694 1695 #ifdef CONFIG_ROCKCHIP_RK3328 1696 { .compatible = "rockchip,rk3328-gmac", 1697 .data = (ulong)&rk3328_gmac_ops }, 1698 #endif 1699 1700 #ifdef CONFIG_ROCKCHIP_RK3368 1701 { .compatible = "rockchip,rk3368-gmac", 1702 .data = (ulong)&rk3368_gmac_ops }, 1703 #endif 1704 1705 #ifdef CONFIG_ROCKCHIP_RK3399 1706 { .compatible = "rockchip,rk3399-gmac", 1707 .data = (ulong)&rk3399_gmac_ops }, 1708 #endif 1709 1710 #ifdef CONFIG_ROCKCHIP_RV1108 1711 { .compatible = "rockchip,rv1108-gmac", 1712 .data = (ulong)&rv1108_gmac_ops }, 1713 #endif 1714 #else 1715 #ifdef CONFIG_ROCKCHIP_RK3568 1716 { .compatible = "rockchip,rk3568-gmac", 1717 .data = (ulong)&rk3568_gmac_ops }, 1718 #endif 1719 1720 #ifdef CONFIG_ROCKCHIP_RK3588 1721 { .compatible = "rockchip,rk3588-gmac", 1722 .data = (ulong)&rk3588_gmac_ops }, 1723 #endif 1724 1725 #ifdef CONFIG_ROCKCHIP_RV1106 1726 { .compatible = "rockchip,rv1106-gmac", 1727 .data = (ulong)&rv1106_gmac_ops }, 1728 #endif 1729 1730 #ifdef CONFIG_ROCKCHIP_RV1126 1731 { .compatible = "rockchip,rv1126-gmac", 1732 .data = (ulong)&rv1126_gmac_ops }, 1733 #endif 1734 #endif 1735 { } 1736 }; 1737 1738 U_BOOT_DRIVER(eth_gmac_rockchip) = { 1739 .name = "gmac_rockchip", 1740 .id = UCLASS_ETH, 1741 .of_match = rockchip_gmac_ids, 1742 .ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata, 1743 .probe = gmac_rockchip_probe, 1744 .ops = &gmac_rockchip_eth_ops, 1745 .priv_auto_alloc_size = sizeof(struct rockchip_eth_dev), 1746 .platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata), 1747 .flags = DM_FLAG_ALLOC_PRIV_DMA, 1748 }; 1749