1 /* 2 * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Rockchip GMAC ethernet IP driver for U-Boot 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <clk.h> 12 #include <phy.h> 13 #include <syscon.h> 14 #include <asm/io.h> 15 #include <asm/arch/periph.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/hardware.h> 18 #ifdef CONFIG_DWC_ETH_QOS 19 #include <asm/arch/grf_rv1126.h> 20 #include "dwc_eth_qos.h" 21 #else 22 #include <asm/arch/grf_px30.h> 23 #include <asm/arch/grf_rk1808.h> 24 #include <asm/arch/grf_rk322x.h> 25 #include <asm/arch/grf_rk3288.h> 26 #include <asm/arch/grf_rk3308.h> 27 #include <asm/arch/grf_rk3328.h> 28 #include <asm/arch/grf_rk3368.h> 29 #include <asm/arch/grf_rk3399.h> 30 #include <asm/arch/grf_rv1108.h> 31 #include "designware.h" 32 #include <dt-bindings/clock/rk3288-cru.h> 33 #endif 34 #include <dm/pinctrl.h> 35 36 DECLARE_GLOBAL_DATA_PTR; 37 38 struct rockchip_eth_dev { 39 #ifdef CONFIG_DWC_ETH_QOS 40 struct eqos_priv eqos; 41 #else 42 struct dw_eth_dev dw; 43 #endif 44 }; 45 46 /* 47 * Platform data for the gmac 48 * 49 * dw_eth_pdata: Required platform data for designware driver (must be first) 50 */ 51 struct gmac_rockchip_platdata { 52 #ifndef CONFIG_DWC_ETH_QOS 53 struct dw_eth_pdata dw_eth_pdata; 54 #else 55 struct eth_pdata eth_pdata; 56 #endif 57 bool clock_input; 58 int tx_delay; 59 int rx_delay; 60 }; 61 62 struct rk_gmac_ops { 63 #ifdef CONFIG_DWC_ETH_QOS 64 const struct eqos_config config; 65 #endif 66 int (*fix_mac_speed)(struct rockchip_eth_dev *dev); 67 void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata); 68 void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata); 69 }; 70 71 void gmac_set_rgmii(struct udevice *dev, u32 tx_delay, u32 rx_delay) 72 { 73 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 74 struct rk_gmac_ops *ops = 75 (struct rk_gmac_ops *)dev_get_driver_data(dev); 76 77 pdata->tx_delay = tx_delay; 78 pdata->rx_delay = rx_delay; 79 80 ops->set_to_rgmii(pdata); 81 } 82 83 static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) 84 { 85 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 86 const char *string; 87 88 string = dev_read_string(dev, "clock_in_out"); 89 if (!strcmp(string, "input")) 90 pdata->clock_input = true; 91 else 92 pdata->clock_input = false; 93 94 /* Check the new naming-style first... */ 95 pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT); 96 pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT); 97 98 /* ... and fall back to the old naming style or default, if necessary */ 99 if (pdata->tx_delay == -ENOENT) 100 pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30); 101 if (pdata->rx_delay == -ENOENT) 102 pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10); 103 104 #ifdef CONFIG_DWC_ETH_QOS 105 return 0; 106 #else 107 return designware_eth_ofdata_to_platdata(dev); 108 #endif 109 } 110 111 #ifndef CONFIG_DWC_ETH_QOS 112 static int px30_gmac_fix_mac_speed(struct rockchip_eth_dev *dev) 113 { 114 struct dw_eth_dev *priv = &dev->dw; 115 struct px30_grf *grf; 116 struct clk clk_speed; 117 int speed, ret; 118 enum { 119 PX30_GMAC_SPEED_SHIFT = 0x2, 120 PX30_GMAC_SPEED_MASK = BIT(2), 121 PX30_GMAC_SPEED_10M = 0, 122 PX30_GMAC_SPEED_100M = BIT(2), 123 }; 124 125 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 126 &clk_speed); 127 if (ret) 128 return ret; 129 130 switch (priv->phydev->speed) { 131 case 10: 132 speed = PX30_GMAC_SPEED_10M; 133 ret = clk_set_rate(&clk_speed, 2500000); 134 if (ret) 135 return ret; 136 break; 137 case 100: 138 speed = PX30_GMAC_SPEED_100M; 139 ret = clk_set_rate(&clk_speed, 25000000); 140 if (ret) 141 return ret; 142 break; 143 default: 144 debug("Unknown phy speed: %d\n", priv->phydev->speed); 145 return -EINVAL; 146 } 147 148 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 149 rk_clrsetreg(&grf->mac_con1, PX30_GMAC_SPEED_MASK, speed); 150 151 return 0; 152 } 153 154 static int rk1808_gmac_fix_mac_speed(struct rockchip_eth_dev *dev) 155 { 156 struct dw_eth_dev *priv = &dev->dw; 157 struct clk clk_speed; 158 int ret; 159 160 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 161 &clk_speed); 162 if (ret) 163 return ret; 164 165 switch (priv->phydev->speed) { 166 case 10: 167 ret = clk_set_rate(&clk_speed, 2500000); 168 if (ret) 169 return ret; 170 break; 171 case 100: 172 ret = clk_set_rate(&clk_speed, 25000000); 173 if (ret) 174 return ret; 175 break; 176 case 1000: 177 ret = clk_set_rate(&clk_speed, 125000000); 178 if (ret) 179 return ret; 180 break; 181 default: 182 debug("Unknown phy speed: %d\n", priv->phydev->speed); 183 return -EINVAL; 184 } 185 186 return 0; 187 } 188 189 static int rk3228_gmac_fix_mac_speed(struct rockchip_eth_dev *dev) 190 { 191 struct dw_eth_dev *priv = &dev->dw; 192 struct rk322x_grf *grf; 193 int clk; 194 enum { 195 RK3228_GMAC_CLK_SEL_SHIFT = 8, 196 RK3228_GMAC_CLK_SEL_MASK = GENMASK(9, 8), 197 RK3228_GMAC_CLK_SEL_125M = 0 << 8, 198 RK3228_GMAC_CLK_SEL_25M = 3 << 8, 199 RK3228_GMAC_CLK_SEL_2_5M = 2 << 8, 200 }; 201 202 switch (priv->phydev->speed) { 203 case 10: 204 clk = RK3228_GMAC_CLK_SEL_2_5M; 205 break; 206 case 100: 207 clk = RK3228_GMAC_CLK_SEL_25M; 208 break; 209 case 1000: 210 clk = RK3228_GMAC_CLK_SEL_125M; 211 break; 212 default: 213 debug("Unknown phy speed: %d\n", priv->phydev->speed); 214 return -EINVAL; 215 } 216 217 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 218 rk_clrsetreg(&grf->mac_con[1], RK3228_GMAC_CLK_SEL_MASK, clk); 219 220 return 0; 221 } 222 223 static int rk3288_gmac_fix_mac_speed(struct rockchip_eth_dev *dev) 224 { 225 struct dw_eth_dev *priv = &dev->dw; 226 struct rk3288_grf *grf; 227 int clk; 228 229 switch (priv->phydev->speed) { 230 case 10: 231 clk = RK3288_GMAC_CLK_SEL_2_5M; 232 break; 233 case 100: 234 clk = RK3288_GMAC_CLK_SEL_25M; 235 break; 236 case 1000: 237 clk = RK3288_GMAC_CLK_SEL_125M; 238 break; 239 default: 240 debug("Unknown phy speed: %d\n", priv->phydev->speed); 241 return -EINVAL; 242 } 243 244 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 245 rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk); 246 247 return 0; 248 } 249 250 static int rk3308_gmac_fix_mac_speed(struct rockchip_eth_dev *dev) 251 { 252 struct dw_eth_dev *priv = &dev->dw; 253 struct rk3308_grf *grf; 254 struct clk clk_speed; 255 int speed, ret; 256 enum { 257 RK3308_GMAC_SPEED_SHIFT = 0x0, 258 RK3308_GMAC_SPEED_MASK = BIT(0), 259 RK3308_GMAC_SPEED_10M = 0, 260 RK3308_GMAC_SPEED_100M = BIT(0), 261 }; 262 263 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 264 &clk_speed); 265 if (ret) 266 return ret; 267 268 switch (priv->phydev->speed) { 269 case 10: 270 speed = RK3308_GMAC_SPEED_10M; 271 ret = clk_set_rate(&clk_speed, 2500000); 272 if (ret) 273 return ret; 274 break; 275 case 100: 276 speed = RK3308_GMAC_SPEED_100M; 277 ret = clk_set_rate(&clk_speed, 25000000); 278 if (ret) 279 return ret; 280 break; 281 default: 282 debug("Unknown phy speed: %d\n", priv->phydev->speed); 283 return -EINVAL; 284 } 285 286 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 287 rk_clrsetreg(&grf->mac_con0, RK3308_GMAC_SPEED_MASK, speed); 288 289 return 0; 290 } 291 292 static int rk3328_gmac_fix_mac_speed(struct rockchip_eth_dev *dev) 293 { 294 struct dw_eth_dev *priv = &dev->dw; 295 struct rk3328_grf_regs *grf; 296 int clk; 297 enum { 298 RK3328_GMAC_CLK_SEL_SHIFT = 11, 299 RK3328_GMAC_CLK_SEL_MASK = GENMASK(12, 11), 300 RK3328_GMAC_CLK_SEL_125M = 0 << 11, 301 RK3328_GMAC_CLK_SEL_25M = 3 << 11, 302 RK3328_GMAC_CLK_SEL_2_5M = 2 << 11, 303 }; 304 305 switch (priv->phydev->speed) { 306 case 10: 307 clk = RK3328_GMAC_CLK_SEL_2_5M; 308 break; 309 case 100: 310 clk = RK3328_GMAC_CLK_SEL_25M; 311 break; 312 case 1000: 313 clk = RK3328_GMAC_CLK_SEL_125M; 314 break; 315 default: 316 debug("Unknown phy speed: %d\n", priv->phydev->speed); 317 return -EINVAL; 318 } 319 320 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 321 rk_clrsetreg(&grf->mac_con[1], RK3328_GMAC_CLK_SEL_MASK, clk); 322 323 return 0; 324 } 325 326 static int rk3368_gmac_fix_mac_speed(struct rockchip_eth_dev *dev) 327 { 328 struct dw_eth_dev *priv = &dev->dw; 329 struct rk3368_grf *grf; 330 int clk; 331 enum { 332 RK3368_GMAC_CLK_SEL_2_5M = 2 << 4, 333 RK3368_GMAC_CLK_SEL_25M = 3 << 4, 334 RK3368_GMAC_CLK_SEL_125M = 0 << 4, 335 RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4), 336 }; 337 338 switch (priv->phydev->speed) { 339 case 10: 340 clk = RK3368_GMAC_CLK_SEL_2_5M; 341 break; 342 case 100: 343 clk = RK3368_GMAC_CLK_SEL_25M; 344 break; 345 case 1000: 346 clk = RK3368_GMAC_CLK_SEL_125M; 347 break; 348 default: 349 debug("Unknown phy speed: %d\n", priv->phydev->speed); 350 return -EINVAL; 351 } 352 353 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 354 rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk); 355 356 return 0; 357 } 358 359 static int rk3399_gmac_fix_mac_speed(struct rockchip_eth_dev *dev) 360 { 361 struct dw_eth_dev *priv = &dev->dw; 362 struct rk3399_grf_regs *grf; 363 int clk; 364 365 switch (priv->phydev->speed) { 366 case 10: 367 clk = RK3399_GMAC_CLK_SEL_2_5M; 368 break; 369 case 100: 370 clk = RK3399_GMAC_CLK_SEL_25M; 371 break; 372 case 1000: 373 clk = RK3399_GMAC_CLK_SEL_125M; 374 break; 375 default: 376 debug("Unknown phy speed: %d\n", priv->phydev->speed); 377 return -EINVAL; 378 } 379 380 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 381 rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk); 382 383 return 0; 384 } 385 386 static int rv1108_set_rmii_speed(struct rockchip_eth_dev *dev) 387 { 388 struct dw_eth_dev *priv = &dev->dw; 389 struct rv1108_grf *grf; 390 int clk, speed; 391 enum { 392 RV1108_GMAC_SPEED_MASK = BIT(2), 393 RV1108_GMAC_SPEED_10M = 0 << 2, 394 RV1108_GMAC_SPEED_100M = 1 << 2, 395 RV1108_GMAC_CLK_SEL_MASK = BIT(7), 396 RV1108_GMAC_CLK_SEL_2_5M = 0 << 7, 397 RV1108_GMAC_CLK_SEL_25M = 1 << 7, 398 }; 399 400 switch (priv->phydev->speed) { 401 case 10: 402 clk = RV1108_GMAC_CLK_SEL_2_5M; 403 speed = RV1108_GMAC_SPEED_10M; 404 break; 405 case 100: 406 clk = RV1108_GMAC_CLK_SEL_25M; 407 speed = RV1108_GMAC_SPEED_100M; 408 break; 409 default: 410 debug("Unknown phy speed: %d\n", priv->phydev->speed); 411 return -EINVAL; 412 } 413 414 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 415 rk_clrsetreg(&grf->gmac_con0, 416 RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK, 417 clk | speed); 418 419 return 0; 420 } 421 #else 422 static int rv1126_set_rgmii_speed(struct rockchip_eth_dev *dev) 423 { 424 struct eqos_priv *priv = &dev->eqos; 425 struct clk clk_speed; 426 int ret; 427 428 ret = clk_get_by_name(priv->phy->dev, "clk_mac_speed", 429 &clk_speed); 430 if (ret) { 431 printf("%s~(ret=%d):\n", __func__, ret); 432 return ret; 433 } 434 435 switch ( priv->phy->speed) { 436 case 10: 437 ret = clk_set_rate(&clk_speed, 2500000); 438 if (ret) 439 return ret; 440 break; 441 case 100: 442 ret = clk_set_rate(&clk_speed, 25000000); 443 if (ret) 444 return ret; 445 break; 446 case 1000: 447 ret = clk_set_rate(&clk_speed, 125000000); 448 if (ret) 449 return ret; 450 break; 451 default: 452 debug("Unknown phy speed: %d\n", priv->phy->speed); 453 return -EINVAL; 454 } 455 456 return 0; 457 } 458 #endif 459 460 #ifndef CONFIG_DWC_ETH_QOS 461 static void px30_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 462 { 463 struct px30_grf *grf; 464 enum { 465 px30_GMAC_PHY_INTF_SEL_SHIFT = 4, 466 px30_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 6), 467 px30_GMAC_PHY_INTF_SEL_RMII = BIT(6), 468 }; 469 470 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 471 472 rk_clrsetreg(&grf->mac_con1, 473 px30_GMAC_PHY_INTF_SEL_MASK, 474 px30_GMAC_PHY_INTF_SEL_RMII); 475 } 476 477 static void rk1808_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 478 { 479 struct rk1808_grf *grf; 480 enum { 481 RK1808_GMAC_PHY_INTF_SEL_SHIFT = 4, 482 RK1808_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 483 RK1808_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 484 485 RK1808_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 486 RK1808_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 487 RK1808_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 488 489 RK1808_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 490 RK1808_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 491 RK1808_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 492 }; 493 enum { 494 RK1808_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 495 RK1808_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 7), 496 497 RK1808_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 498 RK1808_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 499 }; 500 501 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 502 rk_clrsetreg(&grf->mac_con1, 503 RK1808_GMAC_PHY_INTF_SEL_MASK | 504 RK1808_RXCLK_DLY_ENA_GMAC_MASK | 505 RK1808_TXCLK_DLY_ENA_GMAC_MASK, 506 RK1808_GMAC_PHY_INTF_SEL_RGMII | 507 RK1808_RXCLK_DLY_ENA_GMAC_ENABLE | 508 RK1808_TXCLK_DLY_ENA_GMAC_ENABLE); 509 510 rk_clrsetreg(&grf->mac_con0, 511 RK1808_CLK_RX_DL_CFG_GMAC_MASK | 512 RK1808_CLK_TX_DL_CFG_GMAC_MASK, 513 pdata->rx_delay << RK1808_CLK_RX_DL_CFG_GMAC_SHIFT | 514 pdata->tx_delay << RK1808_CLK_TX_DL_CFG_GMAC_SHIFT); 515 } 516 517 static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 518 { 519 struct rk322x_grf *grf; 520 enum { 521 RK3228_RMII_MODE_SHIFT = 10, 522 RK3228_RMII_MODE_MASK = BIT(10), 523 524 RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4, 525 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 526 RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 527 528 RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 529 RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 530 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 531 532 RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 533 RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 534 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 535 }; 536 enum { 537 RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 538 RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 539 540 RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 541 RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 542 }; 543 544 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 545 rk_clrsetreg(&grf->mac_con[1], 546 RK3228_RMII_MODE_MASK | 547 RK3228_GMAC_PHY_INTF_SEL_MASK | 548 RK3228_RXCLK_DLY_ENA_GMAC_MASK | 549 RK3228_TXCLK_DLY_ENA_GMAC_MASK, 550 RK3228_GMAC_PHY_INTF_SEL_RGMII | 551 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE | 552 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE); 553 554 rk_clrsetreg(&grf->mac_con[0], 555 RK3228_CLK_RX_DL_CFG_GMAC_MASK | 556 RK3228_CLK_TX_DL_CFG_GMAC_MASK, 557 pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT | 558 pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT); 559 } 560 561 static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 562 { 563 struct rk3288_grf *grf; 564 565 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 566 rk_clrsetreg(&grf->soc_con1, 567 RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK, 568 RK3288_GMAC_PHY_INTF_SEL_RGMII); 569 570 rk_clrsetreg(&grf->soc_con3, 571 RK3288_RXCLK_DLY_ENA_GMAC_MASK | 572 RK3288_TXCLK_DLY_ENA_GMAC_MASK | 573 RK3288_CLK_RX_DL_CFG_GMAC_MASK | 574 RK3288_CLK_TX_DL_CFG_GMAC_MASK, 575 RK3288_RXCLK_DLY_ENA_GMAC_ENABLE | 576 RK3288_TXCLK_DLY_ENA_GMAC_ENABLE | 577 pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT | 578 pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT); 579 } 580 581 static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 582 { 583 struct rk3308_grf *grf; 584 enum { 585 RK3308_GMAC_PHY_INTF_SEL_SHIFT = 2, 586 RK3308_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 2), 587 RK3308_GMAC_PHY_INTF_SEL_RMII = BIT(4), 588 }; 589 590 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 591 592 rk_clrsetreg(&grf->mac_con0, 593 RK3308_GMAC_PHY_INTF_SEL_MASK, 594 RK3308_GMAC_PHY_INTF_SEL_RMII); 595 } 596 597 static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 598 { 599 struct rk3328_grf_regs *grf; 600 enum { 601 RK3328_RMII_MODE_SHIFT = 9, 602 RK3328_RMII_MODE_MASK = BIT(9), 603 604 RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4, 605 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 606 RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 607 608 RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 609 RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 610 RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 611 612 RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 613 RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 614 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 615 }; 616 enum { 617 RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 618 RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 619 620 RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 621 RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 622 }; 623 624 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 625 rk_clrsetreg(&grf->mac_con[1], 626 RK3328_RMII_MODE_MASK | 627 RK3328_GMAC_PHY_INTF_SEL_MASK | 628 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 629 RK3328_TXCLK_DLY_ENA_GMAC_MASK, 630 RK3328_GMAC_PHY_INTF_SEL_RGMII | 631 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 632 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE); 633 634 rk_clrsetreg(&grf->mac_con[0], 635 RK3328_CLK_RX_DL_CFG_GMAC_MASK | 636 RK3328_CLK_TX_DL_CFG_GMAC_MASK, 637 pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT | 638 pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT); 639 } 640 641 static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 642 { 643 struct rk3368_grf *grf; 644 enum { 645 RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9, 646 RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9), 647 RK3368_RMII_MODE_MASK = BIT(6), 648 RK3368_RMII_MODE = BIT(6), 649 }; 650 enum { 651 RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15), 652 RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 653 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15), 654 RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7), 655 RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 656 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7), 657 RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8, 658 RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 659 RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0, 660 RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 661 }; 662 663 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 664 rk_clrsetreg(&grf->soc_con15, 665 RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK, 666 RK3368_GMAC_PHY_INTF_SEL_RGMII); 667 668 rk_clrsetreg(&grf->soc_con16, 669 RK3368_RXCLK_DLY_ENA_GMAC_MASK | 670 RK3368_TXCLK_DLY_ENA_GMAC_MASK | 671 RK3368_CLK_RX_DL_CFG_GMAC_MASK | 672 RK3368_CLK_TX_DL_CFG_GMAC_MASK, 673 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE | 674 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE | 675 pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT | 676 pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT); 677 } 678 679 static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 680 { 681 struct rk3399_grf_regs *grf; 682 683 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 684 685 rk_clrsetreg(&grf->soc_con5, 686 RK3399_GMAC_PHY_INTF_SEL_MASK, 687 RK3399_GMAC_PHY_INTF_SEL_RGMII); 688 689 rk_clrsetreg(&grf->soc_con6, 690 RK3399_RXCLK_DLY_ENA_GMAC_MASK | 691 RK3399_TXCLK_DLY_ENA_GMAC_MASK | 692 RK3399_CLK_RX_DL_CFG_GMAC_MASK | 693 RK3399_CLK_TX_DL_CFG_GMAC_MASK, 694 RK3399_RXCLK_DLY_ENA_GMAC_ENABLE | 695 RK3399_TXCLK_DLY_ENA_GMAC_ENABLE | 696 pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT | 697 pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT); 698 } 699 700 static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 701 { 702 struct rv1108_grf *grf; 703 704 enum { 705 RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 706 RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4, 707 }; 708 709 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 710 rk_clrsetreg(&grf->gmac_con0, 711 RV1108_GMAC_PHY_INTF_SEL_MASK, 712 RV1108_GMAC_PHY_INTF_SEL_RMII); 713 } 714 #else 715 static void rv1126_set_to_rmii(struct gmac_rockchip_platdata *pdata) 716 { 717 struct rv1126_grf *grf; 718 719 enum { 720 RV1126_GMAC_PHY_INTF_SEL_SHIFT = 4, 721 RV1126_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 722 RV1126_GMAC_PHY_INTF_SEL_RMII = BIT(6), 723 }; 724 725 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 726 727 rk_clrsetreg(&grf->mac_con0, 728 RV1126_GMAC_PHY_INTF_SEL_MASK, 729 RV1126_GMAC_PHY_INTF_SEL_RMII); 730 } 731 732 static void rv1126_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 733 { 734 struct rv1126_grf *grf; 735 736 enum { 737 RV1126_GMAC_PHY_INTF_SEL_SHIFT = 4, 738 RV1126_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 739 RV1126_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 740 741 RV1126_RXCLK_M1_DLY_ENA_GMAC_MASK = BIT(3), 742 RV1126_RXCLK_M1_DLY_ENA_GMAC_DISABLE = 0, 743 RV1126_RXCLK_M1_DLY_ENA_GMAC_ENABLE = BIT(3), 744 745 RV1126_TXCLK_M1_DLY_ENA_GMAC_MASK = BIT(2), 746 RV1126_TXCLK_M1_DLY_ENA_GMAC_DISABLE = 0, 747 RV1126_TXCLK_M1_DLY_ENA_GMAC_ENABLE = BIT(2), 748 749 RV1126_RXCLK_M0_DLY_ENA_GMAC_MASK = BIT(1), 750 RV1126_RXCLK_M0_DLY_ENA_GMAC_DISABLE = 0, 751 RV1126_RXCLK_M0_DLY_ENA_GMAC_ENABLE = BIT(1), 752 753 RV1126_TXCLK_M0_DLY_ENA_GMAC_MASK = BIT(0), 754 RV1126_TXCLK_M0_DLY_ENA_GMAC_DISABLE = 0, 755 RV1126_TXCLK_M0_DLY_ENA_GMAC_ENABLE = BIT(0), 756 }; 757 enum { 758 RV1126_M0_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 759 RV1126_M0_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 760 761 RV1126_M0_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 762 RV1126_M0_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 763 }; 764 enum { 765 RV1126_M1_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 766 RV1126_M1_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 767 768 RV1126_M1_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 769 RV1126_M1_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 770 }; 771 772 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 773 774 rk_clrsetreg(&grf->mac_con0, 775 RV1126_TXCLK_M0_DLY_ENA_GMAC_MASK | 776 RV1126_RXCLK_M0_DLY_ENA_GMAC_MASK | 777 RV1126_TXCLK_M1_DLY_ENA_GMAC_MASK | 778 RV1126_RXCLK_M1_DLY_ENA_GMAC_MASK | 779 RV1126_GMAC_PHY_INTF_SEL_MASK, 780 RV1126_TXCLK_M0_DLY_ENA_GMAC_ENABLE | 781 RV1126_RXCLK_M0_DLY_ENA_GMAC_ENABLE | 782 RV1126_TXCLK_M1_DLY_ENA_GMAC_ENABLE | 783 RV1126_RXCLK_M1_DLY_ENA_GMAC_ENABLE | 784 RV1126_GMAC_PHY_INTF_SEL_RGMII); 785 786 rk_clrsetreg(&grf->mac_con1, 787 RV1126_M0_CLK_RX_DL_CFG_GMAC_MASK | 788 RV1126_M0_CLK_TX_DL_CFG_GMAC_MASK, 789 pdata->rx_delay << RV1126_M0_CLK_RX_DL_CFG_GMAC_SHIFT | 790 pdata->tx_delay << RV1126_M0_CLK_TX_DL_CFG_GMAC_SHIFT); 791 792 rk_clrsetreg(&grf->mac_con2, 793 RV1126_M1_CLK_RX_DL_CFG_GMAC_MASK | 794 RV1126_M1_CLK_TX_DL_CFG_GMAC_MASK, 795 pdata->rx_delay << RV1126_M1_CLK_RX_DL_CFG_GMAC_SHIFT | 796 pdata->tx_delay << RV1126_M1_CLK_TX_DL_CFG_GMAC_SHIFT); 797 } 798 #endif 799 800 static int gmac_rockchip_probe(struct udevice *dev) 801 { 802 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 803 struct rk_gmac_ops *ops = 804 (struct rk_gmac_ops *)dev_get_driver_data(dev); 805 #ifdef CONFIG_DWC_ETH_QOS 806 struct eqos_config *config; 807 #else 808 struct dw_eth_pdata *dw_pdata; 809 #endif 810 struct eth_pdata *eth_pdata; 811 struct clk clk; 812 ulong rate; 813 int ret; 814 815 #ifdef CONFIG_DWC_ETH_QOS 816 eth_pdata = &pdata->eth_pdata; 817 config = (struct eqos_config *)&ops->config; 818 eth_pdata->phy_interface = config->ops->eqos_get_interface(dev); 819 #else 820 dw_pdata = &pdata->dw_eth_pdata; 821 eth_pdata = &dw_pdata->eth_pdata; 822 #endif 823 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 824 ret = clk_set_defaults(dev); 825 if (ret) 826 debug("%s clk_set_defaults failed %d\n", __func__, ret); 827 828 ret = clk_get_by_index(dev, 0, &clk); 829 if (ret) 830 return ret; 831 832 switch (eth_pdata->phy_interface) { 833 case PHY_INTERFACE_MODE_RGMII: 834 /* 835 * If the gmac clock is from internal pll, need to set and 836 * check the return value for gmac clock at RGMII mode. If 837 * the gmac clock is from external source, the clock rate 838 * is not set, because of it is bypassed. 839 */ 840 if (!pdata->clock_input) { 841 rate = clk_set_rate(&clk, 125000000); 842 if (rate != 125000000) 843 return -EINVAL; 844 } 845 846 /* Set to RGMII mode */ 847 if (ops->set_to_rgmii) 848 ops->set_to_rgmii(pdata); 849 else 850 return -EPERM; 851 852 break; 853 case PHY_INTERFACE_MODE_RMII: 854 /* The commet is the same as RGMII mode */ 855 if (!pdata->clock_input) { 856 rate = clk_set_rate(&clk, 50000000); 857 if (rate != 50000000) 858 return -EINVAL; 859 } 860 861 /* Set to RMII mode */ 862 if (ops->set_to_rmii) 863 ops->set_to_rmii(pdata); 864 else 865 return -EPERM; 866 867 break; 868 default: 869 debug("NO interface defined!\n"); 870 return -ENXIO; 871 } 872 873 #ifdef CONFIG_DWC_ETH_QOS 874 return eqos_probe(dev); 875 #else 876 return designware_eth_probe(dev); 877 #endif 878 } 879 880 static int gmac_rockchip_eth_write_hwaddr(struct udevice *dev) 881 { 882 #if defined(CONFIG_DWC_ETH_QOS) 883 return eqos_write_hwaddr(dev); 884 #else 885 return designware_eth_write_hwaddr(dev); 886 #endif 887 } 888 889 static int gmac_rockchip_eth_free_pkt(struct udevice *dev, uchar *packet, 890 int length) 891 { 892 #ifdef CONFIG_DWC_ETH_QOS 893 return eqos_free_pkt(dev, packet, length); 894 #else 895 return designware_eth_free_pkt(dev, packet, length); 896 #endif 897 } 898 899 static int gmac_rockchip_eth_send(struct udevice *dev, void *packet, 900 int length) 901 { 902 #ifdef CONFIG_DWC_ETH_QOS 903 return eqos_send(dev, packet, length); 904 #else 905 return designware_eth_send(dev, packet, length); 906 #endif 907 } 908 909 static int gmac_rockchip_eth_recv(struct udevice *dev, int flags, 910 uchar **packetp) 911 { 912 #ifdef CONFIG_DWC_ETH_QOS 913 return eqos_recv(dev, flags, packetp); 914 #else 915 return designware_eth_recv(dev, flags, packetp); 916 #endif 917 } 918 919 static int gmac_rockchip_eth_start(struct udevice *dev) 920 { 921 struct rockchip_eth_dev *priv = dev_get_priv(dev); 922 struct rk_gmac_ops *ops = 923 (struct rk_gmac_ops *)dev_get_driver_data(dev); 924 #ifndef CONFIG_DWC_ETH_QOS 925 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 926 struct dw_eth_pdata *dw_pdata; 927 struct eth_pdata *eth_pdata; 928 #endif 929 int ret; 930 931 #ifdef CONFIG_DWC_ETH_QOS 932 ret = eqos_init(dev); 933 #else 934 dw_pdata = &pdata->dw_eth_pdata; 935 eth_pdata = &dw_pdata->eth_pdata; 936 ret = designware_eth_init((struct dw_eth_dev *)priv, 937 eth_pdata->enetaddr); 938 #endif 939 if (ret) 940 return ret; 941 ret = ops->fix_mac_speed(priv); 942 if (ret) 943 return ret; 944 945 #ifdef CONFIG_DWC_ETH_QOS 946 eqos_enable(dev); 947 #else 948 ret = designware_eth_enable((struct dw_eth_dev *)priv); 949 if (ret) 950 return ret; 951 #endif 952 953 return 0; 954 } 955 956 static void gmac_rockchip_eth_stop(struct udevice *dev) 957 { 958 #ifdef CONFIG_DWC_ETH_QOS 959 eqos_stop(dev); 960 #else 961 designware_eth_stop(dev); 962 #endif 963 } 964 965 const struct eth_ops gmac_rockchip_eth_ops = { 966 .start = gmac_rockchip_eth_start, 967 .send = gmac_rockchip_eth_send, 968 .recv = gmac_rockchip_eth_recv, 969 .free_pkt = gmac_rockchip_eth_free_pkt, 970 .stop = gmac_rockchip_eth_stop, 971 .write_hwaddr = gmac_rockchip_eth_write_hwaddr, 972 }; 973 974 #ifndef CONFIG_DWC_ETH_QOS 975 const struct rk_gmac_ops px30_gmac_ops = { 976 .fix_mac_speed = px30_gmac_fix_mac_speed, 977 .set_to_rmii = px30_gmac_set_to_rmii, 978 }; 979 980 const struct rk_gmac_ops rk1808_gmac_ops = { 981 .fix_mac_speed = rk1808_gmac_fix_mac_speed, 982 .set_to_rgmii = rk1808_gmac_set_to_rgmii, 983 }; 984 985 const struct rk_gmac_ops rk3228_gmac_ops = { 986 .fix_mac_speed = rk3228_gmac_fix_mac_speed, 987 .set_to_rgmii = rk3228_gmac_set_to_rgmii, 988 }; 989 990 const struct rk_gmac_ops rk3288_gmac_ops = { 991 .fix_mac_speed = rk3288_gmac_fix_mac_speed, 992 .set_to_rgmii = rk3288_gmac_set_to_rgmii, 993 }; 994 995 const struct rk_gmac_ops rk3308_gmac_ops = { 996 .fix_mac_speed = rk3308_gmac_fix_mac_speed, 997 .set_to_rmii = rk3308_gmac_set_to_rmii, 998 }; 999 1000 const struct rk_gmac_ops rk3328_gmac_ops = { 1001 .fix_mac_speed = rk3328_gmac_fix_mac_speed, 1002 .set_to_rgmii = rk3328_gmac_set_to_rgmii, 1003 }; 1004 1005 const struct rk_gmac_ops rk3368_gmac_ops = { 1006 .fix_mac_speed = rk3368_gmac_fix_mac_speed, 1007 .set_to_rgmii = rk3368_gmac_set_to_rgmii, 1008 }; 1009 1010 const struct rk_gmac_ops rk3399_gmac_ops = { 1011 .fix_mac_speed = rk3399_gmac_fix_mac_speed, 1012 .set_to_rgmii = rk3399_gmac_set_to_rgmii, 1013 }; 1014 1015 const struct rk_gmac_ops rv1108_gmac_ops = { 1016 .fix_mac_speed = rv1108_set_rmii_speed, 1017 .set_to_rmii = rv1108_gmac_set_to_rmii, 1018 }; 1019 #else 1020 const struct rk_gmac_ops rv1126_gmac_ops = { 1021 .config = { 1022 .reg_access_always_ok = false, 1023 .mdio_wait = 10000, 1024 .swr_wait = 200, 1025 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED, 1026 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_100_150, 1027 .ops = &eqos_rockchip_ops 1028 }, 1029 1030 .fix_mac_speed = rv1126_set_rgmii_speed, 1031 .set_to_rgmii = rv1126_set_to_rgmii, 1032 .set_to_rmii = rv1126_set_to_rmii, 1033 }; 1034 #endif 1035 1036 static const struct udevice_id rockchip_gmac_ids[] = { 1037 #ifndef CONFIG_DWC_ETH_QOS 1038 { .compatible = "rockchip,px30-gmac", 1039 .data = (ulong)&px30_gmac_ops }, 1040 { .compatible = "rockchip,rk1808-gmac", 1041 .data = (ulong)&rk1808_gmac_ops }, 1042 { .compatible = "rockchip,rk3228-gmac", 1043 .data = (ulong)&rk3228_gmac_ops }, 1044 { .compatible = "rockchip,rk3288-gmac", 1045 .data = (ulong)&rk3288_gmac_ops }, 1046 { .compatible = "rockchip,rk3308-mac", 1047 .data = (ulong)&rk3308_gmac_ops }, 1048 { .compatible = "rockchip,rk3328-gmac", 1049 .data = (ulong)&rk3328_gmac_ops }, 1050 { .compatible = "rockchip,rk3368-gmac", 1051 .data = (ulong)&rk3368_gmac_ops }, 1052 { .compatible = "rockchip,rk3399-gmac", 1053 .data = (ulong)&rk3399_gmac_ops }, 1054 { .compatible = "rockchip,rv1108-gmac", 1055 .data = (ulong)&rv1108_gmac_ops }, 1056 #else 1057 { .compatible = "rockchip,rv1126-gmac", 1058 .data = (ulong)&rv1126_gmac_ops }, 1059 #endif 1060 { } 1061 }; 1062 1063 U_BOOT_DRIVER(eth_gmac_rockchip) = { 1064 .name = "gmac_rockchip", 1065 .id = UCLASS_ETH, 1066 .of_match = rockchip_gmac_ids, 1067 .ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata, 1068 .probe = gmac_rockchip_probe, 1069 .ops = &gmac_rockchip_eth_ops, 1070 .priv_auto_alloc_size = sizeof(struct rockchip_eth_dev), 1071 .platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata), 1072 .flags = DM_FLAG_ALLOC_PRIV_DMA, 1073 }; 1074