1 /* 2 * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Rockchip GMAC ethernet IP driver for U-Boot 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <clk.h> 12 #include <phy.h> 13 #include <reset.h> 14 #include <syscon.h> 15 #include <asm/io.h> 16 #include <asm/arch/periph.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/hardware.h> 19 #ifdef CONFIG_DWC_ETH_QOS 20 #include <asm/arch/grf_rk3568.h> 21 #include <asm/arch/grf_rk3588.h> 22 #include <asm/arch/grf_rv1106.h> 23 #include <asm/arch/grf_rv1126.h> 24 #include "dwc_eth_qos.h" 25 #else 26 #include <asm/arch/grf_px30.h> 27 #include <asm/arch/grf_rk1808.h> 28 #include <asm/arch/grf_rk322x.h> 29 #include <asm/arch/grf_rk3288.h> 30 #include <asm/arch/grf_rk3308.h> 31 #include <asm/arch/grf_rk3328.h> 32 #include <asm/arch/grf_rk3368.h> 33 #include <asm/arch/grf_rk3399.h> 34 #include <asm/arch/grf_rv1108.h> 35 #include "designware.h" 36 #include <dt-bindings/clock/rk3288-cru.h> 37 #endif 38 #include <dm/pinctrl.h> 39 #include <dm/of_access.h> 40 41 DECLARE_GLOBAL_DATA_PTR; 42 43 struct rockchip_eth_dev { 44 #ifdef CONFIG_DWC_ETH_QOS 45 struct eqos_priv eqos; 46 #else 47 struct dw_eth_dev dw; 48 #endif 49 int phy_interface; 50 }; 51 52 /* 53 * Platform data for the gmac 54 * 55 * dw_eth_pdata: Required platform data for designware driver (must be first) 56 */ 57 struct gmac_rockchip_platdata { 58 #ifndef CONFIG_DWC_ETH_QOS 59 struct dw_eth_pdata dw_eth_pdata; 60 #else 61 struct eth_pdata eth_pdata; 62 #endif 63 struct reset_ctl phy_reset; 64 bool integrated_phy; 65 bool clock_input; 66 int phy_interface; 67 int tx_delay; 68 int rx_delay; 69 int bus_id; 70 }; 71 72 struct rk_gmac_ops { 73 #ifdef CONFIG_DWC_ETH_QOS 74 const struct eqos_config config; 75 #endif 76 int (*fix_mac_speed)(struct gmac_rockchip_platdata *pdata, 77 struct rockchip_eth_dev *dev); 78 void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata); 79 void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata); 80 void (*set_clock_selection)(struct gmac_rockchip_platdata *pdata); 81 void (*integrated_phy_powerup)(struct gmac_rockchip_platdata *pdata); 82 }; 83 84 #ifdef CONFIG_DWC_ETH_QOS 85 static const struct eqos_config eqos_rockchip_config = { 86 .reg_access_always_ok = false, 87 .mdio_wait = 10000, 88 .swr_wait = 200, 89 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED, 90 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_100_150, 91 .ops = &eqos_rockchip_ops, 92 }; 93 #endif 94 95 void gmac_set_rgmii(struct udevice *dev, u32 tx_delay, u32 rx_delay) 96 { 97 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 98 struct rk_gmac_ops *ops = 99 (struct rk_gmac_ops *)dev_get_driver_data(dev); 100 101 pdata->tx_delay = tx_delay; 102 pdata->rx_delay = rx_delay; 103 104 ops->set_to_rgmii(pdata); 105 } 106 107 static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) 108 { 109 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 110 struct ofnode_phandle_args args; 111 struct udevice *phydev; 112 const char *string; 113 int ret; 114 115 string = dev_read_string(dev, "clock_in_out"); 116 if (!strcmp(string, "input")) 117 pdata->clock_input = true; 118 else 119 pdata->clock_input = false; 120 121 /* If phy-handle property is passed from DT, use it as the PHY */ 122 ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &args); 123 if (ret) { 124 debug("Cannot get phy phandle: ret=%d\n", ret); 125 pdata->integrated_phy = dev_read_bool(dev, "phy-is-integrated"); 126 } else { 127 debug("Found phy-handle subnode\n"); 128 pdata->integrated_phy = ofnode_read_bool(args.node, 129 "phy-is-integrated"); 130 } 131 132 if (pdata->integrated_phy) { 133 ret = reset_get_by_name(dev, "mac-phy", &pdata->phy_reset); 134 if (ret) { 135 ret = uclass_get_device_by_ofnode(UCLASS_ETH_PHY, args.node, &phydev); 136 if (ret) { 137 debug("Get phydev by ofnode failed: err=%d\n", ret); 138 return ret; 139 } 140 141 ret = reset_get_by_index(phydev, 0, &pdata->phy_reset); 142 if (ret) { 143 debug("No PHY reset control found: ret=%d\n", ret); 144 return ret; 145 } 146 } 147 } 148 149 /* Check the new naming-style first... */ 150 pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT); 151 pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT); 152 153 /* ... and fall back to the old naming style or default, if necessary */ 154 if (pdata->tx_delay == -ENOENT) 155 pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30); 156 if (pdata->rx_delay == -ENOENT) 157 pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10); 158 159 #ifdef CONFIG_DWC_ETH_QOS 160 return 0; 161 #else 162 return designware_eth_ofdata_to_platdata(dev); 163 #endif 164 } 165 166 #ifndef CONFIG_DWC_ETH_QOS 167 static int px30_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 168 struct rockchip_eth_dev *dev) 169 { 170 struct dw_eth_dev *priv = &dev->dw; 171 struct px30_grf *grf; 172 struct clk clk_speed; 173 int speed, ret; 174 enum { 175 PX30_GMAC_SPEED_SHIFT = 0x2, 176 PX30_GMAC_SPEED_MASK = BIT(2), 177 PX30_GMAC_SPEED_10M = 0, 178 PX30_GMAC_SPEED_100M = BIT(2), 179 }; 180 181 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 182 &clk_speed); 183 if (ret) 184 return ret; 185 186 switch (priv->phydev->speed) { 187 case 10: 188 speed = PX30_GMAC_SPEED_10M; 189 ret = clk_set_rate(&clk_speed, 2500000); 190 if (ret) 191 return ret; 192 break; 193 case 100: 194 speed = PX30_GMAC_SPEED_100M; 195 ret = clk_set_rate(&clk_speed, 25000000); 196 if (ret) 197 return ret; 198 break; 199 default: 200 debug("Unknown phy speed: %d\n", priv->phydev->speed); 201 return -EINVAL; 202 } 203 204 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 205 rk_clrsetreg(&grf->mac_con1, PX30_GMAC_SPEED_MASK, speed); 206 207 return 0; 208 } 209 210 static int rk1808_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 211 struct rockchip_eth_dev *dev) 212 { 213 struct dw_eth_dev *priv = &dev->dw; 214 struct clk clk_speed; 215 int ret; 216 217 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 218 &clk_speed); 219 if (ret) 220 return ret; 221 222 switch (priv->phydev->speed) { 223 case 10: 224 ret = clk_set_rate(&clk_speed, 2500000); 225 if (ret) 226 return ret; 227 break; 228 case 100: 229 ret = clk_set_rate(&clk_speed, 25000000); 230 if (ret) 231 return ret; 232 break; 233 case 1000: 234 ret = clk_set_rate(&clk_speed, 125000000); 235 if (ret) 236 return ret; 237 break; 238 default: 239 debug("Unknown phy speed: %d\n", priv->phydev->speed); 240 return -EINVAL; 241 } 242 243 return 0; 244 } 245 246 static int rk3228_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 247 struct rockchip_eth_dev *dev) 248 { 249 struct dw_eth_dev *priv = &dev->dw; 250 struct rk322x_grf *grf; 251 int clk; 252 enum { 253 RK3228_GMAC_CLK_SEL_SHIFT = 8, 254 RK3228_GMAC_CLK_SEL_MASK = GENMASK(9, 8), 255 RK3228_GMAC_CLK_SEL_125M = 0 << 8, 256 RK3228_GMAC_CLK_SEL_25M = 3 << 8, 257 RK3228_GMAC_CLK_SEL_2_5M = 2 << 8, 258 259 RK3228_GMAC_RMII_CLK_MASK = BIT(7), 260 RK3228_GMAC_RMII_CLK_2_5M = 0, 261 RK3228_GMAC_RMII_CLK_25M = BIT(7), 262 263 RK3228_GMAC_RMII_SPEED_MASK = BIT(2), 264 RK3228_GMAC_RMII_SPEED_10 = 0, 265 RK3228_GMAC_RMII_SPEED_100 = BIT(2), 266 }; 267 268 switch (priv->phydev->speed) { 269 case 10: 270 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 271 (RK3228_GMAC_RMII_CLK_2_5M | RK3228_GMAC_RMII_SPEED_10) : 272 RK3228_GMAC_CLK_SEL_2_5M; 273 break; 274 case 100: 275 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 276 (RK3228_GMAC_RMII_CLK_25M | RK3228_GMAC_RMII_SPEED_100) : 277 RK3228_GMAC_CLK_SEL_25M; 278 break; 279 case 1000: 280 clk = RK3228_GMAC_CLK_SEL_125M; 281 break; 282 default: 283 debug("Unknown phy speed: %d\n", priv->phydev->speed); 284 return -EINVAL; 285 } 286 287 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 288 rk_clrsetreg(&grf->mac_con[1], 289 RK3228_GMAC_CLK_SEL_MASK | 290 RK3228_GMAC_RMII_CLK_MASK | 291 RK3228_GMAC_RMII_SPEED_MASK, 292 clk); 293 294 return 0; 295 } 296 297 static int rk3288_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 298 struct rockchip_eth_dev *dev) 299 { 300 struct dw_eth_dev *priv = &dev->dw; 301 struct rk3288_grf *grf; 302 int clk; 303 304 switch (priv->phydev->speed) { 305 case 10: 306 clk = RK3288_GMAC_CLK_SEL_2_5M; 307 break; 308 case 100: 309 clk = RK3288_GMAC_CLK_SEL_25M; 310 break; 311 case 1000: 312 clk = RK3288_GMAC_CLK_SEL_125M; 313 break; 314 default: 315 debug("Unknown phy speed: %d\n", priv->phydev->speed); 316 return -EINVAL; 317 } 318 319 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 320 rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk); 321 322 return 0; 323 } 324 325 static int rk3308_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 326 struct rockchip_eth_dev *dev) 327 { 328 struct dw_eth_dev *priv = &dev->dw; 329 struct rk3308_grf *grf; 330 struct clk clk_speed; 331 int speed, ret; 332 enum { 333 RK3308_GMAC_SPEED_SHIFT = 0x0, 334 RK3308_GMAC_SPEED_MASK = BIT(0), 335 RK3308_GMAC_SPEED_10M = 0, 336 RK3308_GMAC_SPEED_100M = BIT(0), 337 }; 338 339 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 340 &clk_speed); 341 if (ret) 342 return ret; 343 344 switch (priv->phydev->speed) { 345 case 10: 346 speed = RK3308_GMAC_SPEED_10M; 347 ret = clk_set_rate(&clk_speed, 2500000); 348 if (ret) 349 return ret; 350 break; 351 case 100: 352 speed = RK3308_GMAC_SPEED_100M; 353 ret = clk_set_rate(&clk_speed, 25000000); 354 if (ret) 355 return ret; 356 break; 357 default: 358 debug("Unknown phy speed: %d\n", priv->phydev->speed); 359 return -EINVAL; 360 } 361 362 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 363 rk_clrsetreg(&grf->mac_con0, RK3308_GMAC_SPEED_MASK, speed); 364 365 return 0; 366 } 367 368 static int rk3328_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 369 struct rockchip_eth_dev *dev) 370 { 371 struct dw_eth_dev *priv = &dev->dw; 372 struct rk3328_grf_regs *grf; 373 int clk; 374 enum { 375 RK3328_GMAC_CLK_SEL_SHIFT = 11, 376 RK3328_GMAC_CLK_SEL_MASK = GENMASK(12, 11), 377 RK3328_GMAC_CLK_SEL_125M = 0 << 11, 378 RK3328_GMAC_CLK_SEL_25M = 3 << 11, 379 RK3328_GMAC_CLK_SEL_2_5M = 2 << 11, 380 381 RK3328_GMAC_RMII_CLK_MASK = BIT(7), 382 RK3328_GMAC_RMII_CLK_2_5M = 0, 383 RK3328_GMAC_RMII_CLK_25M = BIT(7), 384 385 RK3328_GMAC_RMII_SPEED_MASK = BIT(2), 386 RK3328_GMAC_RMII_SPEED_10 = 0, 387 RK3328_GMAC_RMII_SPEED_100 = BIT(2), 388 }; 389 390 switch (priv->phydev->speed) { 391 case 10: 392 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 393 (RK3328_GMAC_RMII_CLK_2_5M | RK3328_GMAC_RMII_SPEED_10) : 394 RK3328_GMAC_CLK_SEL_2_5M; 395 break; 396 case 100: 397 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 398 (RK3328_GMAC_RMII_CLK_25M | RK3328_GMAC_RMII_SPEED_100) : 399 RK3328_GMAC_CLK_SEL_25M; 400 break; 401 case 1000: 402 clk = RK3328_GMAC_CLK_SEL_125M; 403 break; 404 default: 405 debug("Unknown phy speed: %d\n", priv->phydev->speed); 406 return -EINVAL; 407 } 408 409 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 410 rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1], 411 RK3328_GMAC_CLK_SEL_MASK | 412 RK3328_GMAC_RMII_CLK_MASK | 413 RK3328_GMAC_RMII_SPEED_MASK, 414 clk); 415 416 return 0; 417 } 418 419 static int rk3368_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 420 struct rockchip_eth_dev *dev) 421 { 422 struct dw_eth_dev *priv = &dev->dw; 423 struct rk3368_grf *grf; 424 int clk; 425 enum { 426 RK3368_GMAC_CLK_SEL_2_5M = 2 << 4, 427 RK3368_GMAC_CLK_SEL_25M = 3 << 4, 428 RK3368_GMAC_CLK_SEL_125M = 0 << 4, 429 RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4), 430 }; 431 432 switch (priv->phydev->speed) { 433 case 10: 434 clk = RK3368_GMAC_CLK_SEL_2_5M; 435 break; 436 case 100: 437 clk = RK3368_GMAC_CLK_SEL_25M; 438 break; 439 case 1000: 440 clk = RK3368_GMAC_CLK_SEL_125M; 441 break; 442 default: 443 debug("Unknown phy speed: %d\n", priv->phydev->speed); 444 return -EINVAL; 445 } 446 447 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 448 rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk); 449 450 return 0; 451 } 452 453 static int rk3399_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 454 struct rockchip_eth_dev *dev) 455 { 456 struct dw_eth_dev *priv = &dev->dw; 457 struct rk3399_grf_regs *grf; 458 int clk; 459 460 switch (priv->phydev->speed) { 461 case 10: 462 clk = RK3399_GMAC_CLK_SEL_2_5M; 463 break; 464 case 100: 465 clk = RK3399_GMAC_CLK_SEL_25M; 466 break; 467 case 1000: 468 clk = RK3399_GMAC_CLK_SEL_125M; 469 break; 470 default: 471 debug("Unknown phy speed: %d\n", priv->phydev->speed); 472 return -EINVAL; 473 } 474 475 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 476 rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk); 477 478 return 0; 479 } 480 481 static int rv1108_set_rmii_speed(struct gmac_rockchip_platdata *pdata, 482 struct rockchip_eth_dev *dev) 483 { 484 struct dw_eth_dev *priv = &dev->dw; 485 struct rv1108_grf *grf; 486 int clk, speed; 487 enum { 488 RV1108_GMAC_SPEED_MASK = BIT(2), 489 RV1108_GMAC_SPEED_10M = 0 << 2, 490 RV1108_GMAC_SPEED_100M = 1 << 2, 491 RV1108_GMAC_CLK_SEL_MASK = BIT(7), 492 RV1108_GMAC_CLK_SEL_2_5M = 0 << 7, 493 RV1108_GMAC_CLK_SEL_25M = 1 << 7, 494 }; 495 496 switch (priv->phydev->speed) { 497 case 10: 498 clk = RV1108_GMAC_CLK_SEL_2_5M; 499 speed = RV1108_GMAC_SPEED_10M; 500 break; 501 case 100: 502 clk = RV1108_GMAC_CLK_SEL_25M; 503 speed = RV1108_GMAC_SPEED_100M; 504 break; 505 default: 506 debug("Unknown phy speed: %d\n", priv->phydev->speed); 507 return -EINVAL; 508 } 509 510 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 511 rk_clrsetreg(&grf->gmac_con0, 512 RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK, 513 clk | speed); 514 515 return 0; 516 } 517 #else 518 static int rk3588_set_rgmii_speed(struct gmac_rockchip_platdata *pdata, 519 struct rockchip_eth_dev *dev) 520 { 521 struct eqos_priv *priv = &dev->eqos; 522 struct rk3588_php_grf *php_grf; 523 unsigned int div, div_mask; 524 525 enum { 526 RK3588_GMAC_CLK_RGMII_DIV_SHIFT = 2, 527 RK3588_GMAC_CLK_RGMII_DIV_MASK = GENMASK(3, 2), 528 RK3588_GMAC_CLK_RGMII_DIV1 = 0, 529 RK3588_GMAC_CLK_RGMII_DIV5 = GENMASK(3, 2), 530 RK3588_GMAC_CLK_RGMII_DIV50 = BIT(3), 531 RK3588_GMA_CLK_RMII_DIV2 = BIT(2), 532 RK3588_GMAC_CLK_RMII_DIV20 = 0, 533 }; 534 535 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 536 537 switch (priv->phy->speed) { 538 case 10: 539 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) 540 div = RK3588_GMAC_CLK_RMII_DIV20; 541 else 542 div = RK3588_GMAC_CLK_RGMII_DIV50; 543 break; 544 case 100: 545 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) 546 div = RK3588_GMA_CLK_RMII_DIV2; 547 else 548 div = RK3588_GMAC_CLK_RGMII_DIV5; 549 break; 550 case 1000: 551 if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII) 552 div = RK3588_GMAC_CLK_RGMII_DIV1; 553 else 554 return -EINVAL; 555 break; 556 default: 557 debug("Unknown phy speed: %d\n", priv->phy->speed); 558 return -EINVAL; 559 } 560 561 if (pdata->bus_id == 1) { 562 div <<= 5; 563 div_mask = RK3588_GMAC_CLK_RGMII_DIV_MASK << 5; 564 } 565 566 rk_clrsetreg(&php_grf->clk_con1, div_mask, div); 567 568 return 0; 569 } 570 571 static int rv1106_set_rmii_speed(struct gmac_rockchip_platdata *pdata, 572 struct rockchip_eth_dev *dev) 573 { 574 struct eqos_priv *priv = &dev->eqos; 575 struct rv1106_grf *grf; 576 unsigned int div; 577 578 enum { 579 RV1106_GMAC_CLK_RMII_DIV_SHIFT = 2, 580 RV1106_GMAC_CLK_RMII_DIV_MASK = GENMASK(3, 2), 581 RV1106_GMAC_CLK_RMII_DIV2 = BIT(2), 582 RV1106_GMAC_CLK_RMII_DIV20 = 0, 583 }; 584 585 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 586 587 switch (priv->phy->speed) { 588 case 10: 589 div = RV1106_GMAC_CLK_RMII_DIV20; 590 break; 591 case 100: 592 div = RV1106_GMAC_CLK_RMII_DIV2; 593 break; 594 default: 595 debug("Unknown phy speed: %d\n", priv->phy->speed); 596 return -EINVAL; 597 } 598 599 rk_clrsetreg(&grf->gmac_clk_con, RV1106_GMAC_CLK_RMII_DIV_MASK, div); 600 601 return 0; 602 } 603 604 static int rv1126_set_rgmii_speed(struct gmac_rockchip_platdata *pdata, 605 struct rockchip_eth_dev *dev) 606 { 607 struct eqos_priv *priv = &dev->eqos; 608 struct clk clk_speed; 609 int ret; 610 611 ret = clk_get_by_name(priv->phy->dev, "clk_mac_speed", 612 &clk_speed); 613 if (ret) { 614 printf("%s can't get clk_mac_speed clock (ret=%d):\n", 615 __func__, ret); 616 return ret; 617 } 618 619 switch ( priv->phy->speed) { 620 case 10: 621 ret = clk_set_rate(&clk_speed, 2500000); 622 if (ret) 623 return ret; 624 break; 625 case 100: 626 ret = clk_set_rate(&clk_speed, 25000000); 627 if (ret) 628 return ret; 629 break; 630 case 1000: 631 ret = clk_set_rate(&clk_speed, 125000000); 632 if (ret) 633 return ret; 634 break; 635 default: 636 debug("Unknown phy speed: %d\n", priv->phy->speed); 637 return -EINVAL; 638 } 639 640 return 0; 641 } 642 #endif 643 644 #ifndef CONFIG_DWC_ETH_QOS 645 static void px30_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 646 { 647 struct px30_grf *grf; 648 enum { 649 px30_GMAC_PHY_INTF_SEL_SHIFT = 4, 650 px30_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 6), 651 px30_GMAC_PHY_INTF_SEL_RMII = BIT(6), 652 }; 653 654 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 655 656 rk_clrsetreg(&grf->mac_con1, 657 px30_GMAC_PHY_INTF_SEL_MASK, 658 px30_GMAC_PHY_INTF_SEL_RMII); 659 } 660 661 static void rk1808_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 662 { 663 struct rk1808_grf *grf; 664 enum { 665 RK1808_GMAC_PHY_INTF_SEL_SHIFT = 4, 666 RK1808_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 667 RK1808_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 668 669 RK1808_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 670 RK1808_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 671 RK1808_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 672 673 RK1808_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 674 RK1808_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 675 RK1808_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 676 }; 677 enum { 678 RK1808_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 679 RK1808_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 7), 680 681 RK1808_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 682 RK1808_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 683 }; 684 685 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 686 rk_clrsetreg(&grf->mac_con1, 687 RK1808_GMAC_PHY_INTF_SEL_MASK | 688 RK1808_RXCLK_DLY_ENA_GMAC_MASK | 689 RK1808_TXCLK_DLY_ENA_GMAC_MASK, 690 RK1808_GMAC_PHY_INTF_SEL_RGMII | 691 RK1808_RXCLK_DLY_ENA_GMAC_ENABLE | 692 RK1808_TXCLK_DLY_ENA_GMAC_ENABLE); 693 694 rk_clrsetreg(&grf->mac_con0, 695 RK1808_CLK_RX_DL_CFG_GMAC_MASK | 696 RK1808_CLK_TX_DL_CFG_GMAC_MASK, 697 pdata->rx_delay << RK1808_CLK_RX_DL_CFG_GMAC_SHIFT | 698 pdata->tx_delay << RK1808_CLK_TX_DL_CFG_GMAC_SHIFT); 699 } 700 701 static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 702 { 703 struct rk322x_grf *grf; 704 enum { 705 RK3228_RMII_MODE_SHIFT = 10, 706 RK3228_RMII_MODE_MASK = BIT(10), 707 708 RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4, 709 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 710 RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 711 712 RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 713 RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 714 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 715 716 RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 717 RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 718 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 719 }; 720 enum { 721 RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 722 RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 723 724 RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 725 RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 726 }; 727 728 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 729 rk_clrsetreg(&grf->mac_con[1], 730 RK3228_RMII_MODE_MASK | 731 RK3228_GMAC_PHY_INTF_SEL_MASK | 732 RK3228_RXCLK_DLY_ENA_GMAC_MASK | 733 RK3228_TXCLK_DLY_ENA_GMAC_MASK, 734 RK3228_GMAC_PHY_INTF_SEL_RGMII | 735 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE | 736 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE); 737 738 rk_clrsetreg(&grf->mac_con[0], 739 RK3228_CLK_RX_DL_CFG_GMAC_MASK | 740 RK3228_CLK_TX_DL_CFG_GMAC_MASK, 741 pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT | 742 pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT); 743 } 744 745 static void rk3228_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 746 { 747 struct rk322x_grf *grf; 748 enum { 749 RK3228_GRF_CON_RMII_MODE_MASK = BIT(11), 750 RK3228_GRF_CON_RMII_MODE_SEL = BIT(11), 751 RK3228_RMII_MODE_MASK = BIT(10), 752 RK3228_RMII_MODE_SEL = BIT(10), 753 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 754 RK3228_GMAC_PHY_INTF_SEL_RMII = BIT(6), 755 }; 756 757 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 758 rk_clrsetreg(&grf->mac_con[1], 759 RK3228_GRF_CON_RMII_MODE_MASK | 760 RK3228_RMII_MODE_MASK | 761 RK3228_GMAC_PHY_INTF_SEL_MASK, 762 RK3228_GRF_CON_RMII_MODE_SEL | 763 RK3228_RMII_MODE_SEL | 764 RK3228_GMAC_PHY_INTF_SEL_RMII); 765 } 766 767 static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 768 { 769 struct rk3288_grf *grf; 770 771 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 772 rk_clrsetreg(&grf->soc_con1, 773 RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK, 774 RK3288_GMAC_PHY_INTF_SEL_RGMII); 775 776 rk_clrsetreg(&grf->soc_con3, 777 RK3288_RXCLK_DLY_ENA_GMAC_MASK | 778 RK3288_TXCLK_DLY_ENA_GMAC_MASK | 779 RK3288_CLK_RX_DL_CFG_GMAC_MASK | 780 RK3288_CLK_TX_DL_CFG_GMAC_MASK, 781 RK3288_RXCLK_DLY_ENA_GMAC_ENABLE | 782 RK3288_TXCLK_DLY_ENA_GMAC_ENABLE | 783 pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT | 784 pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT); 785 } 786 787 static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 788 { 789 struct rk3308_grf *grf; 790 enum { 791 RK3308_GMAC_PHY_INTF_SEL_SHIFT = 2, 792 RK3308_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 2), 793 RK3308_GMAC_PHY_INTF_SEL_RMII = BIT(4), 794 }; 795 796 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 797 798 rk_clrsetreg(&grf->mac_con0, 799 RK3308_GMAC_PHY_INTF_SEL_MASK, 800 RK3308_GMAC_PHY_INTF_SEL_RMII); 801 } 802 803 static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 804 { 805 struct rk3328_grf_regs *grf; 806 enum { 807 RK3328_RMII_MODE_SHIFT = 9, 808 RK3328_RMII_MODE_MASK = BIT(9), 809 810 RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4, 811 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 812 RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 813 814 RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 815 RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 816 RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 817 818 RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 819 RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 820 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 821 }; 822 enum { 823 RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 824 RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 825 826 RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 827 RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 828 }; 829 830 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 831 rk_clrsetreg(&grf->mac_con[1], 832 RK3328_RMII_MODE_MASK | 833 RK3328_GMAC_PHY_INTF_SEL_MASK | 834 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 835 RK3328_TXCLK_DLY_ENA_GMAC_MASK, 836 RK3328_GMAC_PHY_INTF_SEL_RGMII | 837 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 838 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE); 839 840 rk_clrsetreg(&grf->mac_con[0], 841 RK3328_CLK_RX_DL_CFG_GMAC_MASK | 842 RK3328_CLK_TX_DL_CFG_GMAC_MASK, 843 pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT | 844 pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT); 845 } 846 847 static void rk3328_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 848 { 849 struct rk3328_grf_regs *grf; 850 enum { 851 RK3328_RMII_MODE_MASK = BIT(9), 852 RK3328_RMII_MODE = BIT(9), 853 854 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 855 RK3328_GMAC_PHY_INTF_SEL_RMII = BIT(6), 856 }; 857 858 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 859 rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1], 860 RK3328_RMII_MODE_MASK | 861 RK3328_GMAC_PHY_INTF_SEL_MASK, 862 RK3328_GMAC_PHY_INTF_SEL_RMII | 863 RK3328_RMII_MODE); 864 } 865 866 static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 867 { 868 struct rk3368_grf *grf; 869 enum { 870 RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9, 871 RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9), 872 RK3368_RMII_MODE_MASK = BIT(6), 873 RK3368_RMII_MODE = BIT(6), 874 }; 875 enum { 876 RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15), 877 RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 878 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15), 879 RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7), 880 RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 881 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7), 882 RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8, 883 RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 884 RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0, 885 RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 886 }; 887 888 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 889 rk_clrsetreg(&grf->soc_con15, 890 RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK, 891 RK3368_GMAC_PHY_INTF_SEL_RGMII); 892 893 rk_clrsetreg(&grf->soc_con16, 894 RK3368_RXCLK_DLY_ENA_GMAC_MASK | 895 RK3368_TXCLK_DLY_ENA_GMAC_MASK | 896 RK3368_CLK_RX_DL_CFG_GMAC_MASK | 897 RK3368_CLK_TX_DL_CFG_GMAC_MASK, 898 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE | 899 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE | 900 pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT | 901 pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT); 902 } 903 904 static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 905 { 906 struct rk3399_grf_regs *grf; 907 908 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 909 910 rk_clrsetreg(&grf->soc_con5, 911 RK3399_GMAC_PHY_INTF_SEL_MASK, 912 RK3399_GMAC_PHY_INTF_SEL_RGMII); 913 914 rk_clrsetreg(&grf->soc_con6, 915 RK3399_RXCLK_DLY_ENA_GMAC_MASK | 916 RK3399_TXCLK_DLY_ENA_GMAC_MASK | 917 RK3399_CLK_RX_DL_CFG_GMAC_MASK | 918 RK3399_CLK_TX_DL_CFG_GMAC_MASK, 919 RK3399_RXCLK_DLY_ENA_GMAC_ENABLE | 920 RK3399_TXCLK_DLY_ENA_GMAC_ENABLE | 921 pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT | 922 pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT); 923 } 924 925 static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 926 { 927 struct rv1108_grf *grf; 928 929 enum { 930 RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 931 RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4, 932 }; 933 934 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 935 rk_clrsetreg(&grf->gmac_con0, 936 RV1108_GMAC_PHY_INTF_SEL_MASK, 937 RV1108_GMAC_PHY_INTF_SEL_RMII); 938 } 939 940 static void rk3228_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 941 { 942 struct rk322x_grf *grf; 943 enum { 944 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK = BIT(15), 945 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY = BIT(15), 946 }; 947 enum { 948 RK3228_MACPHY_CFG_CLK_50M_MASK = BIT(14), 949 RK3228_MACPHY_CFG_CLK_50M = BIT(14), 950 951 RK3228_MACPHY_RMII_MODE_MASK = GENMASK(7, 6), 952 RK3228_MACPHY_RMII_MODE = BIT(6), 953 954 RK3228_MACPHY_ENABLE_MASK = BIT(0), 955 RK3228_MACPHY_DISENABLE = 0, 956 RK3228_MACPHY_ENABLE = BIT(0), 957 }; 958 enum { 959 RK3228_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0), 960 RK3228_RK_GRF_CON2_MACPHY_ID = 0x1234, 961 }; 962 enum { 963 RK3228_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0), 964 RK3228_RK_GRF_CON3_MACPHY_ID = 0x35, 965 }; 966 967 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 968 rk_clrsetreg(&grf->con_iomux, 969 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK, 970 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY); 971 972 rk_clrsetreg(&grf->macphy_con[2], 973 RK3228_RK_GRF_CON2_MACPHY_ID_MASK, 974 RK3228_RK_GRF_CON2_MACPHY_ID); 975 976 rk_clrsetreg(&grf->macphy_con[3], 977 RK3228_RK_GRF_CON3_MACPHY_ID_MASK, 978 RK3228_RK_GRF_CON3_MACPHY_ID); 979 980 /* disabled before trying to reset it &*/ 981 rk_clrsetreg(&grf->macphy_con[0], 982 RK3228_MACPHY_CFG_CLK_50M_MASK | 983 RK3228_MACPHY_RMII_MODE_MASK | 984 RK3228_MACPHY_ENABLE_MASK, 985 RK3228_MACPHY_CFG_CLK_50M | 986 RK3228_MACPHY_RMII_MODE | 987 RK3228_MACPHY_DISENABLE); 988 989 reset_assert(&pdata->phy_reset); 990 udelay(10); 991 reset_deassert(&pdata->phy_reset); 992 udelay(10); 993 994 rk_clrsetreg(&grf->macphy_con[0], 995 RK3228_MACPHY_ENABLE_MASK, 996 RK3228_MACPHY_ENABLE); 997 udelay(30 * 1000); 998 } 999 1000 static void rk3328_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 1001 { 1002 struct rk3328_grf_regs *grf; 1003 enum { 1004 RK3328_GRF_CON_RMII_MODE_MASK = BIT(9), 1005 RK3328_GRF_CON_RMII_MODE = BIT(9), 1006 }; 1007 enum { 1008 RK3328_MACPHY_CFG_CLK_50M_MASK = BIT(14), 1009 RK3328_MACPHY_CFG_CLK_50M = BIT(14), 1010 1011 RK3328_MACPHY_RMII_MODE_MASK = GENMASK(7, 6), 1012 RK3328_MACPHY_RMII_MODE = BIT(6), 1013 1014 RK3328_MACPHY_ENABLE_MASK = BIT(0), 1015 RK3328_MACPHY_DISENABLE = 0, 1016 RK3328_MACPHY_ENABLE = BIT(0), 1017 }; 1018 enum { 1019 RK3328_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0), 1020 RK3328_RK_GRF_CON2_MACPHY_ID = 0x1234, 1021 }; 1022 enum { 1023 RK3328_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0), 1024 RK3328_RK_GRF_CON3_MACPHY_ID = 0x35, 1025 }; 1026 1027 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1028 rk_clrsetreg(&grf->macphy_con[1], 1029 RK3328_GRF_CON_RMII_MODE_MASK, 1030 RK3328_GRF_CON_RMII_MODE); 1031 1032 rk_clrsetreg(&grf->macphy_con[2], 1033 RK3328_RK_GRF_CON2_MACPHY_ID_MASK, 1034 RK3328_RK_GRF_CON2_MACPHY_ID); 1035 1036 rk_clrsetreg(&grf->macphy_con[3], 1037 RK3328_RK_GRF_CON3_MACPHY_ID_MASK, 1038 RK3328_RK_GRF_CON3_MACPHY_ID); 1039 1040 /* disabled before trying to reset it &*/ 1041 rk_clrsetreg(&grf->macphy_con[0], 1042 RK3328_MACPHY_CFG_CLK_50M_MASK | 1043 RK3328_MACPHY_RMII_MODE_MASK | 1044 RK3328_MACPHY_ENABLE_MASK, 1045 RK3328_MACPHY_CFG_CLK_50M | 1046 RK3328_MACPHY_RMII_MODE | 1047 RK3328_MACPHY_DISENABLE); 1048 1049 reset_assert(&pdata->phy_reset); 1050 udelay(10); 1051 reset_deassert(&pdata->phy_reset); 1052 udelay(10); 1053 1054 rk_clrsetreg(&grf->macphy_con[0], 1055 RK3328_MACPHY_ENABLE_MASK, 1056 RK3328_MACPHY_ENABLE); 1057 udelay(30 * 1000); 1058 } 1059 1060 #else 1061 static void rk3568_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1062 { 1063 struct rk3568_grf *grf; 1064 void *con1; 1065 1066 enum { 1067 RK3568_GMAC_PHY_INTF_SEL_SHIFT = 4, 1068 RK3568_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1069 RK3568_GMAC_PHY_INTF_SEL_RMII = BIT(6), 1070 }; 1071 1072 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1073 1074 if (pdata->bus_id == 1) 1075 con1 = &grf->mac1_con1; 1076 else 1077 con1 = &grf->mac0_con1; 1078 1079 rk_clrsetreg(con1, 1080 RK3568_GMAC_PHY_INTF_SEL_MASK, 1081 RK3568_GMAC_PHY_INTF_SEL_RMII); 1082 } 1083 1084 static void rk3568_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1085 { 1086 struct rk3568_grf *grf; 1087 void *con0, *con1; 1088 1089 enum { 1090 RK3568_GMAC_PHY_INTF_SEL_SHIFT = 4, 1091 RK3568_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1092 RK3568_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 1093 1094 RK3568_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 1095 RK3568_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 1096 RK3568_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 1097 1098 RK3568_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 1099 RK3568_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 1100 RK3568_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 1101 }; 1102 1103 enum { 1104 RK3568_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1105 RK3568_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 8), 1106 1107 RK3568_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1108 RK3568_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 1109 }; 1110 1111 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1112 1113 if (pdata->bus_id == 1) { 1114 con0 = &grf->mac1_con0; 1115 con1 = &grf->mac1_con1; 1116 } else { 1117 con0 = &grf->mac0_con0; 1118 con1 = &grf->mac0_con1; 1119 } 1120 1121 rk_clrsetreg(con0, 1122 RK3568_CLK_RX_DL_CFG_GMAC_MASK | 1123 RK3568_CLK_TX_DL_CFG_GMAC_MASK, 1124 pdata->rx_delay << RK3568_CLK_RX_DL_CFG_GMAC_SHIFT | 1125 pdata->tx_delay << RK3568_CLK_TX_DL_CFG_GMAC_SHIFT); 1126 1127 rk_clrsetreg(con1, 1128 RK3568_TXCLK_DLY_ENA_GMAC_MASK | 1129 RK3568_RXCLK_DLY_ENA_GMAC_MASK | 1130 RK3568_GMAC_PHY_INTF_SEL_MASK, 1131 RK3568_TXCLK_DLY_ENA_GMAC_ENABLE | 1132 RK3568_RXCLK_DLY_ENA_GMAC_ENABLE | 1133 RK3568_GMAC_PHY_INTF_SEL_RGMII); 1134 } 1135 1136 static void rk3588_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1137 { 1138 unsigned int intf_sel, intf_sel_mask; 1139 unsigned int clk_mode, clk_mode_mask; 1140 struct rk3588_php_grf *php_grf; 1141 1142 enum { 1143 RK3588_GMAC_PHY_INTF_SEL_SHIFT = 3, 1144 RK3588_GMAC_PHY_INTF_SEL_MASK = GENMASK(5, 3), 1145 RK3588_GMAC_PHY_INTF_SEL_RMII = BIT(5), 1146 }; 1147 1148 enum { 1149 RK3588_GMAC_CLK_RMII_MODE_SHIFT = 0x0, 1150 RK3588_GMAC_CLK_RMII_MODE_MASK = BIT(0), 1151 RK3588_GMAC_CLK_RMII_MODE = 0x1, 1152 }; 1153 1154 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 1155 1156 if (pdata->bus_id == 1) { 1157 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RMII << 6; 1158 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK << 6; 1159 clk_mode = RK3588_GMAC_CLK_RMII_MODE << 5; 1160 clk_mode_mask = RK3588_GMAC_CLK_RMII_MODE_MASK << 5; 1161 } else { 1162 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RMII; 1163 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK; 1164 clk_mode = RK3588_GMAC_CLK_RMII_MODE; 1165 clk_mode_mask = RK3588_GMAC_CLK_RMII_MODE_MASK; 1166 } 1167 1168 rk_clrsetreg(&php_grf->gmac_con0, intf_sel_mask, intf_sel); 1169 rk_clrsetreg(&php_grf->clk_con1, clk_mode_mask, clk_mode); 1170 } 1171 1172 static void rk3588_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1173 { 1174 unsigned int rx_enable, rx_enable_mask, tx_enable, tx_enable_mask; 1175 unsigned int intf_sel, intf_sel_mask; 1176 unsigned int clk_mode, clk_mode_mask; 1177 unsigned int rx_delay; 1178 struct rk3588_php_grf *php_grf; 1179 struct rk3588_sys_grf *grf; 1180 void *offset_con; 1181 1182 enum { 1183 RK3588_GMAC_PHY_INTF_SEL_SHIFT = 3, 1184 RK3588_GMAC_PHY_INTF_SEL_MASK = GENMASK(5, 3), 1185 RK3588_GMAC_PHY_INTF_SEL_RGMII = BIT(3), 1186 1187 RK3588_RXCLK_DLY_ENA_GMAC_MASK = BIT(3), 1188 RK3588_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 1189 RK3588_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(3), 1190 1191 RK3588_TXCLK_DLY_ENA_GMAC_MASK = BIT(2), 1192 RK3588_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 1193 RK3588_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(2), 1194 }; 1195 1196 enum { 1197 RK3588_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1198 RK3588_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 8), 1199 1200 RK3588_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1201 RK3588_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 1202 }; 1203 1204 enum { 1205 RK3588_GMAC_CLK_RGMII_MODE_SHIFT = 0x0, 1206 RK3588_GMAC_CLK_RGMII_MODE_MASK = BIT(0), 1207 RK3588_GMAC_CLK_RGMII_MODE = 0x0, 1208 }; 1209 1210 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1211 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 1212 1213 if (pdata->rx_delay < 0) { 1214 rx_enable = RK3588_RXCLK_DLY_ENA_GMAC_DISABLE; 1215 rx_delay = 0; 1216 } else { 1217 rx_enable = RK3588_RXCLK_DLY_ENA_GMAC_ENABLE; 1218 rx_delay = pdata->rx_delay << RK3588_CLK_RX_DL_CFG_GMAC_SHIFT; 1219 } 1220 1221 if (pdata->bus_id == 1) { 1222 offset_con = &grf->soc_con9; 1223 rx_enable = rx_delay << 2; 1224 rx_enable_mask = RK3588_RXCLK_DLY_ENA_GMAC_MASK << 2; 1225 tx_enable = RK3588_TXCLK_DLY_ENA_GMAC_ENABLE << 2; 1226 tx_enable_mask = RK3588_TXCLK_DLY_ENA_GMAC_MASK << 2; 1227 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RGMII << 6; 1228 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK << 6; 1229 clk_mode = RK3588_GMAC_CLK_RGMII_MODE << 5; 1230 clk_mode_mask = RK3588_GMAC_CLK_RGMII_MODE_MASK << 5; 1231 } else { 1232 offset_con = &grf->soc_con8; 1233 rx_enable_mask = RK3588_RXCLK_DLY_ENA_GMAC_MASK; 1234 tx_enable = RK3588_TXCLK_DLY_ENA_GMAC_ENABLE; 1235 tx_enable_mask = RK3588_TXCLK_DLY_ENA_GMAC_MASK; 1236 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RGMII; 1237 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK; 1238 clk_mode = RK3588_GMAC_CLK_RGMII_MODE; 1239 clk_mode_mask = RK3588_GMAC_CLK_RGMII_MODE_MASK; 1240 } 1241 1242 rk_clrsetreg(offset_con, 1243 RK3588_CLK_TX_DL_CFG_GMAC_MASK | 1244 RK3588_CLK_RX_DL_CFG_GMAC_MASK, 1245 pdata->tx_delay << RK3588_CLK_TX_DL_CFG_GMAC_SHIFT | 1246 rx_delay); 1247 1248 rk_clrsetreg(&grf->soc_con7, tx_enable_mask | rx_enable_mask, 1249 tx_enable | rx_enable); 1250 1251 rk_clrsetreg(&php_grf->gmac_con0, intf_sel_mask, intf_sel); 1252 rk_clrsetreg(&php_grf->clk_con1, clk_mode_mask, clk_mode); 1253 } 1254 1255 static void rv1106_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 1256 { 1257 struct rv1106_grf *grf; 1258 enum { 1259 RV1106_VOGRF_GMAC_CLK_RMII_MODE_MASK = BIT(0), 1260 RV1106_VOGRF_GMAC_CLK_RMII_MODE = BIT(0), 1261 }; 1262 1263 enum { 1264 RV1106_MACPHY_ENABLE_MASK = BIT(1), 1265 RV1106_MACPHY_DISENABLE = BIT(1), 1266 RV1106_MACPHY_ENABLE = 0, 1267 RV1106_MACPHY_XMII_SEL_MASK = GENMASK(6, 5), 1268 RV1106_MACPHY_XMII_SEL = BIT(6), 1269 RV1106_MACPHY_24M_CLK_SEL_MASK = GENMASK(9, 7), 1270 RV1106_MACPHY_24M_CLK_SEL_24M = (BIT(8) | BIT(9)), 1271 RV1106_MACPHY_PHY_ID_MASK = GENMASK(14, 10), 1272 RV1106_MACPHY_PHY_ID = BIT(11), 1273 }; 1274 1275 enum { 1276 RV1106_MACPHY_BGS_MASK = GENMASK(3, 0), 1277 RV1106_MACPHY_BGS = BIT(2), 1278 }; 1279 1280 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1281 1282 reset_assert(&pdata->phy_reset); 1283 udelay(20); 1284 1285 rk_clrsetreg(&grf->gmac_clk_con, 1286 RV1106_VOGRF_GMAC_CLK_RMII_MODE_MASK, 1287 RV1106_VOGRF_GMAC_CLK_RMII_MODE); 1288 1289 rk_clrsetreg(&grf->macphy_con0, 1290 RV1106_MACPHY_ENABLE_MASK | 1291 RV1106_MACPHY_XMII_SEL_MASK | 1292 RV1106_MACPHY_24M_CLK_SEL_MASK | 1293 RV1106_MACPHY_PHY_ID_MASK, 1294 RV1106_MACPHY_ENABLE | 1295 RV1106_MACPHY_XMII_SEL | 1296 RV1106_MACPHY_24M_CLK_SEL_24M | 1297 RV1106_MACPHY_PHY_ID); 1298 1299 rk_clrsetreg(&grf->macphy_con1, 1300 RV1106_MACPHY_BGS_MASK, 1301 RV1106_MACPHY_BGS); 1302 1303 reset_deassert(&pdata->phy_reset); 1304 1305 udelay(30 * 1000); 1306 } 1307 1308 static void rv1126_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1309 { 1310 struct rv1126_grf *grf; 1311 1312 enum { 1313 RV1126_GMAC_PHY_INTF_SEL_SHIFT = 4, 1314 RV1126_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1315 RV1126_GMAC_PHY_INTF_SEL_RMII = BIT(6), 1316 }; 1317 1318 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1319 1320 rk_clrsetreg(&grf->mac_con0, 1321 RV1126_GMAC_PHY_INTF_SEL_MASK, 1322 RV1126_GMAC_PHY_INTF_SEL_RMII); 1323 } 1324 1325 static void rv1126_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1326 { 1327 struct rv1126_grf *grf; 1328 1329 enum { 1330 RV1126_GMAC_PHY_INTF_SEL_SHIFT = 4, 1331 RV1126_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1332 RV1126_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 1333 1334 RV1126_RXCLK_M1_DLY_ENA_GMAC_MASK = BIT(3), 1335 RV1126_RXCLK_M1_DLY_ENA_GMAC_DISABLE = 0, 1336 RV1126_RXCLK_M1_DLY_ENA_GMAC_ENABLE = BIT(3), 1337 1338 RV1126_TXCLK_M1_DLY_ENA_GMAC_MASK = BIT(2), 1339 RV1126_TXCLK_M1_DLY_ENA_GMAC_DISABLE = 0, 1340 RV1126_TXCLK_M1_DLY_ENA_GMAC_ENABLE = BIT(2), 1341 1342 RV1126_RXCLK_M0_DLY_ENA_GMAC_MASK = BIT(1), 1343 RV1126_RXCLK_M0_DLY_ENA_GMAC_DISABLE = 0, 1344 RV1126_RXCLK_M0_DLY_ENA_GMAC_ENABLE = BIT(1), 1345 1346 RV1126_TXCLK_M0_DLY_ENA_GMAC_MASK = BIT(0), 1347 RV1126_TXCLK_M0_DLY_ENA_GMAC_DISABLE = 0, 1348 RV1126_TXCLK_M0_DLY_ENA_GMAC_ENABLE = BIT(0), 1349 }; 1350 enum { 1351 RV1126_M0_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1352 RV1126_M0_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 1353 1354 RV1126_M0_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1355 RV1126_M0_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 1356 }; 1357 enum { 1358 RV1126_M1_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1359 RV1126_M1_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 1360 1361 RV1126_M1_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1362 RV1126_M1_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 1363 }; 1364 1365 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1366 1367 rk_clrsetreg(&grf->mac_con0, 1368 RV1126_TXCLK_M0_DLY_ENA_GMAC_MASK | 1369 RV1126_RXCLK_M0_DLY_ENA_GMAC_MASK | 1370 RV1126_TXCLK_M1_DLY_ENA_GMAC_MASK | 1371 RV1126_RXCLK_M1_DLY_ENA_GMAC_MASK | 1372 RV1126_GMAC_PHY_INTF_SEL_MASK, 1373 RV1126_TXCLK_M0_DLY_ENA_GMAC_ENABLE | 1374 RV1126_RXCLK_M0_DLY_ENA_GMAC_ENABLE | 1375 RV1126_TXCLK_M1_DLY_ENA_GMAC_ENABLE | 1376 RV1126_RXCLK_M1_DLY_ENA_GMAC_ENABLE | 1377 RV1126_GMAC_PHY_INTF_SEL_RGMII); 1378 1379 rk_clrsetreg(&grf->mac_con1, 1380 RV1126_M0_CLK_RX_DL_CFG_GMAC_MASK | 1381 RV1126_M0_CLK_TX_DL_CFG_GMAC_MASK, 1382 pdata->rx_delay << RV1126_M0_CLK_RX_DL_CFG_GMAC_SHIFT | 1383 pdata->tx_delay << RV1126_M0_CLK_TX_DL_CFG_GMAC_SHIFT); 1384 1385 rk_clrsetreg(&grf->mac_con2, 1386 RV1126_M1_CLK_RX_DL_CFG_GMAC_MASK | 1387 RV1126_M1_CLK_TX_DL_CFG_GMAC_MASK, 1388 pdata->rx_delay << RV1126_M1_CLK_RX_DL_CFG_GMAC_SHIFT | 1389 pdata->tx_delay << RV1126_M1_CLK_TX_DL_CFG_GMAC_SHIFT); 1390 } 1391 #endif 1392 1393 #ifdef CONFIG_DWC_ETH_QOS 1394 static void rk3588_set_clock_selection(struct gmac_rockchip_platdata *pdata) 1395 { 1396 struct rk3588_php_grf *php_grf; 1397 unsigned int val, mask; 1398 1399 enum { 1400 RK3588_GMAC_CLK_SELET_SHIFT = 0x4, 1401 RK3588_GMAC_CLK_SELET_MASK = BIT(4), 1402 RK3588_GMAC_CLK_SELET_CRU = BIT(4), 1403 RK3588_GMAC_CLK_SELET_IO = 0, 1404 }; 1405 1406 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 1407 val = pdata->clock_input ? RK3588_GMAC_CLK_SELET_IO : 1408 RK3588_GMAC_CLK_SELET_CRU; 1409 mask = RK3588_GMAC_CLK_SELET_MASK; 1410 1411 if (pdata->bus_id == 1) { 1412 val <<= 5; 1413 mask <<= 5; 1414 } 1415 1416 rk_clrsetreg(&php_grf->clk_con1, mask, val); 1417 } 1418 #endif 1419 1420 static int gmac_rockchip_probe(struct udevice *dev) 1421 { 1422 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 1423 struct rk_gmac_ops *ops = 1424 (struct rk_gmac_ops *)dev_get_driver_data(dev); 1425 #ifdef CONFIG_DWC_ETH_QOS 1426 struct eqos_config *config; 1427 #else 1428 struct dw_eth_pdata *dw_pdata; 1429 #endif 1430 struct eth_pdata *eth_pdata; 1431 struct clk clk; 1432 ulong rate; 1433 int ret; 1434 1435 #ifdef CONFIG_DWC_ETH_QOS 1436 eth_pdata = &pdata->eth_pdata; 1437 config = (struct eqos_config *)&ops->config; 1438 memcpy(config, &eqos_rockchip_config, sizeof(struct eqos_config)); 1439 eth_pdata->phy_interface = config->ops->eqos_get_interface(dev); 1440 #else 1441 dw_pdata = &pdata->dw_eth_pdata; 1442 eth_pdata = &dw_pdata->eth_pdata; 1443 #endif 1444 pdata->bus_id = dev->seq; 1445 1446 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 1447 ret = clk_set_defaults(dev); 1448 if (ret) 1449 debug("%s clk_set_defaults failed %d\n", __func__, ret); 1450 1451 ret = clk_get_by_index(dev, 0, &clk); 1452 if (ret) 1453 return ret; 1454 1455 pdata->phy_interface = eth_pdata->phy_interface; 1456 1457 if (ops->set_clock_selection) 1458 ops->set_clock_selection(pdata); 1459 1460 if (pdata->integrated_phy && ops->integrated_phy_powerup) 1461 ops->integrated_phy_powerup(pdata); 1462 1463 switch (eth_pdata->phy_interface) { 1464 case PHY_INTERFACE_MODE_RGMII: 1465 case PHY_INTERFACE_MODE_RGMII_RXID: 1466 /* 1467 * If the gmac clock is from internal pll, need to set and 1468 * check the return value for gmac clock at RGMII mode. If 1469 * the gmac clock is from external source, the clock rate 1470 * is not set, because of it is bypassed. 1471 */ 1472 if (!pdata->clock_input) { 1473 rate = clk_set_rate(&clk, 125000000); 1474 if (rate != 125000000) 1475 return -EINVAL; 1476 } 1477 1478 if (eth_pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) 1479 pdata->rx_delay = -1; 1480 1481 /* Set to RGMII mode */ 1482 if (ops->set_to_rgmii) 1483 ops->set_to_rgmii(pdata); 1484 else 1485 return -EPERM; 1486 1487 break; 1488 case PHY_INTERFACE_MODE_RMII: 1489 /* The commet is the same as RGMII mode */ 1490 if (!pdata->clock_input) { 1491 rate = clk_set_rate(&clk, 50000000); 1492 if (rate != 50000000) 1493 return -EINVAL; 1494 } 1495 1496 /* Set to RMII mode */ 1497 if (ops->set_to_rmii) 1498 ops->set_to_rmii(pdata); 1499 1500 break; 1501 default: 1502 debug("NO interface defined!\n"); 1503 return -ENXIO; 1504 } 1505 1506 #ifdef CONFIG_DWC_ETH_QOS 1507 return eqos_probe(dev); 1508 #else 1509 return designware_eth_probe(dev); 1510 #endif 1511 } 1512 1513 static int gmac_rockchip_eth_write_hwaddr(struct udevice *dev) 1514 { 1515 #if defined(CONFIG_DWC_ETH_QOS) 1516 return eqos_write_hwaddr(dev); 1517 #else 1518 return designware_eth_write_hwaddr(dev); 1519 #endif 1520 } 1521 1522 static int gmac_rockchip_eth_free_pkt(struct udevice *dev, uchar *packet, 1523 int length) 1524 { 1525 #ifdef CONFIG_DWC_ETH_QOS 1526 return eqos_free_pkt(dev, packet, length); 1527 #else 1528 return designware_eth_free_pkt(dev, packet, length); 1529 #endif 1530 } 1531 1532 static int gmac_rockchip_eth_send(struct udevice *dev, void *packet, 1533 int length) 1534 { 1535 #ifdef CONFIG_DWC_ETH_QOS 1536 return eqos_send(dev, packet, length); 1537 #else 1538 return designware_eth_send(dev, packet, length); 1539 #endif 1540 } 1541 1542 static int gmac_rockchip_eth_recv(struct udevice *dev, int flags, 1543 uchar **packetp) 1544 { 1545 #ifdef CONFIG_DWC_ETH_QOS 1546 return eqos_recv(dev, flags, packetp); 1547 #else 1548 return designware_eth_recv(dev, flags, packetp); 1549 #endif 1550 } 1551 1552 static int gmac_rockchip_eth_start(struct udevice *dev) 1553 { 1554 struct rockchip_eth_dev *priv = dev_get_priv(dev); 1555 struct rk_gmac_ops *ops = 1556 (struct rk_gmac_ops *)dev_get_driver_data(dev); 1557 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 1558 #ifndef CONFIG_DWC_ETH_QOS 1559 struct dw_eth_pdata *dw_pdata; 1560 struct eth_pdata *eth_pdata; 1561 #endif 1562 int ret; 1563 1564 #ifdef CONFIG_DWC_ETH_QOS 1565 ret = eqos_init(dev); 1566 #else 1567 dw_pdata = &pdata->dw_eth_pdata; 1568 eth_pdata = &dw_pdata->eth_pdata; 1569 ret = designware_eth_init((struct dw_eth_dev *)priv, 1570 eth_pdata->enetaddr); 1571 #endif 1572 if (ret) 1573 return ret; 1574 ret = ops->fix_mac_speed(pdata, priv); 1575 if (ret) 1576 return ret; 1577 1578 #ifdef CONFIG_DWC_ETH_QOS 1579 eqos_enable(dev); 1580 #else 1581 ret = designware_eth_enable((struct dw_eth_dev *)priv); 1582 if (ret) 1583 return ret; 1584 #endif 1585 1586 return 0; 1587 } 1588 1589 static void gmac_rockchip_eth_stop(struct udevice *dev) 1590 { 1591 #ifdef CONFIG_DWC_ETH_QOS 1592 eqos_stop(dev); 1593 #else 1594 designware_eth_stop(dev); 1595 #endif 1596 } 1597 1598 const struct eth_ops gmac_rockchip_eth_ops = { 1599 .start = gmac_rockchip_eth_start, 1600 .send = gmac_rockchip_eth_send, 1601 .recv = gmac_rockchip_eth_recv, 1602 .free_pkt = gmac_rockchip_eth_free_pkt, 1603 .stop = gmac_rockchip_eth_stop, 1604 .write_hwaddr = gmac_rockchip_eth_write_hwaddr, 1605 }; 1606 1607 #ifndef CONFIG_DWC_ETH_QOS 1608 const struct rk_gmac_ops px30_gmac_ops = { 1609 .fix_mac_speed = px30_gmac_fix_mac_speed, 1610 .set_to_rmii = px30_gmac_set_to_rmii, 1611 }; 1612 1613 const struct rk_gmac_ops rk1808_gmac_ops = { 1614 .fix_mac_speed = rk1808_gmac_fix_mac_speed, 1615 .set_to_rgmii = rk1808_gmac_set_to_rgmii, 1616 }; 1617 1618 const struct rk_gmac_ops rk3228_gmac_ops = { 1619 .fix_mac_speed = rk3228_gmac_fix_mac_speed, 1620 .set_to_rmii = rk3228_gmac_set_to_rmii, 1621 .set_to_rgmii = rk3228_gmac_set_to_rgmii, 1622 .integrated_phy_powerup = rk3228_gmac_integrated_phy_powerup, 1623 }; 1624 1625 const struct rk_gmac_ops rk3288_gmac_ops = { 1626 .fix_mac_speed = rk3288_gmac_fix_mac_speed, 1627 .set_to_rgmii = rk3288_gmac_set_to_rgmii, 1628 }; 1629 1630 const struct rk_gmac_ops rk3308_gmac_ops = { 1631 .fix_mac_speed = rk3308_gmac_fix_mac_speed, 1632 .set_to_rmii = rk3308_gmac_set_to_rmii, 1633 }; 1634 1635 const struct rk_gmac_ops rk3328_gmac_ops = { 1636 .fix_mac_speed = rk3328_gmac_fix_mac_speed, 1637 .set_to_rmii = rk3328_gmac_set_to_rmii, 1638 .set_to_rgmii = rk3328_gmac_set_to_rgmii, 1639 .integrated_phy_powerup = rk3328_gmac_integrated_phy_powerup, 1640 }; 1641 1642 const struct rk_gmac_ops rk3368_gmac_ops = { 1643 .fix_mac_speed = rk3368_gmac_fix_mac_speed, 1644 .set_to_rgmii = rk3368_gmac_set_to_rgmii, 1645 }; 1646 1647 const struct rk_gmac_ops rk3399_gmac_ops = { 1648 .fix_mac_speed = rk3399_gmac_fix_mac_speed, 1649 .set_to_rgmii = rk3399_gmac_set_to_rgmii, 1650 }; 1651 1652 const struct rk_gmac_ops rv1108_gmac_ops = { 1653 .fix_mac_speed = rv1108_set_rmii_speed, 1654 .set_to_rmii = rv1108_gmac_set_to_rmii, 1655 }; 1656 #else 1657 const struct rk_gmac_ops rk3568_gmac_ops = { 1658 .fix_mac_speed = rv1126_set_rgmii_speed, 1659 .set_to_rgmii = rk3568_set_to_rgmii, 1660 .set_to_rmii = rk3568_set_to_rmii, 1661 }; 1662 1663 const struct rk_gmac_ops rk3588_gmac_ops = { 1664 .fix_mac_speed = rk3588_set_rgmii_speed, 1665 .set_to_rgmii = rk3588_set_to_rgmii, 1666 .set_to_rmii = rk3588_set_to_rmii, 1667 .set_clock_selection = rk3588_set_clock_selection, 1668 }; 1669 1670 const struct rk_gmac_ops rv1106_gmac_ops = { 1671 .fix_mac_speed = rv1106_set_rmii_speed, 1672 .integrated_phy_powerup = rv1106_gmac_integrated_phy_powerup, 1673 }; 1674 1675 const struct rk_gmac_ops rv1126_gmac_ops = { 1676 .fix_mac_speed = rv1126_set_rgmii_speed, 1677 .set_to_rgmii = rv1126_set_to_rgmii, 1678 .set_to_rmii = rv1126_set_to_rmii, 1679 }; 1680 #endif 1681 1682 static const struct udevice_id rockchip_gmac_ids[] = { 1683 #ifndef CONFIG_DWC_ETH_QOS 1684 #ifdef CONFIG_ROCKCHIP_PX30 1685 { .compatible = "rockchip,px30-gmac", 1686 .data = (ulong)&px30_gmac_ops }, 1687 #endif 1688 1689 #ifdef CONFIG_ROCKCHIP_RK1808 1690 { .compatible = "rockchip,rk1808-gmac", 1691 .data = (ulong)&rk1808_gmac_ops }, 1692 #endif 1693 1694 #ifdef CONFIG_ROCKCHIP_RK3228 1695 { .compatible = "rockchip,rk3228-gmac", 1696 .data = (ulong)&rk3228_gmac_ops }, 1697 #endif 1698 1699 #ifdef CONFIG_ROCKCHIP_RK3288 1700 { .compatible = "rockchip,rk3288-gmac", 1701 .data = (ulong)&rk3288_gmac_ops }, 1702 #endif 1703 1704 #ifdef CONFIG_ROCKCHIP_RK3308 1705 { .compatible = "rockchip,rk3308-mac", 1706 .data = (ulong)&rk3308_gmac_ops }, 1707 #endif 1708 1709 #ifdef CONFIG_ROCKCHIP_RK3328 1710 { .compatible = "rockchip,rk3328-gmac", 1711 .data = (ulong)&rk3328_gmac_ops }, 1712 #endif 1713 1714 #ifdef CONFIG_ROCKCHIP_RK3368 1715 { .compatible = "rockchip,rk3368-gmac", 1716 .data = (ulong)&rk3368_gmac_ops }, 1717 #endif 1718 1719 #ifdef CONFIG_ROCKCHIP_RK3399 1720 { .compatible = "rockchip,rk3399-gmac", 1721 .data = (ulong)&rk3399_gmac_ops }, 1722 #endif 1723 1724 #ifdef CONFIG_ROCKCHIP_RV1108 1725 { .compatible = "rockchip,rv1108-gmac", 1726 .data = (ulong)&rv1108_gmac_ops }, 1727 #endif 1728 #else 1729 #ifdef CONFIG_ROCKCHIP_RK3568 1730 { .compatible = "rockchip,rk3568-gmac", 1731 .data = (ulong)&rk3568_gmac_ops }, 1732 #endif 1733 1734 #ifdef CONFIG_ROCKCHIP_RK3588 1735 { .compatible = "rockchip,rk3588-gmac", 1736 .data = (ulong)&rk3588_gmac_ops }, 1737 #endif 1738 1739 #ifdef CONFIG_ROCKCHIP_RV1106 1740 { .compatible = "rockchip,rv1106-gmac", 1741 .data = (ulong)&rv1106_gmac_ops }, 1742 #endif 1743 1744 #ifdef CONFIG_ROCKCHIP_RV1126 1745 { .compatible = "rockchip,rv1126-gmac", 1746 .data = (ulong)&rv1126_gmac_ops }, 1747 #endif 1748 #endif 1749 { } 1750 }; 1751 1752 U_BOOT_DRIVER(eth_gmac_rockchip) = { 1753 .name = "gmac_rockchip", 1754 .id = UCLASS_ETH, 1755 .of_match = rockchip_gmac_ids, 1756 .ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata, 1757 .probe = gmac_rockchip_probe, 1758 .ops = &gmac_rockchip_eth_ops, 1759 .priv_auto_alloc_size = sizeof(struct rockchip_eth_dev), 1760 .platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata), 1761 .flags = DM_FLAG_ALLOC_PRIV_DMA, 1762 }; 1763