1 /* 2 * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Rockchip GMAC ethernet IP driver for U-Boot 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <clk.h> 12 #include <phy.h> 13 #include <syscon.h> 14 #include <asm/io.h> 15 #include <asm/arch/periph.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/hardware.h> 18 #ifdef CONFIG_DWC_ETH_QOS 19 #include <asm/arch/grf_rv1126.h> 20 #include "dwc_eth_qos.h" 21 #else 22 #include <asm/arch/grf_px30.h> 23 #include <asm/arch/grf_rk1808.h> 24 #include <asm/arch/grf_rk322x.h> 25 #include <asm/arch/grf_rk3288.h> 26 #include <asm/arch/grf_rk3308.h> 27 #include <asm/arch/grf_rk3328.h> 28 #include <asm/arch/grf_rk3368.h> 29 #include <asm/arch/grf_rk3399.h> 30 #include <asm/arch/grf_rv1108.h> 31 #include "designware.h" 32 #include <dt-bindings/clock/rk3288-cru.h> 33 #endif 34 #include <dm/pinctrl.h> 35 36 DECLARE_GLOBAL_DATA_PTR; 37 38 struct rockchip_eth_dev { 39 #ifdef CONFIG_DWC_ETH_QOS 40 struct eqos_priv eqos; 41 #else 42 struct dw_eth_dev dw; 43 #endif 44 }; 45 46 /* 47 * Platform data for the gmac 48 * 49 * dw_eth_pdata: Required platform data for designware driver (must be first) 50 */ 51 struct gmac_rockchip_platdata { 52 #ifndef CONFIG_DWC_ETH_QOS 53 struct dw_eth_pdata dw_eth_pdata; 54 #else 55 struct eth_pdata eth_pdata; 56 #endif 57 bool clock_input; 58 int tx_delay; 59 int rx_delay; 60 }; 61 62 struct rk_gmac_ops { 63 #ifdef CONFIG_DWC_ETH_QOS 64 const struct eqos_config config; 65 #endif 66 int (*fix_mac_speed)(struct rockchip_eth_dev *dev); 67 void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata); 68 void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata); 69 }; 70 71 #ifdef CONFIG_DWC_ETH_QOS 72 static const struct eqos_config eqos_rockchip_config = { 73 .reg_access_always_ok = false, 74 .mdio_wait = 10000, 75 .swr_wait = 200, 76 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED, 77 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_100_150, 78 .ops = &eqos_rockchip_ops, 79 }; 80 #endif 81 82 void gmac_set_rgmii(struct udevice *dev, u32 tx_delay, u32 rx_delay) 83 { 84 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 85 struct rk_gmac_ops *ops = 86 (struct rk_gmac_ops *)dev_get_driver_data(dev); 87 88 pdata->tx_delay = tx_delay; 89 pdata->rx_delay = rx_delay; 90 91 ops->set_to_rgmii(pdata); 92 } 93 94 static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) 95 { 96 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 97 const char *string; 98 99 string = dev_read_string(dev, "clock_in_out"); 100 if (!strcmp(string, "input")) 101 pdata->clock_input = true; 102 else 103 pdata->clock_input = false; 104 105 /* Check the new naming-style first... */ 106 pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT); 107 pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT); 108 109 /* ... and fall back to the old naming style or default, if necessary */ 110 if (pdata->tx_delay == -ENOENT) 111 pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30); 112 if (pdata->rx_delay == -ENOENT) 113 pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10); 114 115 #ifdef CONFIG_DWC_ETH_QOS 116 return 0; 117 #else 118 return designware_eth_ofdata_to_platdata(dev); 119 #endif 120 } 121 122 #ifndef CONFIG_DWC_ETH_QOS 123 static int px30_gmac_fix_mac_speed(struct rockchip_eth_dev *dev) 124 { 125 struct dw_eth_dev *priv = &dev->dw; 126 struct px30_grf *grf; 127 struct clk clk_speed; 128 int speed, ret; 129 enum { 130 PX30_GMAC_SPEED_SHIFT = 0x2, 131 PX30_GMAC_SPEED_MASK = BIT(2), 132 PX30_GMAC_SPEED_10M = 0, 133 PX30_GMAC_SPEED_100M = BIT(2), 134 }; 135 136 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 137 &clk_speed); 138 if (ret) 139 return ret; 140 141 switch (priv->phydev->speed) { 142 case 10: 143 speed = PX30_GMAC_SPEED_10M; 144 ret = clk_set_rate(&clk_speed, 2500000); 145 if (ret) 146 return ret; 147 break; 148 case 100: 149 speed = PX30_GMAC_SPEED_100M; 150 ret = clk_set_rate(&clk_speed, 25000000); 151 if (ret) 152 return ret; 153 break; 154 default: 155 debug("Unknown phy speed: %d\n", priv->phydev->speed); 156 return -EINVAL; 157 } 158 159 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 160 rk_clrsetreg(&grf->mac_con1, PX30_GMAC_SPEED_MASK, speed); 161 162 return 0; 163 } 164 165 static int rk1808_gmac_fix_mac_speed(struct rockchip_eth_dev *dev) 166 { 167 struct dw_eth_dev *priv = &dev->dw; 168 struct clk clk_speed; 169 int ret; 170 171 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 172 &clk_speed); 173 if (ret) 174 return ret; 175 176 switch (priv->phydev->speed) { 177 case 10: 178 ret = clk_set_rate(&clk_speed, 2500000); 179 if (ret) 180 return ret; 181 break; 182 case 100: 183 ret = clk_set_rate(&clk_speed, 25000000); 184 if (ret) 185 return ret; 186 break; 187 case 1000: 188 ret = clk_set_rate(&clk_speed, 125000000); 189 if (ret) 190 return ret; 191 break; 192 default: 193 debug("Unknown phy speed: %d\n", priv->phydev->speed); 194 return -EINVAL; 195 } 196 197 return 0; 198 } 199 200 static int rk3228_gmac_fix_mac_speed(struct rockchip_eth_dev *dev) 201 { 202 struct dw_eth_dev *priv = &dev->dw; 203 struct rk322x_grf *grf; 204 int clk; 205 enum { 206 RK3228_GMAC_CLK_SEL_SHIFT = 8, 207 RK3228_GMAC_CLK_SEL_MASK = GENMASK(9, 8), 208 RK3228_GMAC_CLK_SEL_125M = 0 << 8, 209 RK3228_GMAC_CLK_SEL_25M = 3 << 8, 210 RK3228_GMAC_CLK_SEL_2_5M = 2 << 8, 211 }; 212 213 switch (priv->phydev->speed) { 214 case 10: 215 clk = RK3228_GMAC_CLK_SEL_2_5M; 216 break; 217 case 100: 218 clk = RK3228_GMAC_CLK_SEL_25M; 219 break; 220 case 1000: 221 clk = RK3228_GMAC_CLK_SEL_125M; 222 break; 223 default: 224 debug("Unknown phy speed: %d\n", priv->phydev->speed); 225 return -EINVAL; 226 } 227 228 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 229 rk_clrsetreg(&grf->mac_con[1], RK3228_GMAC_CLK_SEL_MASK, clk); 230 231 return 0; 232 } 233 234 static int rk3288_gmac_fix_mac_speed(struct rockchip_eth_dev *dev) 235 { 236 struct dw_eth_dev *priv = &dev->dw; 237 struct rk3288_grf *grf; 238 int clk; 239 240 switch (priv->phydev->speed) { 241 case 10: 242 clk = RK3288_GMAC_CLK_SEL_2_5M; 243 break; 244 case 100: 245 clk = RK3288_GMAC_CLK_SEL_25M; 246 break; 247 case 1000: 248 clk = RK3288_GMAC_CLK_SEL_125M; 249 break; 250 default: 251 debug("Unknown phy speed: %d\n", priv->phydev->speed); 252 return -EINVAL; 253 } 254 255 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 256 rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk); 257 258 return 0; 259 } 260 261 static int rk3308_gmac_fix_mac_speed(struct rockchip_eth_dev *dev) 262 { 263 struct dw_eth_dev *priv = &dev->dw; 264 struct rk3308_grf *grf; 265 struct clk clk_speed; 266 int speed, ret; 267 enum { 268 RK3308_GMAC_SPEED_SHIFT = 0x0, 269 RK3308_GMAC_SPEED_MASK = BIT(0), 270 RK3308_GMAC_SPEED_10M = 0, 271 RK3308_GMAC_SPEED_100M = BIT(0), 272 }; 273 274 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 275 &clk_speed); 276 if (ret) 277 return ret; 278 279 switch (priv->phydev->speed) { 280 case 10: 281 speed = RK3308_GMAC_SPEED_10M; 282 ret = clk_set_rate(&clk_speed, 2500000); 283 if (ret) 284 return ret; 285 break; 286 case 100: 287 speed = RK3308_GMAC_SPEED_100M; 288 ret = clk_set_rate(&clk_speed, 25000000); 289 if (ret) 290 return ret; 291 break; 292 default: 293 debug("Unknown phy speed: %d\n", priv->phydev->speed); 294 return -EINVAL; 295 } 296 297 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 298 rk_clrsetreg(&grf->mac_con0, RK3308_GMAC_SPEED_MASK, speed); 299 300 return 0; 301 } 302 303 static int rk3328_gmac_fix_mac_speed(struct rockchip_eth_dev *dev) 304 { 305 struct dw_eth_dev *priv = &dev->dw; 306 struct rk3328_grf_regs *grf; 307 int clk; 308 enum { 309 RK3328_GMAC_CLK_SEL_SHIFT = 11, 310 RK3328_GMAC_CLK_SEL_MASK = GENMASK(12, 11), 311 RK3328_GMAC_CLK_SEL_125M = 0 << 11, 312 RK3328_GMAC_CLK_SEL_25M = 3 << 11, 313 RK3328_GMAC_CLK_SEL_2_5M = 2 << 11, 314 }; 315 316 switch (priv->phydev->speed) { 317 case 10: 318 clk = RK3328_GMAC_CLK_SEL_2_5M; 319 break; 320 case 100: 321 clk = RK3328_GMAC_CLK_SEL_25M; 322 break; 323 case 1000: 324 clk = RK3328_GMAC_CLK_SEL_125M; 325 break; 326 default: 327 debug("Unknown phy speed: %d\n", priv->phydev->speed); 328 return -EINVAL; 329 } 330 331 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 332 rk_clrsetreg(&grf->mac_con[1], RK3328_GMAC_CLK_SEL_MASK, clk); 333 334 return 0; 335 } 336 337 static int rk3368_gmac_fix_mac_speed(struct rockchip_eth_dev *dev) 338 { 339 struct dw_eth_dev *priv = &dev->dw; 340 struct rk3368_grf *grf; 341 int clk; 342 enum { 343 RK3368_GMAC_CLK_SEL_2_5M = 2 << 4, 344 RK3368_GMAC_CLK_SEL_25M = 3 << 4, 345 RK3368_GMAC_CLK_SEL_125M = 0 << 4, 346 RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4), 347 }; 348 349 switch (priv->phydev->speed) { 350 case 10: 351 clk = RK3368_GMAC_CLK_SEL_2_5M; 352 break; 353 case 100: 354 clk = RK3368_GMAC_CLK_SEL_25M; 355 break; 356 case 1000: 357 clk = RK3368_GMAC_CLK_SEL_125M; 358 break; 359 default: 360 debug("Unknown phy speed: %d\n", priv->phydev->speed); 361 return -EINVAL; 362 } 363 364 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 365 rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk); 366 367 return 0; 368 } 369 370 static int rk3399_gmac_fix_mac_speed(struct rockchip_eth_dev *dev) 371 { 372 struct dw_eth_dev *priv = &dev->dw; 373 struct rk3399_grf_regs *grf; 374 int clk; 375 376 switch (priv->phydev->speed) { 377 case 10: 378 clk = RK3399_GMAC_CLK_SEL_2_5M; 379 break; 380 case 100: 381 clk = RK3399_GMAC_CLK_SEL_25M; 382 break; 383 case 1000: 384 clk = RK3399_GMAC_CLK_SEL_125M; 385 break; 386 default: 387 debug("Unknown phy speed: %d\n", priv->phydev->speed); 388 return -EINVAL; 389 } 390 391 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 392 rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk); 393 394 return 0; 395 } 396 397 static int rv1108_set_rmii_speed(struct rockchip_eth_dev *dev) 398 { 399 struct dw_eth_dev *priv = &dev->dw; 400 struct rv1108_grf *grf; 401 int clk, speed; 402 enum { 403 RV1108_GMAC_SPEED_MASK = BIT(2), 404 RV1108_GMAC_SPEED_10M = 0 << 2, 405 RV1108_GMAC_SPEED_100M = 1 << 2, 406 RV1108_GMAC_CLK_SEL_MASK = BIT(7), 407 RV1108_GMAC_CLK_SEL_2_5M = 0 << 7, 408 RV1108_GMAC_CLK_SEL_25M = 1 << 7, 409 }; 410 411 switch (priv->phydev->speed) { 412 case 10: 413 clk = RV1108_GMAC_CLK_SEL_2_5M; 414 speed = RV1108_GMAC_SPEED_10M; 415 break; 416 case 100: 417 clk = RV1108_GMAC_CLK_SEL_25M; 418 speed = RV1108_GMAC_SPEED_100M; 419 break; 420 default: 421 debug("Unknown phy speed: %d\n", priv->phydev->speed); 422 return -EINVAL; 423 } 424 425 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 426 rk_clrsetreg(&grf->gmac_con0, 427 RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK, 428 clk | speed); 429 430 return 0; 431 } 432 #else 433 static int rv1126_set_rgmii_speed(struct rockchip_eth_dev *dev) 434 { 435 struct eqos_priv *priv = &dev->eqos; 436 struct clk clk_speed; 437 int ret; 438 439 ret = clk_get_by_name(priv->phy->dev, "clk_mac_speed", 440 &clk_speed); 441 if (ret) { 442 printf("%s~(ret=%d):\n", __func__, ret); 443 return ret; 444 } 445 446 switch ( priv->phy->speed) { 447 case 10: 448 ret = clk_set_rate(&clk_speed, 2500000); 449 if (ret) 450 return ret; 451 break; 452 case 100: 453 ret = clk_set_rate(&clk_speed, 25000000); 454 if (ret) 455 return ret; 456 break; 457 case 1000: 458 ret = clk_set_rate(&clk_speed, 125000000); 459 if (ret) 460 return ret; 461 break; 462 default: 463 debug("Unknown phy speed: %d\n", priv->phy->speed); 464 return -EINVAL; 465 } 466 467 return 0; 468 } 469 #endif 470 471 #ifndef CONFIG_DWC_ETH_QOS 472 static void px30_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 473 { 474 struct px30_grf *grf; 475 enum { 476 px30_GMAC_PHY_INTF_SEL_SHIFT = 4, 477 px30_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 6), 478 px30_GMAC_PHY_INTF_SEL_RMII = BIT(6), 479 }; 480 481 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 482 483 rk_clrsetreg(&grf->mac_con1, 484 px30_GMAC_PHY_INTF_SEL_MASK, 485 px30_GMAC_PHY_INTF_SEL_RMII); 486 } 487 488 static void rk1808_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 489 { 490 struct rk1808_grf *grf; 491 enum { 492 RK1808_GMAC_PHY_INTF_SEL_SHIFT = 4, 493 RK1808_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 494 RK1808_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 495 496 RK1808_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 497 RK1808_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 498 RK1808_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 499 500 RK1808_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 501 RK1808_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 502 RK1808_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 503 }; 504 enum { 505 RK1808_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 506 RK1808_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 7), 507 508 RK1808_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 509 RK1808_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 510 }; 511 512 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 513 rk_clrsetreg(&grf->mac_con1, 514 RK1808_GMAC_PHY_INTF_SEL_MASK | 515 RK1808_RXCLK_DLY_ENA_GMAC_MASK | 516 RK1808_TXCLK_DLY_ENA_GMAC_MASK, 517 RK1808_GMAC_PHY_INTF_SEL_RGMII | 518 RK1808_RXCLK_DLY_ENA_GMAC_ENABLE | 519 RK1808_TXCLK_DLY_ENA_GMAC_ENABLE); 520 521 rk_clrsetreg(&grf->mac_con0, 522 RK1808_CLK_RX_DL_CFG_GMAC_MASK | 523 RK1808_CLK_TX_DL_CFG_GMAC_MASK, 524 pdata->rx_delay << RK1808_CLK_RX_DL_CFG_GMAC_SHIFT | 525 pdata->tx_delay << RK1808_CLK_TX_DL_CFG_GMAC_SHIFT); 526 } 527 528 static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 529 { 530 struct rk322x_grf *grf; 531 enum { 532 RK3228_RMII_MODE_SHIFT = 10, 533 RK3228_RMII_MODE_MASK = BIT(10), 534 535 RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4, 536 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 537 RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 538 539 RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 540 RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 541 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 542 543 RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 544 RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 545 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 546 }; 547 enum { 548 RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 549 RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 550 551 RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 552 RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 553 }; 554 555 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 556 rk_clrsetreg(&grf->mac_con[1], 557 RK3228_RMII_MODE_MASK | 558 RK3228_GMAC_PHY_INTF_SEL_MASK | 559 RK3228_RXCLK_DLY_ENA_GMAC_MASK | 560 RK3228_TXCLK_DLY_ENA_GMAC_MASK, 561 RK3228_GMAC_PHY_INTF_SEL_RGMII | 562 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE | 563 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE); 564 565 rk_clrsetreg(&grf->mac_con[0], 566 RK3228_CLK_RX_DL_CFG_GMAC_MASK | 567 RK3228_CLK_TX_DL_CFG_GMAC_MASK, 568 pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT | 569 pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT); 570 } 571 572 static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 573 { 574 struct rk3288_grf *grf; 575 576 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 577 rk_clrsetreg(&grf->soc_con1, 578 RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK, 579 RK3288_GMAC_PHY_INTF_SEL_RGMII); 580 581 rk_clrsetreg(&grf->soc_con3, 582 RK3288_RXCLK_DLY_ENA_GMAC_MASK | 583 RK3288_TXCLK_DLY_ENA_GMAC_MASK | 584 RK3288_CLK_RX_DL_CFG_GMAC_MASK | 585 RK3288_CLK_TX_DL_CFG_GMAC_MASK, 586 RK3288_RXCLK_DLY_ENA_GMAC_ENABLE | 587 RK3288_TXCLK_DLY_ENA_GMAC_ENABLE | 588 pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT | 589 pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT); 590 } 591 592 static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 593 { 594 struct rk3308_grf *grf; 595 enum { 596 RK3308_GMAC_PHY_INTF_SEL_SHIFT = 2, 597 RK3308_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 2), 598 RK3308_GMAC_PHY_INTF_SEL_RMII = BIT(4), 599 }; 600 601 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 602 603 rk_clrsetreg(&grf->mac_con0, 604 RK3308_GMAC_PHY_INTF_SEL_MASK, 605 RK3308_GMAC_PHY_INTF_SEL_RMII); 606 } 607 608 static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 609 { 610 struct rk3328_grf_regs *grf; 611 enum { 612 RK3328_RMII_MODE_SHIFT = 9, 613 RK3328_RMII_MODE_MASK = BIT(9), 614 615 RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4, 616 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 617 RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 618 619 RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 620 RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 621 RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 622 623 RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 624 RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 625 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 626 }; 627 enum { 628 RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 629 RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 630 631 RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 632 RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 633 }; 634 635 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 636 rk_clrsetreg(&grf->mac_con[1], 637 RK3328_RMII_MODE_MASK | 638 RK3328_GMAC_PHY_INTF_SEL_MASK | 639 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 640 RK3328_TXCLK_DLY_ENA_GMAC_MASK, 641 RK3328_GMAC_PHY_INTF_SEL_RGMII | 642 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 643 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE); 644 645 rk_clrsetreg(&grf->mac_con[0], 646 RK3328_CLK_RX_DL_CFG_GMAC_MASK | 647 RK3328_CLK_TX_DL_CFG_GMAC_MASK, 648 pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT | 649 pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT); 650 } 651 652 static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 653 { 654 struct rk3368_grf *grf; 655 enum { 656 RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9, 657 RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9), 658 RK3368_RMII_MODE_MASK = BIT(6), 659 RK3368_RMII_MODE = BIT(6), 660 }; 661 enum { 662 RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15), 663 RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 664 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15), 665 RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7), 666 RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 667 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7), 668 RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8, 669 RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 670 RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0, 671 RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 672 }; 673 674 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 675 rk_clrsetreg(&grf->soc_con15, 676 RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK, 677 RK3368_GMAC_PHY_INTF_SEL_RGMII); 678 679 rk_clrsetreg(&grf->soc_con16, 680 RK3368_RXCLK_DLY_ENA_GMAC_MASK | 681 RK3368_TXCLK_DLY_ENA_GMAC_MASK | 682 RK3368_CLK_RX_DL_CFG_GMAC_MASK | 683 RK3368_CLK_TX_DL_CFG_GMAC_MASK, 684 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE | 685 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE | 686 pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT | 687 pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT); 688 } 689 690 static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 691 { 692 struct rk3399_grf_regs *grf; 693 694 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 695 696 rk_clrsetreg(&grf->soc_con5, 697 RK3399_GMAC_PHY_INTF_SEL_MASK, 698 RK3399_GMAC_PHY_INTF_SEL_RGMII); 699 700 rk_clrsetreg(&grf->soc_con6, 701 RK3399_RXCLK_DLY_ENA_GMAC_MASK | 702 RK3399_TXCLK_DLY_ENA_GMAC_MASK | 703 RK3399_CLK_RX_DL_CFG_GMAC_MASK | 704 RK3399_CLK_TX_DL_CFG_GMAC_MASK, 705 RK3399_RXCLK_DLY_ENA_GMAC_ENABLE | 706 RK3399_TXCLK_DLY_ENA_GMAC_ENABLE | 707 pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT | 708 pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT); 709 } 710 711 static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 712 { 713 struct rv1108_grf *grf; 714 715 enum { 716 RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 717 RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4, 718 }; 719 720 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 721 rk_clrsetreg(&grf->gmac_con0, 722 RV1108_GMAC_PHY_INTF_SEL_MASK, 723 RV1108_GMAC_PHY_INTF_SEL_RMII); 724 } 725 #else 726 static void rv1126_set_to_rmii(struct gmac_rockchip_platdata *pdata) 727 { 728 struct rv1126_grf *grf; 729 730 enum { 731 RV1126_GMAC_PHY_INTF_SEL_SHIFT = 4, 732 RV1126_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 733 RV1126_GMAC_PHY_INTF_SEL_RMII = BIT(6), 734 }; 735 736 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 737 738 rk_clrsetreg(&grf->mac_con0, 739 RV1126_GMAC_PHY_INTF_SEL_MASK, 740 RV1126_GMAC_PHY_INTF_SEL_RMII); 741 } 742 743 static void rv1126_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 744 { 745 struct rv1126_grf *grf; 746 747 enum { 748 RV1126_GMAC_PHY_INTF_SEL_SHIFT = 4, 749 RV1126_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 750 RV1126_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 751 752 RV1126_RXCLK_M1_DLY_ENA_GMAC_MASK = BIT(3), 753 RV1126_RXCLK_M1_DLY_ENA_GMAC_DISABLE = 0, 754 RV1126_RXCLK_M1_DLY_ENA_GMAC_ENABLE = BIT(3), 755 756 RV1126_TXCLK_M1_DLY_ENA_GMAC_MASK = BIT(2), 757 RV1126_TXCLK_M1_DLY_ENA_GMAC_DISABLE = 0, 758 RV1126_TXCLK_M1_DLY_ENA_GMAC_ENABLE = BIT(2), 759 760 RV1126_RXCLK_M0_DLY_ENA_GMAC_MASK = BIT(1), 761 RV1126_RXCLK_M0_DLY_ENA_GMAC_DISABLE = 0, 762 RV1126_RXCLK_M0_DLY_ENA_GMAC_ENABLE = BIT(1), 763 764 RV1126_TXCLK_M0_DLY_ENA_GMAC_MASK = BIT(0), 765 RV1126_TXCLK_M0_DLY_ENA_GMAC_DISABLE = 0, 766 RV1126_TXCLK_M0_DLY_ENA_GMAC_ENABLE = BIT(0), 767 }; 768 enum { 769 RV1126_M0_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 770 RV1126_M0_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 771 772 RV1126_M0_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 773 RV1126_M0_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 774 }; 775 enum { 776 RV1126_M1_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 777 RV1126_M1_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 778 779 RV1126_M1_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 780 RV1126_M1_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 781 }; 782 783 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 784 785 rk_clrsetreg(&grf->mac_con0, 786 RV1126_TXCLK_M0_DLY_ENA_GMAC_MASK | 787 RV1126_RXCLK_M0_DLY_ENA_GMAC_MASK | 788 RV1126_TXCLK_M1_DLY_ENA_GMAC_MASK | 789 RV1126_RXCLK_M1_DLY_ENA_GMAC_MASK | 790 RV1126_GMAC_PHY_INTF_SEL_MASK, 791 RV1126_TXCLK_M0_DLY_ENA_GMAC_ENABLE | 792 RV1126_RXCLK_M0_DLY_ENA_GMAC_ENABLE | 793 RV1126_TXCLK_M1_DLY_ENA_GMAC_ENABLE | 794 RV1126_RXCLK_M1_DLY_ENA_GMAC_ENABLE | 795 RV1126_GMAC_PHY_INTF_SEL_RGMII); 796 797 rk_clrsetreg(&grf->mac_con1, 798 RV1126_M0_CLK_RX_DL_CFG_GMAC_MASK | 799 RV1126_M0_CLK_TX_DL_CFG_GMAC_MASK, 800 pdata->rx_delay << RV1126_M0_CLK_RX_DL_CFG_GMAC_SHIFT | 801 pdata->tx_delay << RV1126_M0_CLK_TX_DL_CFG_GMAC_SHIFT); 802 803 rk_clrsetreg(&grf->mac_con2, 804 RV1126_M1_CLK_RX_DL_CFG_GMAC_MASK | 805 RV1126_M1_CLK_TX_DL_CFG_GMAC_MASK, 806 pdata->rx_delay << RV1126_M1_CLK_RX_DL_CFG_GMAC_SHIFT | 807 pdata->tx_delay << RV1126_M1_CLK_TX_DL_CFG_GMAC_SHIFT); 808 } 809 #endif 810 811 static int gmac_rockchip_probe(struct udevice *dev) 812 { 813 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 814 struct rk_gmac_ops *ops = 815 (struct rk_gmac_ops *)dev_get_driver_data(dev); 816 #ifdef CONFIG_DWC_ETH_QOS 817 struct eqos_config *config; 818 #else 819 struct dw_eth_pdata *dw_pdata; 820 #endif 821 struct eth_pdata *eth_pdata; 822 struct clk clk; 823 ulong rate; 824 int ret; 825 826 #ifdef CONFIG_DWC_ETH_QOS 827 eth_pdata = &pdata->eth_pdata; 828 config = (struct eqos_config *)&ops->config; 829 memcpy(config, &eqos_rockchip_config, sizeof(struct eqos_config)); 830 eth_pdata->phy_interface = config->ops->eqos_get_interface(dev); 831 #else 832 dw_pdata = &pdata->dw_eth_pdata; 833 eth_pdata = &dw_pdata->eth_pdata; 834 #endif 835 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 836 ret = clk_set_defaults(dev); 837 if (ret) 838 debug("%s clk_set_defaults failed %d\n", __func__, ret); 839 840 ret = clk_get_by_index(dev, 0, &clk); 841 if (ret) 842 return ret; 843 844 switch (eth_pdata->phy_interface) { 845 case PHY_INTERFACE_MODE_RGMII: 846 /* 847 * If the gmac clock is from internal pll, need to set and 848 * check the return value for gmac clock at RGMII mode. If 849 * the gmac clock is from external source, the clock rate 850 * is not set, because of it is bypassed. 851 */ 852 if (!pdata->clock_input) { 853 rate = clk_set_rate(&clk, 125000000); 854 if (rate != 125000000) 855 return -EINVAL; 856 } 857 858 /* Set to RGMII mode */ 859 if (ops->set_to_rgmii) 860 ops->set_to_rgmii(pdata); 861 else 862 return -EPERM; 863 864 break; 865 case PHY_INTERFACE_MODE_RMII: 866 /* The commet is the same as RGMII mode */ 867 if (!pdata->clock_input) { 868 rate = clk_set_rate(&clk, 50000000); 869 if (rate != 50000000) 870 return -EINVAL; 871 } 872 873 /* Set to RMII mode */ 874 if (ops->set_to_rmii) 875 ops->set_to_rmii(pdata); 876 else 877 return -EPERM; 878 879 break; 880 default: 881 debug("NO interface defined!\n"); 882 return -ENXIO; 883 } 884 885 #ifdef CONFIG_DWC_ETH_QOS 886 return eqos_probe(dev); 887 #else 888 return designware_eth_probe(dev); 889 #endif 890 } 891 892 static int gmac_rockchip_eth_write_hwaddr(struct udevice *dev) 893 { 894 #if defined(CONFIG_DWC_ETH_QOS) 895 return eqos_write_hwaddr(dev); 896 #else 897 return designware_eth_write_hwaddr(dev); 898 #endif 899 } 900 901 static int gmac_rockchip_eth_free_pkt(struct udevice *dev, uchar *packet, 902 int length) 903 { 904 #ifdef CONFIG_DWC_ETH_QOS 905 return eqos_free_pkt(dev, packet, length); 906 #else 907 return designware_eth_free_pkt(dev, packet, length); 908 #endif 909 } 910 911 static int gmac_rockchip_eth_send(struct udevice *dev, void *packet, 912 int length) 913 { 914 #ifdef CONFIG_DWC_ETH_QOS 915 return eqos_send(dev, packet, length); 916 #else 917 return designware_eth_send(dev, packet, length); 918 #endif 919 } 920 921 static int gmac_rockchip_eth_recv(struct udevice *dev, int flags, 922 uchar **packetp) 923 { 924 #ifdef CONFIG_DWC_ETH_QOS 925 return eqos_recv(dev, flags, packetp); 926 #else 927 return designware_eth_recv(dev, flags, packetp); 928 #endif 929 } 930 931 static int gmac_rockchip_eth_start(struct udevice *dev) 932 { 933 struct rockchip_eth_dev *priv = dev_get_priv(dev); 934 struct rk_gmac_ops *ops = 935 (struct rk_gmac_ops *)dev_get_driver_data(dev); 936 #ifndef CONFIG_DWC_ETH_QOS 937 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 938 struct dw_eth_pdata *dw_pdata; 939 struct eth_pdata *eth_pdata; 940 #endif 941 int ret; 942 943 #ifdef CONFIG_DWC_ETH_QOS 944 ret = eqos_init(dev); 945 #else 946 dw_pdata = &pdata->dw_eth_pdata; 947 eth_pdata = &dw_pdata->eth_pdata; 948 ret = designware_eth_init((struct dw_eth_dev *)priv, 949 eth_pdata->enetaddr); 950 #endif 951 if (ret) 952 return ret; 953 ret = ops->fix_mac_speed(priv); 954 if (ret) 955 return ret; 956 957 #ifdef CONFIG_DWC_ETH_QOS 958 eqos_enable(dev); 959 #else 960 ret = designware_eth_enable((struct dw_eth_dev *)priv); 961 if (ret) 962 return ret; 963 #endif 964 965 return 0; 966 } 967 968 static void gmac_rockchip_eth_stop(struct udevice *dev) 969 { 970 #ifdef CONFIG_DWC_ETH_QOS 971 eqos_stop(dev); 972 #else 973 designware_eth_stop(dev); 974 #endif 975 } 976 977 const struct eth_ops gmac_rockchip_eth_ops = { 978 .start = gmac_rockchip_eth_start, 979 .send = gmac_rockchip_eth_send, 980 .recv = gmac_rockchip_eth_recv, 981 .free_pkt = gmac_rockchip_eth_free_pkt, 982 .stop = gmac_rockchip_eth_stop, 983 .write_hwaddr = gmac_rockchip_eth_write_hwaddr, 984 }; 985 986 #ifndef CONFIG_DWC_ETH_QOS 987 const struct rk_gmac_ops px30_gmac_ops = { 988 .fix_mac_speed = px30_gmac_fix_mac_speed, 989 .set_to_rmii = px30_gmac_set_to_rmii, 990 }; 991 992 const struct rk_gmac_ops rk1808_gmac_ops = { 993 .fix_mac_speed = rk1808_gmac_fix_mac_speed, 994 .set_to_rgmii = rk1808_gmac_set_to_rgmii, 995 }; 996 997 const struct rk_gmac_ops rk3228_gmac_ops = { 998 .fix_mac_speed = rk3228_gmac_fix_mac_speed, 999 .set_to_rgmii = rk3228_gmac_set_to_rgmii, 1000 }; 1001 1002 const struct rk_gmac_ops rk3288_gmac_ops = { 1003 .fix_mac_speed = rk3288_gmac_fix_mac_speed, 1004 .set_to_rgmii = rk3288_gmac_set_to_rgmii, 1005 }; 1006 1007 const struct rk_gmac_ops rk3308_gmac_ops = { 1008 .fix_mac_speed = rk3308_gmac_fix_mac_speed, 1009 .set_to_rmii = rk3308_gmac_set_to_rmii, 1010 }; 1011 1012 const struct rk_gmac_ops rk3328_gmac_ops = { 1013 .fix_mac_speed = rk3328_gmac_fix_mac_speed, 1014 .set_to_rgmii = rk3328_gmac_set_to_rgmii, 1015 }; 1016 1017 const struct rk_gmac_ops rk3368_gmac_ops = { 1018 .fix_mac_speed = rk3368_gmac_fix_mac_speed, 1019 .set_to_rgmii = rk3368_gmac_set_to_rgmii, 1020 }; 1021 1022 const struct rk_gmac_ops rk3399_gmac_ops = { 1023 .fix_mac_speed = rk3399_gmac_fix_mac_speed, 1024 .set_to_rgmii = rk3399_gmac_set_to_rgmii, 1025 }; 1026 1027 const struct rk_gmac_ops rv1108_gmac_ops = { 1028 .fix_mac_speed = rv1108_set_rmii_speed, 1029 .set_to_rmii = rv1108_gmac_set_to_rmii, 1030 }; 1031 #else 1032 const struct rk_gmac_ops rv1126_gmac_ops = { 1033 .fix_mac_speed = rv1126_set_rgmii_speed, 1034 .set_to_rgmii = rv1126_set_to_rgmii, 1035 .set_to_rmii = rv1126_set_to_rmii, 1036 }; 1037 #endif 1038 1039 static const struct udevice_id rockchip_gmac_ids[] = { 1040 #ifndef CONFIG_DWC_ETH_QOS 1041 { .compatible = "rockchip,px30-gmac", 1042 .data = (ulong)&px30_gmac_ops }, 1043 { .compatible = "rockchip,rk1808-gmac", 1044 .data = (ulong)&rk1808_gmac_ops }, 1045 { .compatible = "rockchip,rk3228-gmac", 1046 .data = (ulong)&rk3228_gmac_ops }, 1047 { .compatible = "rockchip,rk3288-gmac", 1048 .data = (ulong)&rk3288_gmac_ops }, 1049 { .compatible = "rockchip,rk3308-mac", 1050 .data = (ulong)&rk3308_gmac_ops }, 1051 { .compatible = "rockchip,rk3328-gmac", 1052 .data = (ulong)&rk3328_gmac_ops }, 1053 { .compatible = "rockchip,rk3368-gmac", 1054 .data = (ulong)&rk3368_gmac_ops }, 1055 { .compatible = "rockchip,rk3399-gmac", 1056 .data = (ulong)&rk3399_gmac_ops }, 1057 { .compatible = "rockchip,rv1108-gmac", 1058 .data = (ulong)&rv1108_gmac_ops }, 1059 #else 1060 { .compatible = "rockchip,rv1126-gmac", 1061 .data = (ulong)&rv1126_gmac_ops }, 1062 #endif 1063 { } 1064 }; 1065 1066 U_BOOT_DRIVER(eth_gmac_rockchip) = { 1067 .name = "gmac_rockchip", 1068 .id = UCLASS_ETH, 1069 .of_match = rockchip_gmac_ids, 1070 .ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata, 1071 .probe = gmac_rockchip_probe, 1072 .ops = &gmac_rockchip_eth_ops, 1073 .priv_auto_alloc_size = sizeof(struct rockchip_eth_dev), 1074 .platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata), 1075 .flags = DM_FLAG_ALLOC_PRIV_DMA, 1076 }; 1077