1 /* 2 * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Rockchip GMAC ethernet IP driver for U-Boot 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <clk.h> 12 #include <misc.h> 13 #include <phy.h> 14 #include <reset.h> 15 #include <syscon.h> 16 #include <asm/io.h> 17 #include <asm/arch/periph.h> 18 #include <asm/arch/clock.h> 19 #include <asm/arch/hardware.h> 20 #ifdef CONFIG_DWC_ETH_QOS 21 #include <asm/arch/grf_rk3506.h> 22 #include <asm/arch/grf_rk3528.h> 23 #include <asm/arch/grf_rk3562.h> 24 #include <asm/arch/ioc_rk3562.h> 25 #include <asm/arch/grf_rk3568.h> 26 #include <asm/arch/grf_rk3588.h> 27 #include <asm/arch/grf_rv1103b.h> 28 #include <asm/arch/grf_rv1106.h> 29 #include <asm/arch/grf_rv1126.h> 30 #include "dwc_eth_qos.h" 31 #else 32 #include <asm/arch/grf_px30.h> 33 #include <asm/arch/grf_rk1808.h> 34 #include <asm/arch/grf_rk322x.h> 35 #include <asm/arch/grf_rk3288.h> 36 #include <asm/arch/grf_rk3308.h> 37 #include <asm/arch/grf_rk3328.h> 38 #include <asm/arch/grf_rk3368.h> 39 #include <asm/arch/grf_rk3399.h> 40 #include <asm/arch/grf_rv1108.h> 41 #include "designware.h" 42 #include <dt-bindings/clock/rk3288-cru.h> 43 #endif 44 #include <dm/pinctrl.h> 45 #include <dm/of_access.h> 46 47 DECLARE_GLOBAL_DATA_PTR; 48 49 struct rockchip_eth_dev { 50 #ifdef CONFIG_DWC_ETH_QOS 51 struct eqos_priv eqos; 52 #else 53 struct dw_eth_dev dw; 54 #endif 55 int phy_interface; 56 }; 57 58 /* 59 * Platform data for the gmac 60 * 61 * dw_eth_pdata: Required platform data for designware driver (must be first) 62 */ 63 struct gmac_rockchip_platdata { 64 #ifndef CONFIG_DWC_ETH_QOS 65 struct dw_eth_pdata dw_eth_pdata; 66 #else 67 struct eth_pdata eth_pdata; 68 #endif 69 struct reset_ctl phy_reset; 70 bool integrated_phy; 71 bool clock_input; 72 int phy_interface; 73 int tx_delay; 74 int rx_delay; 75 int bus_id; 76 }; 77 78 struct rk_gmac_ops { 79 #ifdef CONFIG_DWC_ETH_QOS 80 const struct eqos_config config; 81 #endif 82 int (*fix_mac_speed)(struct gmac_rockchip_platdata *pdata, 83 struct rockchip_eth_dev *dev); 84 void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata); 85 void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata); 86 void (*set_clock_selection)(struct gmac_rockchip_platdata *pdata); 87 void (*integrated_phy_powerup)(struct gmac_rockchip_platdata *pdata); 88 }; 89 90 #ifdef CONFIG_DWC_ETH_QOS 91 static const struct eqos_config eqos_rockchip_config = { 92 .reg_access_always_ok = false, 93 .mdio_wait = 10000, 94 .swr_wait = 200, 95 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED, 96 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_100_150, 97 .ops = &eqos_rockchip_ops, 98 }; 99 #endif 100 101 void gmac_set_rgmii(struct udevice *dev, u32 tx_delay, u32 rx_delay) 102 { 103 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 104 struct rk_gmac_ops *ops = 105 (struct rk_gmac_ops *)dev_get_driver_data(dev); 106 107 pdata->tx_delay = tx_delay; 108 pdata->rx_delay = rx_delay; 109 110 ops->set_to_rgmii(pdata); 111 } 112 113 static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) 114 { 115 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 116 struct ofnode_phandle_args args; 117 struct udevice *phydev; 118 const char *string; 119 int ret; 120 121 string = dev_read_string(dev, "clock_in_out"); 122 if (!strcmp(string, "input")) 123 pdata->clock_input = true; 124 else 125 pdata->clock_input = false; 126 127 /* If phy-handle property is passed from DT, use it as the PHY */ 128 ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &args); 129 if (ret) { 130 debug("Cannot get phy phandle: ret=%d\n", ret); 131 pdata->integrated_phy = dev_read_bool(dev, "phy-is-integrated"); 132 } else { 133 debug("Found phy-handle subnode\n"); 134 pdata->integrated_phy = ofnode_read_bool(args.node, 135 "phy-is-integrated"); 136 } 137 138 if (pdata->integrated_phy) { 139 ret = reset_get_by_name(dev, "mac-phy", &pdata->phy_reset); 140 if (ret) { 141 ret = uclass_get_device_by_ofnode(UCLASS_ETH_PHY, args.node, &phydev); 142 if (ret) { 143 debug("Get phydev by ofnode failed: err=%d\n", ret); 144 return ret; 145 } 146 147 ret = reset_get_by_index(phydev, 0, &pdata->phy_reset); 148 if (ret) { 149 debug("No PHY reset control found: ret=%d\n", ret); 150 return ret; 151 } 152 } 153 } 154 155 /* Check the new naming-style first... */ 156 pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT); 157 pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT); 158 159 /* ... and fall back to the old naming style or default, if necessary */ 160 if (pdata->tx_delay == -ENOENT) 161 pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30); 162 if (pdata->rx_delay == -ENOENT) 163 pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10); 164 165 #ifdef CONFIG_DWC_ETH_QOS 166 return 0; 167 #else 168 return designware_eth_ofdata_to_platdata(dev); 169 #endif 170 } 171 172 #ifndef CONFIG_DWC_ETH_QOS 173 static int px30_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 174 struct rockchip_eth_dev *dev) 175 { 176 struct dw_eth_dev *priv = &dev->dw; 177 struct px30_grf *grf; 178 struct clk clk_speed; 179 int speed, ret; 180 enum { 181 PX30_GMAC_SPEED_SHIFT = 0x2, 182 PX30_GMAC_SPEED_MASK = BIT(2), 183 PX30_GMAC_SPEED_10M = 0, 184 PX30_GMAC_SPEED_100M = BIT(2), 185 }; 186 187 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 188 &clk_speed); 189 if (ret) 190 return ret; 191 192 switch (priv->phydev->speed) { 193 case 10: 194 speed = PX30_GMAC_SPEED_10M; 195 ret = clk_set_rate(&clk_speed, 2500000); 196 if (ret) 197 return ret; 198 break; 199 case 100: 200 speed = PX30_GMAC_SPEED_100M; 201 ret = clk_set_rate(&clk_speed, 25000000); 202 if (ret) 203 return ret; 204 break; 205 default: 206 debug("Unknown phy speed: %d\n", priv->phydev->speed); 207 return -EINVAL; 208 } 209 210 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 211 rk_clrsetreg(&grf->mac_con1, PX30_GMAC_SPEED_MASK, speed); 212 213 return 0; 214 } 215 216 static int rk1808_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 217 struct rockchip_eth_dev *dev) 218 { 219 struct dw_eth_dev *priv = &dev->dw; 220 struct clk clk_speed; 221 int ret; 222 223 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 224 &clk_speed); 225 if (ret) 226 return ret; 227 228 switch (priv->phydev->speed) { 229 case 10: 230 ret = clk_set_rate(&clk_speed, 2500000); 231 if (ret) 232 return ret; 233 break; 234 case 100: 235 ret = clk_set_rate(&clk_speed, 25000000); 236 if (ret) 237 return ret; 238 break; 239 case 1000: 240 ret = clk_set_rate(&clk_speed, 125000000); 241 if (ret) 242 return ret; 243 break; 244 default: 245 debug("Unknown phy speed: %d\n", priv->phydev->speed); 246 return -EINVAL; 247 } 248 249 return 0; 250 } 251 252 static int rk3228_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 253 struct rockchip_eth_dev *dev) 254 { 255 struct dw_eth_dev *priv = &dev->dw; 256 struct rk322x_grf *grf; 257 int clk; 258 enum { 259 RK3228_GMAC_CLK_SEL_SHIFT = 8, 260 RK3228_GMAC_CLK_SEL_MASK = GENMASK(9, 8), 261 RK3228_GMAC_CLK_SEL_125M = 0 << 8, 262 RK3228_GMAC_CLK_SEL_25M = 3 << 8, 263 RK3228_GMAC_CLK_SEL_2_5M = 2 << 8, 264 265 RK3228_GMAC_RMII_CLK_MASK = BIT(7), 266 RK3228_GMAC_RMII_CLK_2_5M = 0, 267 RK3228_GMAC_RMII_CLK_25M = BIT(7), 268 269 RK3228_GMAC_RMII_SPEED_MASK = BIT(2), 270 RK3228_GMAC_RMII_SPEED_10 = 0, 271 RK3228_GMAC_RMII_SPEED_100 = BIT(2), 272 }; 273 274 switch (priv->phydev->speed) { 275 case 10: 276 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 277 (RK3228_GMAC_RMII_CLK_2_5M | RK3228_GMAC_RMII_SPEED_10) : 278 RK3228_GMAC_CLK_SEL_2_5M; 279 break; 280 case 100: 281 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 282 (RK3228_GMAC_RMII_CLK_25M | RK3228_GMAC_RMII_SPEED_100) : 283 RK3228_GMAC_CLK_SEL_25M; 284 break; 285 case 1000: 286 clk = RK3228_GMAC_CLK_SEL_125M; 287 break; 288 default: 289 debug("Unknown phy speed: %d\n", priv->phydev->speed); 290 return -EINVAL; 291 } 292 293 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 294 rk_clrsetreg(&grf->mac_con[1], 295 RK3228_GMAC_CLK_SEL_MASK | 296 RK3228_GMAC_RMII_CLK_MASK | 297 RK3228_GMAC_RMII_SPEED_MASK, 298 clk); 299 300 return 0; 301 } 302 303 static int rk3288_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 304 struct rockchip_eth_dev *dev) 305 { 306 struct dw_eth_dev *priv = &dev->dw; 307 struct rk3288_grf *grf; 308 int clk; 309 310 switch (priv->phydev->speed) { 311 case 10: 312 clk = RK3288_GMAC_CLK_SEL_2_5M; 313 break; 314 case 100: 315 clk = RK3288_GMAC_CLK_SEL_25M; 316 break; 317 case 1000: 318 clk = RK3288_GMAC_CLK_SEL_125M; 319 break; 320 default: 321 debug("Unknown phy speed: %d\n", priv->phydev->speed); 322 return -EINVAL; 323 } 324 325 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 326 rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk); 327 328 return 0; 329 } 330 331 static int rk3308_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 332 struct rockchip_eth_dev *dev) 333 { 334 struct dw_eth_dev *priv = &dev->dw; 335 struct rk3308_grf *grf; 336 struct clk clk_speed; 337 int speed, ret; 338 enum { 339 RK3308_GMAC_SPEED_SHIFT = 0x0, 340 RK3308_GMAC_SPEED_MASK = BIT(0), 341 RK3308_GMAC_SPEED_10M = 0, 342 RK3308_GMAC_SPEED_100M = BIT(0), 343 }; 344 345 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 346 &clk_speed); 347 if (ret) 348 return ret; 349 350 switch (priv->phydev->speed) { 351 case 10: 352 speed = RK3308_GMAC_SPEED_10M; 353 ret = clk_set_rate(&clk_speed, 2500000); 354 if (ret) 355 return ret; 356 break; 357 case 100: 358 speed = RK3308_GMAC_SPEED_100M; 359 ret = clk_set_rate(&clk_speed, 25000000); 360 if (ret) 361 return ret; 362 break; 363 default: 364 debug("Unknown phy speed: %d\n", priv->phydev->speed); 365 return -EINVAL; 366 } 367 368 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 369 rk_clrsetreg(&grf->mac_con0, RK3308_GMAC_SPEED_MASK, speed); 370 371 return 0; 372 } 373 374 static int rk3328_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 375 struct rockchip_eth_dev *dev) 376 { 377 struct dw_eth_dev *priv = &dev->dw; 378 struct rk3328_grf_regs *grf; 379 int clk; 380 enum { 381 RK3328_GMAC_CLK_SEL_SHIFT = 11, 382 RK3328_GMAC_CLK_SEL_MASK = GENMASK(12, 11), 383 RK3328_GMAC_CLK_SEL_125M = 0 << 11, 384 RK3328_GMAC_CLK_SEL_25M = 3 << 11, 385 RK3328_GMAC_CLK_SEL_2_5M = 2 << 11, 386 387 RK3328_GMAC_RMII_CLK_MASK = BIT(7), 388 RK3328_GMAC_RMII_CLK_2_5M = 0, 389 RK3328_GMAC_RMII_CLK_25M = BIT(7), 390 391 RK3328_GMAC_RMII_SPEED_MASK = BIT(2), 392 RK3328_GMAC_RMII_SPEED_10 = 0, 393 RK3328_GMAC_RMII_SPEED_100 = BIT(2), 394 }; 395 396 switch (priv->phydev->speed) { 397 case 10: 398 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 399 (RK3328_GMAC_RMII_CLK_2_5M | RK3328_GMAC_RMII_SPEED_10) : 400 RK3328_GMAC_CLK_SEL_2_5M; 401 break; 402 case 100: 403 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 404 (RK3328_GMAC_RMII_CLK_25M | RK3328_GMAC_RMII_SPEED_100) : 405 RK3328_GMAC_CLK_SEL_25M; 406 break; 407 case 1000: 408 clk = RK3328_GMAC_CLK_SEL_125M; 409 break; 410 default: 411 debug("Unknown phy speed: %d\n", priv->phydev->speed); 412 return -EINVAL; 413 } 414 415 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 416 rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1], 417 RK3328_GMAC_CLK_SEL_MASK | 418 RK3328_GMAC_RMII_CLK_MASK | 419 RK3328_GMAC_RMII_SPEED_MASK, 420 clk); 421 422 return 0; 423 } 424 425 static int rk3368_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 426 struct rockchip_eth_dev *dev) 427 { 428 struct dw_eth_dev *priv = &dev->dw; 429 struct rk3368_grf *grf; 430 int clk; 431 enum { 432 RK3368_GMAC_CLK_SEL_2_5M = 2 << 4, 433 RK3368_GMAC_CLK_SEL_25M = 3 << 4, 434 RK3368_GMAC_CLK_SEL_125M = 0 << 4, 435 RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4), 436 }; 437 438 switch (priv->phydev->speed) { 439 case 10: 440 clk = RK3368_GMAC_CLK_SEL_2_5M; 441 break; 442 case 100: 443 clk = RK3368_GMAC_CLK_SEL_25M; 444 break; 445 case 1000: 446 clk = RK3368_GMAC_CLK_SEL_125M; 447 break; 448 default: 449 debug("Unknown phy speed: %d\n", priv->phydev->speed); 450 return -EINVAL; 451 } 452 453 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 454 rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk); 455 456 return 0; 457 } 458 459 static int rk3399_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 460 struct rockchip_eth_dev *dev) 461 { 462 struct dw_eth_dev *priv = &dev->dw; 463 struct rk3399_grf_regs *grf; 464 int clk; 465 466 switch (priv->phydev->speed) { 467 case 10: 468 clk = RK3399_GMAC_CLK_SEL_2_5M; 469 break; 470 case 100: 471 clk = RK3399_GMAC_CLK_SEL_25M; 472 break; 473 case 1000: 474 clk = RK3399_GMAC_CLK_SEL_125M; 475 break; 476 default: 477 debug("Unknown phy speed: %d\n", priv->phydev->speed); 478 return -EINVAL; 479 } 480 481 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 482 rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk); 483 484 return 0; 485 } 486 487 static int rv1108_set_rmii_speed(struct gmac_rockchip_platdata *pdata, 488 struct rockchip_eth_dev *dev) 489 { 490 struct dw_eth_dev *priv = &dev->dw; 491 struct rv1108_grf *grf; 492 int clk, speed; 493 enum { 494 RV1108_GMAC_SPEED_MASK = BIT(2), 495 RV1108_GMAC_SPEED_10M = 0 << 2, 496 RV1108_GMAC_SPEED_100M = 1 << 2, 497 RV1108_GMAC_CLK_SEL_MASK = BIT(7), 498 RV1108_GMAC_CLK_SEL_2_5M = 0 << 7, 499 RV1108_GMAC_CLK_SEL_25M = 1 << 7, 500 }; 501 502 switch (priv->phydev->speed) { 503 case 10: 504 clk = RV1108_GMAC_CLK_SEL_2_5M; 505 speed = RV1108_GMAC_SPEED_10M; 506 break; 507 case 100: 508 clk = RV1108_GMAC_CLK_SEL_25M; 509 speed = RV1108_GMAC_SPEED_100M; 510 break; 511 default: 512 debug("Unknown phy speed: %d\n", priv->phydev->speed); 513 return -EINVAL; 514 } 515 516 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 517 rk_clrsetreg(&grf->gmac_con0, 518 RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK, 519 clk | speed); 520 521 return 0; 522 } 523 #else 524 static int rk3506_set_rmii_speed(struct gmac_rockchip_platdata *pdata, 525 struct rockchip_eth_dev *dev) 526 { 527 struct eqos_priv *priv = &dev->eqos; 528 struct rk3506_grf_reg *grf; 529 unsigned int div; 530 531 enum { 532 RK3506_GMAC_CLK_RMII_DIV_SHIFT = 3, 533 RK3506_GMAC_CLK_RMII_DIV_MASK = BIT(3), 534 RK3506_GMAC_CLK_RMII_DIV2 = BIT(3), 535 RK3506_GMAC_CLK_RMII_DIV20 = 0, 536 }; 537 538 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 539 540 switch (priv->phy->speed) { 541 case 10: 542 div = RK3506_GMAC_CLK_RMII_DIV20; 543 break; 544 case 100: 545 div = RK3506_GMAC_CLK_RMII_DIV2; 546 break; 547 default: 548 debug("Unknown phy speed: %d\n", priv->phy->speed); 549 return -EINVAL; 550 } 551 552 if (pdata->bus_id) 553 rk_clrsetreg(&grf->soc_con11, RK3506_GMAC_CLK_RMII_DIV_MASK, div); 554 else 555 rk_clrsetreg(&grf->soc_con8, RK3506_GMAC_CLK_RMII_DIV_MASK, div); 556 557 return 0; 558 } 559 560 static int rk3528_set_rgmii_speed(struct gmac_rockchip_platdata *pdata, 561 struct rockchip_eth_dev *dev) 562 { 563 struct eqos_priv *priv = &dev->eqos; 564 struct rk3528_grf *grf; 565 unsigned int div; 566 567 enum { 568 RK3528_GMAC0_CLK_RMII_DIV_SHIFT = 3, 569 RK3528_GMAC0_CLK_RMII_DIV_MASK = GENMASK(4, 3), 570 RK3528_GMAC0_CLK_RMII_DIV2 = BIT(3), 571 RK3528_GMAC0_CLK_RMII_DIV20 = 0, 572 }; 573 574 enum { 575 RK3528_GMAC1_CLK_RGMII_DIV_SHIFT = 10, 576 RK3528_GMAC1_CLK_RGMII_DIV_MASK = GENMASK(11, 10), 577 RK3528_GMAC1_CLK_RGMII_DIV1 = 0, 578 RK3528_GMAC1_CLK_RGMII_DIV5 = GENMASK(11, 10), 579 RK3528_GMAC1_CLK_RGMII_DIV50 = BIT(11), 580 RK3528_GMAC1_CLK_RMII_DIV2 = BIT(11), 581 RK3528_GMAC1_CLK_RMII_DIV20 = 0, 582 }; 583 584 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 585 586 switch (priv->phy->speed) { 587 case 10: 588 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) 589 div = pdata->bus_id ? RK3528_GMAC1_CLK_RMII_DIV20 : 590 RK3528_GMAC0_CLK_RMII_DIV20; 591 else 592 div = RK3528_GMAC1_CLK_RGMII_DIV50; 593 break; 594 case 100: 595 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) 596 div = pdata->bus_id ? RK3528_GMAC1_CLK_RMII_DIV2 : 597 RK3528_GMAC0_CLK_RMII_DIV2; 598 else 599 div = RK3528_GMAC1_CLK_RGMII_DIV5; 600 break; 601 case 1000: 602 if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII) 603 div = RK3528_GMAC1_CLK_RGMII_DIV1; 604 else 605 return -EINVAL; 606 break; 607 default: 608 debug("Unknown phy speed: %d\n", priv->phy->speed); 609 return -EINVAL; 610 } 611 612 if (pdata->bus_id) 613 rk_clrsetreg(&grf->gmac1_con0, RK3528_GMAC1_CLK_RGMII_DIV_MASK, div); 614 else 615 rk_clrsetreg(&grf->gmac0_con, RK3528_GMAC0_CLK_RMII_DIV_MASK, div); 616 617 return 0; 618 } 619 620 static int rk3562_set_gmac_speed(struct gmac_rockchip_platdata *pdata, 621 struct rockchip_eth_dev *dev) 622 { 623 struct eqos_priv *priv = &dev->eqos; 624 struct rk3562_grf *grf; 625 unsigned int div; 626 627 enum { 628 RK3562_GMAC0_CLK_RGMII_DIV_SHIFT = 7, 629 RK3562_GMAC0_CLK_RGMII_DIV_MASK = GENMASK(8, 7), 630 RK3562_GMAC0_CLK_RGMII_DIV1 = 0, 631 RK3562_GMAC0_CLK_RGMII_DIV5 = GENMASK(8, 7), 632 RK3562_GMAC0_CLK_RGMII_DIV50 = BIT(8), 633 RK3562_GMAC0_CLK_RMII_DIV2 = BIT(7), 634 RK3562_GMAC0_CLK_RMII_DIV20 = 0, 635 }; 636 637 enum { 638 RK3562_GMAC1_SPEED_SHIFT = 0x0, 639 RK3562_GMAC1_SPEED_MASK = BIT(0), 640 RK3562_GMAC1_SPEED_10M = 0, 641 RK3562_GMAC1_SPEED_100M = BIT(0), 642 }; 643 644 enum { 645 RK3562_GMAC1_CLK_RMII_DIV_SHIFT = 13, 646 RK3562_GMAC1_CLK_RMII_DIV_MASK = BIT(13), 647 RK3562_GMAC1_CLK_RMII_DIV2 = BIT(13), 648 RK3562_GMAC1_CLK_RMII_DIV20 = 0, 649 }; 650 651 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 652 653 switch (priv->phy->speed) { 654 case 10: 655 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) { 656 if (pdata->bus_id > 0) { 657 div = RK3562_GMAC1_CLK_RMII_DIV20; 658 rk_clrsetreg(&grf->soc_con[0], 659 RK3562_GMAC1_SPEED_MASK, 660 RK3562_GMAC1_SPEED_10M); 661 } else { 662 div = RK3562_GMAC0_CLK_RMII_DIV20; 663 } 664 } else { 665 div = RK3562_GMAC0_CLK_RGMII_DIV50; 666 } 667 break; 668 case 100: 669 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) { 670 if (pdata->bus_id > 0) { 671 div = RK3562_GMAC1_CLK_RMII_DIV2; 672 rk_clrsetreg(&grf->soc_con[0], 673 RK3562_GMAC1_SPEED_MASK, 674 RK3562_GMAC1_SPEED_100M); 675 } else { 676 div = RK3562_GMAC0_CLK_RMII_DIV2; 677 } 678 } else { 679 div = RK3562_GMAC0_CLK_RGMII_DIV5; 680 } 681 break; 682 case 1000: 683 if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII) 684 div = RK3562_GMAC0_CLK_RGMII_DIV1; 685 else 686 return -EINVAL; 687 break; 688 default: 689 debug("Unknown phy speed: %d\n", priv->phy->speed); 690 return -EINVAL; 691 } 692 693 if (pdata->bus_id) 694 rk_clrsetreg(&grf->soc_con[1], RK3562_GMAC1_CLK_RMII_DIV_MASK, div); 695 else 696 rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_CLK_RGMII_DIV_MASK, div); 697 698 return 0; 699 } 700 701 static int rk3588_set_rgmii_speed(struct gmac_rockchip_platdata *pdata, 702 struct rockchip_eth_dev *dev) 703 { 704 struct eqos_priv *priv = &dev->eqos; 705 struct rk3588_php_grf *php_grf; 706 unsigned int div, div_mask; 707 708 enum { 709 RK3588_GMAC_CLK_RGMII_DIV_SHIFT = 2, 710 RK3588_GMAC_CLK_RGMII_DIV_MASK = GENMASK(3, 2), 711 RK3588_GMAC_CLK_RGMII_DIV1 = 0, 712 RK3588_GMAC_CLK_RGMII_DIV5 = GENMASK(3, 2), 713 RK3588_GMAC_CLK_RGMII_DIV50 = BIT(3), 714 RK3588_GMAC_CLK_RMII_DIV2 = BIT(2), 715 RK3588_GMAC_CLK_RMII_DIV20 = 0, 716 RK3588_GMAC1_ID_SHIFT = 5, 717 }; 718 719 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 720 721 switch (priv->phy->speed) { 722 case 10: 723 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) 724 div = RK3588_GMAC_CLK_RMII_DIV20; 725 else 726 div = RK3588_GMAC_CLK_RGMII_DIV50; 727 break; 728 case 100: 729 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) 730 div = RK3588_GMAC_CLK_RMII_DIV2; 731 else 732 div = RK3588_GMAC_CLK_RGMII_DIV5; 733 break; 734 case 1000: 735 if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII) 736 div = RK3588_GMAC_CLK_RGMII_DIV1; 737 else 738 return -EINVAL; 739 break; 740 default: 741 debug("Unknown phy speed: %d\n", priv->phy->speed); 742 return -EINVAL; 743 } 744 745 if (pdata->bus_id == 1) { 746 div <<= 5; 747 div_mask = RK3588_GMAC_CLK_RGMII_DIV_MASK << 5; 748 } 749 750 div <<= pdata->bus_id ? RK3588_GMAC1_ID_SHIFT : 0; 751 div_mask = pdata->bus_id ? (RK3588_GMAC_CLK_RGMII_DIV_MASK << 5) : 752 RK3588_GMAC_CLK_RGMII_DIV_MASK; 753 754 rk_clrsetreg(&php_grf->clk_con1, div_mask, div); 755 756 return 0; 757 } 758 759 static int rv1106_set_rmii_speed(struct gmac_rockchip_platdata *pdata, 760 struct rockchip_eth_dev *dev) 761 { 762 struct eqos_priv *priv = &dev->eqos; 763 #ifdef CONFIG_ROCKCHIP_RV1103B 764 struct rv1103b_grf *grf; 765 #else 766 struct rv1106_grf *grf; 767 #endif 768 unsigned int div; 769 770 enum { 771 RV1106_GMAC_CLK_RMII_DIV_SHIFT = 2, 772 RV1106_GMAC_CLK_RMII_DIV_MASK = GENMASK(3, 2), 773 RV1106_GMAC_CLK_RMII_DIV2 = BIT(2), 774 RV1106_GMAC_CLK_RMII_DIV20 = 0, 775 }; 776 777 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 778 779 switch (priv->phy->speed) { 780 case 10: 781 div = RV1106_GMAC_CLK_RMII_DIV20; 782 break; 783 case 100: 784 div = RV1106_GMAC_CLK_RMII_DIV2; 785 break; 786 default: 787 debug("Unknown phy speed: %d\n", priv->phy->speed); 788 return -EINVAL; 789 } 790 791 rk_clrsetreg(&grf->gmac_clk_con, RV1106_GMAC_CLK_RMII_DIV_MASK, div); 792 793 return 0; 794 } 795 796 static int rv1126_set_rgmii_speed(struct gmac_rockchip_platdata *pdata, 797 struct rockchip_eth_dev *dev) 798 { 799 struct eqos_priv *priv = &dev->eqos; 800 struct clk clk_speed; 801 int ret; 802 803 ret = clk_get_by_name(priv->phy->dev, "clk_mac_speed", 804 &clk_speed); 805 if (ret) { 806 printf("%s can't get clk_mac_speed clock (ret=%d):\n", 807 __func__, ret); 808 return ret; 809 } 810 811 switch ( priv->phy->speed) { 812 case 10: 813 ret = clk_set_rate(&clk_speed, 2500000); 814 if (ret) 815 return ret; 816 break; 817 case 100: 818 ret = clk_set_rate(&clk_speed, 25000000); 819 if (ret) 820 return ret; 821 break; 822 case 1000: 823 ret = clk_set_rate(&clk_speed, 125000000); 824 if (ret) 825 return ret; 826 break; 827 default: 828 debug("Unknown phy speed: %d\n", priv->phy->speed); 829 return -EINVAL; 830 } 831 832 return 0; 833 } 834 #endif 835 836 #ifndef CONFIG_DWC_ETH_QOS 837 static void px30_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 838 { 839 struct px30_grf *grf; 840 enum { 841 px30_GMAC_PHY_INTF_SEL_SHIFT = 4, 842 px30_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 6), 843 px30_GMAC_PHY_INTF_SEL_RMII = BIT(6), 844 }; 845 846 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 847 848 rk_clrsetreg(&grf->mac_con1, 849 px30_GMAC_PHY_INTF_SEL_MASK, 850 px30_GMAC_PHY_INTF_SEL_RMII); 851 } 852 853 static void rk1808_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 854 { 855 struct rk1808_grf *grf; 856 enum { 857 RK1808_GMAC_PHY_INTF_SEL_SHIFT = 4, 858 RK1808_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 859 RK1808_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 860 861 RK1808_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 862 RK1808_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 863 RK1808_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 864 865 RK1808_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 866 RK1808_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 867 RK1808_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 868 }; 869 enum { 870 RK1808_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 871 RK1808_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 7), 872 873 RK1808_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 874 RK1808_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 875 }; 876 877 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 878 rk_clrsetreg(&grf->mac_con1, 879 RK1808_GMAC_PHY_INTF_SEL_MASK | 880 RK1808_RXCLK_DLY_ENA_GMAC_MASK | 881 RK1808_TXCLK_DLY_ENA_GMAC_MASK, 882 RK1808_GMAC_PHY_INTF_SEL_RGMII | 883 RK1808_RXCLK_DLY_ENA_GMAC_ENABLE | 884 RK1808_TXCLK_DLY_ENA_GMAC_ENABLE); 885 886 rk_clrsetreg(&grf->mac_con0, 887 RK1808_CLK_RX_DL_CFG_GMAC_MASK | 888 RK1808_CLK_TX_DL_CFG_GMAC_MASK, 889 (pdata->rx_delay << RK1808_CLK_RX_DL_CFG_GMAC_SHIFT) | 890 (pdata->tx_delay << RK1808_CLK_TX_DL_CFG_GMAC_SHIFT)); 891 } 892 893 static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 894 { 895 struct rk322x_grf *grf; 896 enum { 897 RK3228_RMII_MODE_SHIFT = 10, 898 RK3228_RMII_MODE_MASK = BIT(10), 899 900 RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4, 901 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 902 RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 903 904 RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 905 RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 906 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 907 908 RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 909 RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 910 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 911 }; 912 enum { 913 RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 914 RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 915 916 RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 917 RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 918 }; 919 920 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 921 rk_clrsetreg(&grf->mac_con[1], 922 RK3228_RMII_MODE_MASK | 923 RK3228_GMAC_PHY_INTF_SEL_MASK | 924 RK3228_RXCLK_DLY_ENA_GMAC_MASK | 925 RK3228_TXCLK_DLY_ENA_GMAC_MASK, 926 RK3228_GMAC_PHY_INTF_SEL_RGMII | 927 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE | 928 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE); 929 930 rk_clrsetreg(&grf->mac_con[0], 931 RK3228_CLK_RX_DL_CFG_GMAC_MASK | 932 RK3228_CLK_TX_DL_CFG_GMAC_MASK, 933 pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT | 934 pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT); 935 } 936 937 static void rk3228_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 938 { 939 struct rk322x_grf *grf; 940 enum { 941 RK3228_GRF_CON_RMII_MODE_MASK = BIT(11), 942 RK3228_GRF_CON_RMII_MODE_SEL = BIT(11), 943 RK3228_RMII_MODE_MASK = BIT(10), 944 RK3228_RMII_MODE_SEL = BIT(10), 945 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 946 RK3228_GMAC_PHY_INTF_SEL_RMII = BIT(6), 947 }; 948 949 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 950 rk_clrsetreg(&grf->mac_con[1], 951 RK3228_GRF_CON_RMII_MODE_MASK | 952 RK3228_RMII_MODE_MASK | 953 RK3228_GMAC_PHY_INTF_SEL_MASK, 954 RK3228_GRF_CON_RMII_MODE_SEL | 955 RK3228_RMII_MODE_SEL | 956 RK3228_GMAC_PHY_INTF_SEL_RMII); 957 } 958 959 static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 960 { 961 struct rk3288_grf *grf; 962 963 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 964 rk_clrsetreg(&grf->soc_con1, 965 RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK, 966 RK3288_GMAC_PHY_INTF_SEL_RGMII); 967 968 rk_clrsetreg(&grf->soc_con3, 969 RK3288_RXCLK_DLY_ENA_GMAC_MASK | 970 RK3288_TXCLK_DLY_ENA_GMAC_MASK | 971 RK3288_CLK_RX_DL_CFG_GMAC_MASK | 972 RK3288_CLK_TX_DL_CFG_GMAC_MASK, 973 RK3288_RXCLK_DLY_ENA_GMAC_ENABLE | 974 RK3288_TXCLK_DLY_ENA_GMAC_ENABLE | 975 pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT | 976 pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT); 977 } 978 979 static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 980 { 981 struct rk3308_grf *grf; 982 enum { 983 RK3308_GMAC_PHY_INTF_SEL_SHIFT = 2, 984 RK3308_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 2), 985 RK3308_GMAC_PHY_INTF_SEL_RMII = BIT(4), 986 }; 987 988 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 989 990 rk_clrsetreg(&grf->mac_con0, 991 RK3308_GMAC_PHY_INTF_SEL_MASK, 992 RK3308_GMAC_PHY_INTF_SEL_RMII); 993 } 994 995 static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 996 { 997 struct rk3328_grf_regs *grf; 998 enum { 999 RK3328_RMII_MODE_SHIFT = 9, 1000 RK3328_RMII_MODE_MASK = BIT(9), 1001 1002 RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4, 1003 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1004 RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 1005 1006 RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 1007 RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 1008 RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 1009 1010 RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 1011 RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 1012 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 1013 }; 1014 enum { 1015 RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 1016 RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 1017 1018 RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1019 RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 1020 }; 1021 1022 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1023 rk_clrsetreg(&grf->mac_con[1], 1024 RK3328_RMII_MODE_MASK | 1025 RK3328_GMAC_PHY_INTF_SEL_MASK | 1026 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 1027 RK3328_TXCLK_DLY_ENA_GMAC_MASK, 1028 RK3328_GMAC_PHY_INTF_SEL_RGMII | 1029 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 1030 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE); 1031 1032 rk_clrsetreg(&grf->mac_con[0], 1033 RK3328_CLK_RX_DL_CFG_GMAC_MASK | 1034 RK3328_CLK_TX_DL_CFG_GMAC_MASK, 1035 pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT | 1036 pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT); 1037 } 1038 1039 static void rk3328_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1040 { 1041 struct rk3328_grf_regs *grf; 1042 enum { 1043 RK3328_RMII_MODE_MASK = BIT(9), 1044 RK3328_RMII_MODE = BIT(9), 1045 1046 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1047 RK3328_GMAC_PHY_INTF_SEL_RMII = BIT(6), 1048 }; 1049 1050 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1051 rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1], 1052 RK3328_RMII_MODE_MASK | 1053 RK3328_GMAC_PHY_INTF_SEL_MASK, 1054 RK3328_GMAC_PHY_INTF_SEL_RMII | 1055 RK3328_RMII_MODE); 1056 } 1057 1058 static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1059 { 1060 struct rk3368_grf *grf; 1061 enum { 1062 RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9, 1063 RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9), 1064 RK3368_RMII_MODE_MASK = BIT(6), 1065 RK3368_RMII_MODE = BIT(6), 1066 }; 1067 enum { 1068 RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15), 1069 RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 1070 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15), 1071 RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7), 1072 RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 1073 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7), 1074 RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8, 1075 RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 1076 RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0, 1077 RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 1078 }; 1079 1080 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1081 rk_clrsetreg(&grf->soc_con15, 1082 RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK, 1083 RK3368_GMAC_PHY_INTF_SEL_RGMII); 1084 1085 rk_clrsetreg(&grf->soc_con16, 1086 RK3368_RXCLK_DLY_ENA_GMAC_MASK | 1087 RK3368_TXCLK_DLY_ENA_GMAC_MASK | 1088 RK3368_CLK_RX_DL_CFG_GMAC_MASK | 1089 RK3368_CLK_TX_DL_CFG_GMAC_MASK, 1090 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE | 1091 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE | 1092 (pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT) | 1093 (pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT)); 1094 } 1095 1096 static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1097 { 1098 struct rk3399_grf_regs *grf; 1099 1100 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1101 1102 rk_clrsetreg(&grf->soc_con5, 1103 RK3399_GMAC_PHY_INTF_SEL_MASK, 1104 RK3399_GMAC_PHY_INTF_SEL_RGMII); 1105 1106 rk_clrsetreg(&grf->soc_con6, 1107 RK3399_RXCLK_DLY_ENA_GMAC_MASK | 1108 RK3399_TXCLK_DLY_ENA_GMAC_MASK | 1109 RK3399_CLK_RX_DL_CFG_GMAC_MASK | 1110 RK3399_CLK_TX_DL_CFG_GMAC_MASK, 1111 RK3399_RXCLK_DLY_ENA_GMAC_ENABLE | 1112 RK3399_TXCLK_DLY_ENA_GMAC_ENABLE | 1113 (pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT) | 1114 (pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT)); 1115 } 1116 1117 static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1118 { 1119 struct rv1108_grf *grf; 1120 1121 enum { 1122 RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1123 RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4, 1124 }; 1125 1126 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1127 rk_clrsetreg(&grf->gmac_con0, 1128 RV1108_GMAC_PHY_INTF_SEL_MASK, 1129 RV1108_GMAC_PHY_INTF_SEL_RMII); 1130 } 1131 1132 static void rk3228_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 1133 { 1134 struct rk322x_grf *grf; 1135 enum { 1136 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK = BIT(15), 1137 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY = BIT(15), 1138 }; 1139 enum { 1140 RK3228_MACPHY_CFG_CLK_50M_MASK = BIT(14), 1141 RK3228_MACPHY_CFG_CLK_50M = BIT(14), 1142 1143 RK3228_MACPHY_RMII_MODE_MASK = GENMASK(7, 6), 1144 RK3228_MACPHY_RMII_MODE = BIT(6), 1145 1146 RK3228_MACPHY_ENABLE_MASK = BIT(0), 1147 RK3228_MACPHY_DISENABLE = 0, 1148 RK3228_MACPHY_ENABLE = BIT(0), 1149 }; 1150 enum { 1151 RK3228_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0), 1152 RK3228_RK_GRF_CON2_MACPHY_ID = 0x1234, 1153 }; 1154 enum { 1155 RK3228_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0), 1156 RK3228_RK_GRF_CON3_MACPHY_ID = 0x35, 1157 }; 1158 1159 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1160 rk_clrsetreg(&grf->con_iomux, 1161 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK, 1162 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY); 1163 1164 rk_clrsetreg(&grf->macphy_con[2], 1165 RK3228_RK_GRF_CON2_MACPHY_ID_MASK, 1166 RK3228_RK_GRF_CON2_MACPHY_ID); 1167 1168 rk_clrsetreg(&grf->macphy_con[3], 1169 RK3228_RK_GRF_CON3_MACPHY_ID_MASK, 1170 RK3228_RK_GRF_CON3_MACPHY_ID); 1171 1172 /* disabled before trying to reset it &*/ 1173 rk_clrsetreg(&grf->macphy_con[0], 1174 RK3228_MACPHY_CFG_CLK_50M_MASK | 1175 RK3228_MACPHY_RMII_MODE_MASK | 1176 RK3228_MACPHY_ENABLE_MASK, 1177 RK3228_MACPHY_CFG_CLK_50M | 1178 RK3228_MACPHY_RMII_MODE | 1179 RK3228_MACPHY_DISENABLE); 1180 1181 reset_assert(&pdata->phy_reset); 1182 udelay(10); 1183 reset_deassert(&pdata->phy_reset); 1184 udelay(10); 1185 1186 rk_clrsetreg(&grf->macphy_con[0], 1187 RK3228_MACPHY_ENABLE_MASK, 1188 RK3228_MACPHY_ENABLE); 1189 udelay(30 * 1000); 1190 } 1191 1192 static void rk3328_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 1193 { 1194 struct rk3328_grf_regs *grf; 1195 enum { 1196 RK3328_GRF_CON_RMII_MODE_MASK = BIT(9), 1197 RK3328_GRF_CON_RMII_MODE = BIT(9), 1198 }; 1199 enum { 1200 RK3328_MACPHY_CFG_CLK_50M_MASK = BIT(14), 1201 RK3328_MACPHY_CFG_CLK_50M = BIT(14), 1202 1203 RK3328_MACPHY_RMII_MODE_MASK = GENMASK(7, 6), 1204 RK3328_MACPHY_RMII_MODE = BIT(6), 1205 1206 RK3328_MACPHY_ENABLE_MASK = BIT(0), 1207 RK3328_MACPHY_DISENABLE = 0, 1208 RK3328_MACPHY_ENABLE = BIT(0), 1209 }; 1210 enum { 1211 RK3328_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0), 1212 RK3328_RK_GRF_CON2_MACPHY_ID = 0x1234, 1213 }; 1214 enum { 1215 RK3328_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0), 1216 RK3328_RK_GRF_CON3_MACPHY_ID = 0x35, 1217 }; 1218 1219 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1220 rk_clrsetreg(&grf->macphy_con[1], 1221 RK3328_GRF_CON_RMII_MODE_MASK, 1222 RK3328_GRF_CON_RMII_MODE); 1223 1224 rk_clrsetreg(&grf->macphy_con[2], 1225 RK3328_RK_GRF_CON2_MACPHY_ID_MASK, 1226 RK3328_RK_GRF_CON2_MACPHY_ID); 1227 1228 rk_clrsetreg(&grf->macphy_con[3], 1229 RK3328_RK_GRF_CON3_MACPHY_ID_MASK, 1230 RK3328_RK_GRF_CON3_MACPHY_ID); 1231 1232 /* disabled before trying to reset it &*/ 1233 rk_clrsetreg(&grf->macphy_con[0], 1234 RK3328_MACPHY_CFG_CLK_50M_MASK | 1235 RK3328_MACPHY_RMII_MODE_MASK | 1236 RK3328_MACPHY_ENABLE_MASK, 1237 RK3328_MACPHY_CFG_CLK_50M | 1238 RK3328_MACPHY_RMII_MODE | 1239 RK3328_MACPHY_DISENABLE); 1240 1241 reset_assert(&pdata->phy_reset); 1242 udelay(10); 1243 reset_deassert(&pdata->phy_reset); 1244 udelay(10); 1245 1246 rk_clrsetreg(&grf->macphy_con[0], 1247 RK3328_MACPHY_ENABLE_MASK, 1248 RK3328_MACPHY_ENABLE); 1249 udelay(30 * 1000); 1250 } 1251 1252 #else 1253 static void rk3506_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1254 { 1255 unsigned int clk_mode; 1256 struct rk3506_grf_reg *grf; 1257 1258 enum { 1259 RK3506_GMAC_CLK_RMII_MODE_SHIFT = 0x1, 1260 RK3506_GMAC_CLK_RMII_MODE_MASK = BIT(1), 1261 RK3506_GMAC_CLK_RMII_MODE = BIT(1), 1262 }; 1263 1264 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1265 clk_mode = RK3506_GMAC_CLK_RMII_MODE; 1266 1267 if (pdata->bus_id == 1) 1268 rk_clrsetreg(&grf->soc_con11, RK3506_GMAC_CLK_RMII_MODE_MASK, clk_mode); 1269 else 1270 rk_clrsetreg(&grf->soc_con8, RK3506_GMAC_CLK_RMII_MODE_MASK, clk_mode); 1271 } 1272 1273 static void rk3528_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 1274 { 1275 struct rk3528_grf *grf; 1276 unsigned char bgs[1] = {0}; 1277 1278 enum { 1279 RK3528_MACPHY_ENABLE_MASK = BIT(1), 1280 RK3528_MACPHY_DISENABLE = BIT(1), 1281 RK3528_MACPHY_ENABLE = 0, 1282 RK3528_MACPHY_XMII_SEL_MASK = GENMASK(6, 5), 1283 RK3528_MACPHY_XMII_SEL = BIT(6), 1284 RK3528_MACPHY_24M_CLK_SEL_MASK = GENMASK(9, 7), 1285 RK3528_MACPHY_24M_CLK_SEL_24M = (BIT(8) | BIT(9)), 1286 RK3528_MACPHY_PHY_ID_MASK = GENMASK(14, 10), 1287 RK3528_MACPHY_PHY_ID = BIT(11), 1288 }; 1289 1290 enum { 1291 RK3528_MACPHY_BGS_MASK = GENMASK(3, 0), 1292 }; 1293 1294 #if defined(CONFIG_ROCKCHIP_EFUSE) || defined(CONFIG_ROCKCHIP_OTP) 1295 struct udevice *dev; 1296 u32 regs[2] = {0}; 1297 ofnode node; 1298 int ret = 0; 1299 1300 /* retrieve the device */ 1301 if (IS_ENABLED(CONFIG_ROCKCHIP_EFUSE)) 1302 ret = uclass_get_device_by_driver(UCLASS_MISC, 1303 DM_GET_DRIVER(rockchip_efuse), 1304 &dev); 1305 else 1306 ret = uclass_get_device_by_driver(UCLASS_MISC, 1307 DM_GET_DRIVER(rockchip_otp), 1308 &dev); 1309 if (!ret) { 1310 node = dev_read_subnode(dev, "macphy-bgs"); 1311 if (ofnode_valid(node)) { 1312 if (!ofnode_read_u32_array(node, "reg", regs, 2)) { 1313 /* read the bgs from the efuses */ 1314 ret = misc_read(dev, regs[0], &bgs, 1); 1315 if (ret) { 1316 printf("read bgs from efuse/otp failed, ret=%d\n", 1317 ret); 1318 bgs[0] = 0; 1319 } 1320 } 1321 } 1322 } 1323 #endif 1324 1325 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1326 1327 reset_assert(&pdata->phy_reset); 1328 udelay(20); 1329 rk_clrsetreg(&grf->macphy_con0, 1330 RK3528_MACPHY_ENABLE_MASK | 1331 RK3528_MACPHY_XMII_SEL_MASK | 1332 RK3528_MACPHY_24M_CLK_SEL_MASK | 1333 RK3528_MACPHY_PHY_ID_MASK, 1334 RK3528_MACPHY_ENABLE | 1335 RK3528_MACPHY_XMII_SEL | 1336 RK3528_MACPHY_24M_CLK_SEL_24M | 1337 RK3528_MACPHY_PHY_ID); 1338 1339 rk_clrsetreg(&grf->macphy_con1, 1340 RK3528_MACPHY_BGS_MASK, 1341 bgs[0]); 1342 udelay(20); 1343 reset_deassert(&pdata->phy_reset); 1344 udelay(30 * 1000); 1345 } 1346 1347 static void rk3528_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1348 { 1349 unsigned int clk_mode; 1350 struct rk3528_grf *grf; 1351 1352 enum { 1353 RK3528_GMAC0_CLK_RMII_MODE_SHIFT = 0x1, 1354 RK3528_GMAC0_CLK_RMII_MODE_MASK = BIT(1), 1355 RK3528_GMAC0_CLK_RMII_MODE = 0x1, 1356 }; 1357 1358 enum { 1359 RK3528_GMAC1_CLK_RMII_MODE_SHIFT = 0x8, 1360 RK3528_GMAC1_CLK_RMII_MODE_MASK = BIT(8), 1361 RK3528_GMAC1_CLK_RMII_MODE = 0x1, 1362 }; 1363 1364 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1365 1366 if (pdata->bus_id == 1) { 1367 clk_mode = RK3528_GMAC1_CLK_RMII_MODE << RK3528_GMAC1_CLK_RMII_MODE_SHIFT; 1368 rk_clrsetreg(&grf->gmac1_con1, RK3528_GMAC1_CLK_RMII_MODE_MASK, clk_mode); 1369 } else { 1370 clk_mode = RK3528_GMAC0_CLK_RMII_MODE << RK3528_GMAC0_CLK_RMII_MODE_SHIFT; 1371 rk_clrsetreg(&grf->gmac0_con, RK3528_GMAC0_CLK_RMII_MODE_MASK, clk_mode); 1372 } 1373 } 1374 1375 static void rk3528_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1376 { 1377 unsigned int rx_enable; 1378 unsigned int rx_delay; 1379 struct rk3528_grf *grf; 1380 1381 enum { 1382 RK3528_GMAC1_RGMII_MODE_SHIFT = 0x8, 1383 RK3528_GMAC1_RGMII_MODE_MASK = BIT(8), 1384 RK3528_GMAC1_RGMII_MODE = 0x0, 1385 1386 RK3528_GMAC1_TXCLK_DLY_ENA_MASK = BIT(14), 1387 RK3528_GMAC1_TXCLK_DLY_ENA_DISABLE = 0, 1388 RK3528_GMAC1_TXCLK_DLY_ENA_ENABLE = BIT(14), 1389 1390 RK3528_GMAC1_RXCLK_DLY_ENA_MASK = BIT(15), 1391 RK3528_GMAC1_RXCLK_DLY_ENA_DISABLE = 0, 1392 RK3528_GMAC1_RXCLK_DLY_ENA_ENABLE = BIT(15), 1393 }; 1394 1395 enum { 1396 RK3528_GMAC1_RX_DL_CFG_SHIFT = 0x8, 1397 RK3528_GMAC1_RX_DL_CFG_MASK = GENMASK(15, 8), 1398 1399 RK3528_GMAC1_TX_DL_CFG_SHIFT = 0x0, 1400 RK3528_GMAC1_TX_DL_CFG_MASK = GENMASK(7, 0), 1401 }; 1402 1403 if (!pdata->bus_id) 1404 return; 1405 1406 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1407 1408 if (pdata->rx_delay < 0) { 1409 rx_enable = RK3528_GMAC1_RXCLK_DLY_ENA_DISABLE; 1410 rx_delay = 0; 1411 } else { 1412 rx_enable = RK3528_GMAC1_RXCLK_DLY_ENA_ENABLE; 1413 rx_delay = pdata->rx_delay << RK3528_GMAC1_RX_DL_CFG_SHIFT; 1414 } 1415 1416 rk_clrsetreg(&grf->gmac1_con0, 1417 RK3528_GMAC1_TXCLK_DLY_ENA_MASK | 1418 RK3528_GMAC1_RXCLK_DLY_ENA_MASK | 1419 RK3528_GMAC1_RGMII_MODE_MASK, 1420 rx_enable | RK3528_GMAC1_TXCLK_DLY_ENA_ENABLE | 1421 (RK3528_GMAC1_RGMII_MODE << RK3528_GMAC1_RGMII_MODE_SHIFT)); 1422 1423 rk_clrsetreg(&grf->gmac1_con1, 1424 RK3528_GMAC1_RX_DL_CFG_MASK | 1425 RK3528_GMAC1_TX_DL_CFG_MASK, 1426 (pdata->tx_delay << RK3528_GMAC1_TX_DL_CFG_SHIFT) | 1427 rx_delay); 1428 } 1429 1430 static void rk3562_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1431 { 1432 struct rk3562_grf *grf; 1433 unsigned int mode; 1434 1435 enum { 1436 RK3562_GMAC0_RMII_MODE_SHIFT = 0x5, 1437 RK3562_GMAC0_RMII_MODE_MASK = BIT(5), 1438 RK3562_GMAC0_RMII_MODE = 0x1, 1439 }; 1440 1441 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1442 1443 if (!pdata->bus_id) { 1444 mode = RK3562_GMAC0_RMII_MODE << RK3562_GMAC0_RMII_MODE_SHIFT; 1445 rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_RMII_MODE_MASK, mode); 1446 } 1447 } 1448 1449 static void rk3562_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1450 { 1451 struct rk3562_grf *grf; 1452 struct rk3562_ioc *ioc; 1453 unsigned int rx_enable; 1454 unsigned int rx_delay; 1455 1456 enum { 1457 RK3562_GMAC0_RGMII_MODE_SHIFT = 0x5, 1458 RK3562_GMAC0_RGMII_MODE_MASK = BIT(5), 1459 RK3562_GMAC0_RGMII_MODE = 0x0, 1460 1461 RK3562_GMAC0_TXCLK_DLY_ENA_MASK = BIT(0), 1462 RK3562_GMAC0_TXCLK_DLY_ENA_DISABLE = 0, 1463 RK3562_GMAC0_TXCLK_DLY_ENA_ENABLE = BIT(0), 1464 1465 RK3562_GMAC0_RXCLK_DLY_ENA_MASK = BIT(1), 1466 RK3562_GMAC0_RXCLK_DLY_ENA_DISABLE = 0, 1467 RK3562_GMAC0_RXCLK_DLY_ENA_ENABLE = BIT(1), 1468 }; 1469 1470 enum { 1471 RK3562_GMAC0_RX_DL_CFG_SHIFT = 0x8, 1472 RK3562_GMAC0_RX_DL_CFG_MASK = GENMASK(15, 8), 1473 1474 RK3562_GMAC0_TX_DL_CFG_SHIFT = 0x0, 1475 RK3562_GMAC0_TX_DL_CFG_MASK = GENMASK(7, 0), 1476 }; 1477 1478 if (pdata->bus_id) 1479 return; 1480 1481 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1482 ioc = syscon_get_first_range(ROCKCHIP_SYSCON_IOC); 1483 1484 rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_RGMII_MODE_MASK, 1485 RK3562_GMAC0_RGMII_MODE << RK3562_GMAC0_RGMII_MODE_SHIFT); 1486 1487 if (pdata->rx_delay < 0) { 1488 rx_enable = RK3562_GMAC0_RXCLK_DLY_ENA_DISABLE; 1489 rx_delay = 0; 1490 } else { 1491 rx_enable = RK3562_GMAC0_RXCLK_DLY_ENA_ENABLE; 1492 rx_delay = pdata->rx_delay << RK3562_GMAC0_RX_DL_CFG_SHIFT; 1493 } 1494 1495 rk_clrsetreg(&ioc->mac0_io_con1, 1496 RK3562_GMAC0_TXCLK_DLY_ENA_MASK | 1497 RK3562_GMAC0_RXCLK_DLY_ENA_MASK, 1498 rx_enable | RK3562_GMAC0_TXCLK_DLY_ENA_ENABLE); 1499 1500 rk_clrsetreg(&ioc->mac0_io_con0, 1501 RK3562_GMAC0_RX_DL_CFG_MASK | 1502 RK3562_GMAC0_TX_DL_CFG_MASK, 1503 (pdata->tx_delay << RK3562_GMAC0_TX_DL_CFG_SHIFT) | 1504 rx_delay); 1505 1506 rk_clrsetreg(&ioc->mac1_io_con1, 1507 RK3562_GMAC0_TXCLK_DLY_ENA_MASK | 1508 RK3562_GMAC0_RXCLK_DLY_ENA_MASK, 1509 rx_enable | RK3562_GMAC0_TXCLK_DLY_ENA_ENABLE); 1510 1511 rk_clrsetreg(&ioc->mac1_io_con0, 1512 RK3562_GMAC0_RX_DL_CFG_MASK | 1513 RK3562_GMAC0_TX_DL_CFG_MASK, 1514 (pdata->tx_delay << RK3562_GMAC0_TX_DL_CFG_SHIFT) | 1515 rx_delay); 1516 } 1517 1518 static void rk3568_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1519 { 1520 struct rk3568_grf *grf; 1521 void *con1; 1522 1523 enum { 1524 RK3568_GMAC_PHY_INTF_SEL_SHIFT = 4, 1525 RK3568_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1526 RK3568_GMAC_PHY_INTF_SEL_RMII = BIT(6), 1527 }; 1528 1529 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1530 1531 if (pdata->bus_id == 1) 1532 con1 = &grf->mac1_con1; 1533 else 1534 con1 = &grf->mac0_con1; 1535 1536 rk_clrsetreg(con1, 1537 RK3568_GMAC_PHY_INTF_SEL_MASK, 1538 RK3568_GMAC_PHY_INTF_SEL_RMII); 1539 } 1540 1541 static void rk3568_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1542 { 1543 struct rk3568_grf *grf; 1544 void *con0, *con1; 1545 1546 enum { 1547 RK3568_GMAC_PHY_INTF_SEL_SHIFT = 4, 1548 RK3568_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1549 RK3568_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 1550 1551 RK3568_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 1552 RK3568_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 1553 RK3568_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 1554 1555 RK3568_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 1556 RK3568_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 1557 RK3568_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 1558 }; 1559 1560 enum { 1561 RK3568_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1562 RK3568_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 8), 1563 1564 RK3568_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1565 RK3568_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 1566 }; 1567 1568 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1569 1570 if (pdata->bus_id == 1) { 1571 con0 = &grf->mac1_con0; 1572 con1 = &grf->mac1_con1; 1573 } else { 1574 con0 = &grf->mac0_con0; 1575 con1 = &grf->mac0_con1; 1576 } 1577 1578 rk_clrsetreg(con0, 1579 RK3568_CLK_RX_DL_CFG_GMAC_MASK | 1580 RK3568_CLK_TX_DL_CFG_GMAC_MASK, 1581 (pdata->rx_delay << RK3568_CLK_RX_DL_CFG_GMAC_SHIFT) | 1582 (pdata->tx_delay << RK3568_CLK_TX_DL_CFG_GMAC_SHIFT)); 1583 1584 rk_clrsetreg(con1, 1585 RK3568_TXCLK_DLY_ENA_GMAC_MASK | 1586 RK3568_RXCLK_DLY_ENA_GMAC_MASK | 1587 RK3568_GMAC_PHY_INTF_SEL_MASK, 1588 RK3568_TXCLK_DLY_ENA_GMAC_ENABLE | 1589 RK3568_RXCLK_DLY_ENA_GMAC_ENABLE | 1590 RK3568_GMAC_PHY_INTF_SEL_RGMII); 1591 } 1592 1593 static void rk3588_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1594 { 1595 unsigned int intf_sel, intf_sel_mask; 1596 unsigned int clk_mode, clk_mode_mask; 1597 struct rk3588_php_grf *php_grf; 1598 1599 enum { 1600 RK3588_GMAC_PHY_INTF_SEL_SHIFT = 3, 1601 RK3588_GMAC_PHY_INTF_SEL_MASK = GENMASK(5, 3), 1602 RK3588_GMAC_PHY_INTF_SEL_RMII = BIT(5), 1603 }; 1604 1605 enum { 1606 RK3588_GMAC_CLK_RMII_MODE_SHIFT = 0x0, 1607 RK3588_GMAC_CLK_RMII_MODE_MASK = BIT(0), 1608 RK3588_GMAC_CLK_RMII_MODE = 0x1, 1609 }; 1610 1611 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 1612 1613 if (pdata->bus_id == 1) { 1614 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RMII << 6; 1615 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK << 6; 1616 clk_mode = RK3588_GMAC_CLK_RMII_MODE << 5; 1617 clk_mode_mask = RK3588_GMAC_CLK_RMII_MODE_MASK << 5; 1618 } else { 1619 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RMII; 1620 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK; 1621 clk_mode = RK3588_GMAC_CLK_RMII_MODE; 1622 clk_mode_mask = RK3588_GMAC_CLK_RMII_MODE_MASK; 1623 } 1624 1625 rk_clrsetreg(&php_grf->gmac_con0, intf_sel_mask, intf_sel); 1626 rk_clrsetreg(&php_grf->clk_con1, clk_mode_mask, clk_mode); 1627 } 1628 1629 static void rk3588_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1630 { 1631 unsigned int rx_enable, rx_enable_mask, tx_enable, tx_enable_mask; 1632 unsigned int intf_sel, intf_sel_mask; 1633 unsigned int clk_mode, clk_mode_mask; 1634 unsigned int rx_delay; 1635 struct rk3588_php_grf *php_grf; 1636 struct rk3588_sys_grf *grf; 1637 void *offset_con; 1638 1639 enum { 1640 RK3588_GMAC_PHY_INTF_SEL_SHIFT = 3, 1641 RK3588_GMAC_PHY_INTF_SEL_MASK = GENMASK(5, 3), 1642 RK3588_GMAC_PHY_INTF_SEL_RGMII = BIT(3), 1643 1644 RK3588_RXCLK_DLY_ENA_GMAC_MASK = BIT(3), 1645 RK3588_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 1646 RK3588_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(3), 1647 1648 RK3588_TXCLK_DLY_ENA_GMAC_MASK = BIT(2), 1649 RK3588_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 1650 RK3588_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(2), 1651 }; 1652 1653 enum { 1654 RK3588_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1655 RK3588_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 8), 1656 1657 RK3588_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1658 RK3588_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 1659 }; 1660 1661 enum { 1662 RK3588_GMAC_CLK_RGMII_MODE_SHIFT = 0x0, 1663 RK3588_GMAC_CLK_RGMII_MODE_MASK = BIT(0), 1664 RK3588_GMAC_CLK_RGMII_MODE = 0x0, 1665 }; 1666 1667 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1668 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 1669 1670 if (pdata->rx_delay < 0) { 1671 rx_enable = RK3588_RXCLK_DLY_ENA_GMAC_DISABLE; 1672 rx_delay = 0; 1673 } else { 1674 rx_enable = RK3588_RXCLK_DLY_ENA_GMAC_ENABLE; 1675 rx_delay = pdata->rx_delay << RK3588_CLK_RX_DL_CFG_GMAC_SHIFT; 1676 } 1677 1678 if (pdata->bus_id == 1) { 1679 offset_con = &grf->soc_con9; 1680 rx_enable = rx_delay << 2; 1681 rx_enable_mask = RK3588_RXCLK_DLY_ENA_GMAC_MASK << 2; 1682 tx_enable = RK3588_TXCLK_DLY_ENA_GMAC_ENABLE << 2; 1683 tx_enable_mask = RK3588_TXCLK_DLY_ENA_GMAC_MASK << 2; 1684 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RGMII << 6; 1685 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK << 6; 1686 clk_mode = RK3588_GMAC_CLK_RGMII_MODE << 5; 1687 clk_mode_mask = RK3588_GMAC_CLK_RGMII_MODE_MASK << 5; 1688 } else { 1689 offset_con = &grf->soc_con8; 1690 rx_enable_mask = RK3588_RXCLK_DLY_ENA_GMAC_MASK; 1691 tx_enable = RK3588_TXCLK_DLY_ENA_GMAC_ENABLE; 1692 tx_enable_mask = RK3588_TXCLK_DLY_ENA_GMAC_MASK; 1693 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RGMII; 1694 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK; 1695 clk_mode = RK3588_GMAC_CLK_RGMII_MODE; 1696 clk_mode_mask = RK3588_GMAC_CLK_RGMII_MODE_MASK; 1697 } 1698 1699 rk_clrsetreg(offset_con, 1700 RK3588_CLK_TX_DL_CFG_GMAC_MASK | 1701 RK3588_CLK_RX_DL_CFG_GMAC_MASK, 1702 (pdata->tx_delay << RK3588_CLK_TX_DL_CFG_GMAC_SHIFT) | 1703 rx_delay); 1704 1705 rk_clrsetreg(&grf->soc_con7, tx_enable_mask | rx_enable_mask, 1706 tx_enable | rx_enable); 1707 1708 rk_clrsetreg(&php_grf->gmac_con0, intf_sel_mask, intf_sel); 1709 rk_clrsetreg(&php_grf->clk_con1, clk_mode_mask, clk_mode); 1710 } 1711 1712 static void rv1103b_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1713 { 1714 struct rv1103b_grf *grf; 1715 enum { 1716 RV1103B_SYSGRF_GMAC_CLK_RMII_50M_MASK = BIT(2), 1717 RV1103B_SYSGRF_GMAC_CLK_RMII_50M = BIT(2), 1718 }; 1719 1720 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1721 rk_clrsetreg(&grf->gmac_clk_con, 1722 RV1103B_SYSGRF_GMAC_CLK_RMII_50M_MASK, 1723 RV1103B_SYSGRF_GMAC_CLK_RMII_50M); 1724 }; 1725 1726 static void rv1106_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 1727 { 1728 #ifdef CONFIG_ROCKCHIP_RV1103B 1729 struct rv1103b_grf *grf; 1730 #else 1731 struct rv1106_grf *grf; 1732 #endif 1733 unsigned char bgs[1] = {0}; 1734 1735 enum { 1736 RV1106_VOGRF_GMAC_CLK_RMII_MODE_MASK = BIT(0), 1737 RV1106_VOGRF_GMAC_CLK_RMII_MODE = BIT(0), 1738 }; 1739 1740 enum { 1741 RV1106_MACPHY_ENABLE_MASK = BIT(1), 1742 RV1106_MACPHY_DISENABLE = BIT(1), 1743 RV1106_MACPHY_ENABLE = 0, 1744 RV1106_MACPHY_XMII_SEL_MASK = GENMASK(6, 5), 1745 RV1106_MACPHY_XMII_SEL = BIT(6), 1746 RV1106_MACPHY_24M_CLK_SEL_MASK = GENMASK(9, 7), 1747 RV1106_MACPHY_24M_CLK_SEL_24M = (BIT(8) | BIT(9)), 1748 RV1106_MACPHY_PHY_ID_MASK = GENMASK(14, 10), 1749 RV1106_MACPHY_PHY_ID = BIT(11), 1750 }; 1751 1752 enum { 1753 RV1106_MACPHY_BGS_MASK = GENMASK(3, 0), 1754 RV1106_MACPHY_BGS = BIT(2), 1755 }; 1756 1757 #if defined(CONFIG_ROCKCHIP_EFUSE) || defined(CONFIG_ROCKCHIP_OTP) 1758 struct udevice *dev; 1759 u32 regs[2] = {0}; 1760 ofnode node; 1761 int ret = 0; 1762 1763 /* retrieve the device */ 1764 if (IS_ENABLED(CONFIG_ROCKCHIP_EFUSE)) 1765 ret = uclass_get_device_by_driver(UCLASS_MISC, 1766 DM_GET_DRIVER(rockchip_efuse), 1767 &dev); 1768 else 1769 ret = uclass_get_device_by_driver(UCLASS_MISC, 1770 DM_GET_DRIVER(rockchip_otp), 1771 &dev); 1772 if (!ret) { 1773 node = dev_read_subnode(dev, "macphy-bgs"); 1774 if (ofnode_valid(node)) { 1775 if (!ofnode_read_u32_array(node, "reg", regs, 2)) { 1776 /* read the bgs from the efuses */ 1777 ret = misc_read(dev, regs[0], &bgs, 1); 1778 if (ret) { 1779 printf("read bgs from efuse/otp failed, ret=%d\n", 1780 ret); 1781 bgs[0] = 0; 1782 } 1783 } 1784 } 1785 } 1786 #endif 1787 1788 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1789 1790 reset_assert(&pdata->phy_reset); 1791 udelay(20); 1792 rk_clrsetreg(&grf->macphy_con0, 1793 RV1106_MACPHY_ENABLE_MASK | 1794 RV1106_MACPHY_XMII_SEL_MASK | 1795 RV1106_MACPHY_24M_CLK_SEL_MASK | 1796 RV1106_MACPHY_PHY_ID_MASK, 1797 RV1106_MACPHY_ENABLE | 1798 RV1106_MACPHY_XMII_SEL | 1799 RV1106_MACPHY_24M_CLK_SEL_24M | 1800 RV1106_MACPHY_PHY_ID); 1801 1802 rk_clrsetreg(&grf->macphy_con1, 1803 RV1106_MACPHY_BGS_MASK, 1804 bgs[0]); 1805 udelay(20); 1806 reset_deassert(&pdata->phy_reset); 1807 udelay(30 * 1000); 1808 } 1809 1810 static void rv1106_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1811 { 1812 struct rv1106_grf *grf; 1813 enum { 1814 RV1106_VOGRF_GMAC_CLK_RMII_MODE_MASK = BIT(0), 1815 RV1106_VOGRF_GMAC_CLK_RMII_MODE = BIT(0), 1816 }; 1817 1818 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1819 rk_clrsetreg(&grf->gmac_clk_con, 1820 RV1106_VOGRF_GMAC_CLK_RMII_MODE_MASK, 1821 RV1106_VOGRF_GMAC_CLK_RMII_MODE); 1822 }; 1823 1824 static void rv1126_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1825 { 1826 struct rv1126_grf *grf; 1827 1828 enum { 1829 RV1126_GMAC_PHY_INTF_SEL_SHIFT = 4, 1830 RV1126_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1831 RV1126_GMAC_PHY_INTF_SEL_RMII = BIT(6), 1832 }; 1833 1834 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1835 1836 rk_clrsetreg(&grf->mac_con0, 1837 RV1126_GMAC_PHY_INTF_SEL_MASK, 1838 RV1126_GMAC_PHY_INTF_SEL_RMII); 1839 } 1840 1841 static void rv1126_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1842 { 1843 struct rv1126_grf *grf; 1844 1845 enum { 1846 RV1126_GMAC_PHY_INTF_SEL_SHIFT = 4, 1847 RV1126_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1848 RV1126_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 1849 1850 RV1126_RXCLK_M1_DLY_ENA_GMAC_MASK = BIT(3), 1851 RV1126_RXCLK_M1_DLY_ENA_GMAC_DISABLE = 0, 1852 RV1126_RXCLK_M1_DLY_ENA_GMAC_ENABLE = BIT(3), 1853 1854 RV1126_TXCLK_M1_DLY_ENA_GMAC_MASK = BIT(2), 1855 RV1126_TXCLK_M1_DLY_ENA_GMAC_DISABLE = 0, 1856 RV1126_TXCLK_M1_DLY_ENA_GMAC_ENABLE = BIT(2), 1857 1858 RV1126_RXCLK_M0_DLY_ENA_GMAC_MASK = BIT(1), 1859 RV1126_RXCLK_M0_DLY_ENA_GMAC_DISABLE = 0, 1860 RV1126_RXCLK_M0_DLY_ENA_GMAC_ENABLE = BIT(1), 1861 1862 RV1126_TXCLK_M0_DLY_ENA_GMAC_MASK = BIT(0), 1863 RV1126_TXCLK_M0_DLY_ENA_GMAC_DISABLE = 0, 1864 RV1126_TXCLK_M0_DLY_ENA_GMAC_ENABLE = BIT(0), 1865 }; 1866 enum { 1867 RV1126_M0_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1868 RV1126_M0_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 1869 1870 RV1126_M0_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1871 RV1126_M0_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 1872 }; 1873 enum { 1874 RV1126_M1_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1875 RV1126_M1_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 1876 1877 RV1126_M1_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1878 RV1126_M1_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 1879 }; 1880 1881 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1882 1883 rk_clrsetreg(&grf->mac_con0, 1884 RV1126_TXCLK_M0_DLY_ENA_GMAC_MASK | 1885 RV1126_RXCLK_M0_DLY_ENA_GMAC_MASK | 1886 RV1126_TXCLK_M1_DLY_ENA_GMAC_MASK | 1887 RV1126_RXCLK_M1_DLY_ENA_GMAC_MASK | 1888 RV1126_GMAC_PHY_INTF_SEL_MASK, 1889 RV1126_TXCLK_M0_DLY_ENA_GMAC_ENABLE | 1890 RV1126_RXCLK_M0_DLY_ENA_GMAC_ENABLE | 1891 RV1126_TXCLK_M1_DLY_ENA_GMAC_ENABLE | 1892 RV1126_RXCLK_M1_DLY_ENA_GMAC_ENABLE | 1893 RV1126_GMAC_PHY_INTF_SEL_RGMII); 1894 1895 rk_clrsetreg(&grf->mac_con1, 1896 RV1126_M0_CLK_RX_DL_CFG_GMAC_MASK | 1897 RV1126_M0_CLK_TX_DL_CFG_GMAC_MASK, 1898 (pdata->rx_delay << RV1126_M0_CLK_RX_DL_CFG_GMAC_SHIFT) | 1899 (pdata->tx_delay << RV1126_M0_CLK_TX_DL_CFG_GMAC_SHIFT)); 1900 1901 rk_clrsetreg(&grf->mac_con2, 1902 RV1126_M1_CLK_RX_DL_CFG_GMAC_MASK | 1903 RV1126_M1_CLK_TX_DL_CFG_GMAC_MASK, 1904 (pdata->rx_delay << RV1126_M1_CLK_RX_DL_CFG_GMAC_SHIFT) | 1905 (pdata->tx_delay << RV1126_M1_CLK_TX_DL_CFG_GMAC_SHIFT)); 1906 } 1907 #endif 1908 1909 #ifdef CONFIG_DWC_ETH_QOS 1910 static void rk3506_set_clock_selection(struct gmac_rockchip_platdata *pdata) 1911 { 1912 struct rk3506_grf_reg *grf; 1913 unsigned int val; 1914 1915 enum { 1916 RK3506_GMAC_CLK_SELET_SHIFT = 5, 1917 RK3506_GMAC_CLK_SELET_MASK = BIT(5), 1918 RK3506_GMAC_CLK_SELET_CRU = 0, 1919 RK3506_GMAC_CLK_SELET_IO = BIT(5), 1920 }; 1921 1922 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1923 1924 val = pdata->clock_input ? RK3506_GMAC_CLK_SELET_IO : 1925 RK3506_GMAC_CLK_SELET_CRU; 1926 1927 if (pdata->bus_id) 1928 rk_clrsetreg(&grf->soc_con11, RK3506_GMAC_CLK_SELET_MASK, val); 1929 else 1930 rk_clrsetreg(&grf->soc_con8, RK3506_GMAC_CLK_SELET_MASK, val); 1931 } 1932 1933 static void rk3528_set_clock_selection(struct gmac_rockchip_platdata *pdata) 1934 { 1935 struct rk3528_grf *grf; 1936 unsigned int val; 1937 1938 enum { 1939 RK3528_GMAC1_CLK_SELET_SHIFT = 0x12, 1940 RK3528_GMAC1_CLK_SELET_MASK = BIT(12), 1941 RK3528_GMAC1_CLK_SELET_CRU = 0, 1942 RK3528_GMAC1_CLK_SELET_IO = BIT(12), 1943 }; 1944 1945 if (!pdata->bus_id) 1946 return; 1947 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1948 1949 val = pdata->clock_input ? RK3528_GMAC1_CLK_SELET_IO : 1950 RK3528_GMAC1_CLK_SELET_CRU; 1951 rk_clrsetreg(&grf->gmac1_con0, RK3528_GMAC1_CLK_SELET_MASK, val); 1952 } 1953 1954 static void rk3562_set_clock_selection(struct gmac_rockchip_platdata *pdata) 1955 { 1956 struct rk3562_grf *grf; 1957 struct rk3562_ioc *ioc; 1958 unsigned int val; 1959 1960 enum { 1961 RK3562_GMAC0_CLK_SELET_SHIFT = 0x9, 1962 RK3562_GMAC0_CLK_SELET_MASK = BIT(9), 1963 RK3562_GMAC0_CLK_SELET_CRU = 0, 1964 RK3562_GMAC0_CLK_SELET_IO = BIT(9), 1965 }; 1966 1967 enum { 1968 RK3562_GMAC1_CLK_SELET_SHIFT = 15, 1969 RK3562_GMAC1_CLK_SELET_MASK = BIT(15), 1970 RK3562_GMAC1_CLK_SELET_CRU = 0, 1971 RK3562_GMAC1_CLK_SELET_IO = BIT(15), 1972 }; 1973 1974 enum { 1975 RK3562_GMAC0_IO_EXTCLK_SELET_SHIFT = 0x2, 1976 RK3562_GMAC0_IO_EXTCLK_SELET_MASK = BIT(2), 1977 RK3562_GMAC0_IO_EXTCLK_SELET_CRU = 0, 1978 RK3562_GMAC0_IO_EXTCLK_SELET_IO = BIT(2), 1979 }; 1980 1981 enum { 1982 RK3562_GMAC1_IO_EXTCLK_SELET_SHIFT = 0x3, 1983 RK3562_GMAC1_IO_EXTCLK_SELET_MASK = BIT(3), 1984 RK3562_GMAC1_IO_EXTCLK_SELET_CRU = 0, 1985 RK3562_GMAC1_IO_EXTCLK_SELET_IO = BIT(3), 1986 }; 1987 1988 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1989 ioc = syscon_get_first_range(ROCKCHIP_SYSCON_IOC); 1990 1991 if (!pdata->bus_id) { 1992 val = pdata->clock_input ? RK3562_GMAC0_CLK_SELET_IO : 1993 RK3562_GMAC0_CLK_SELET_CRU; 1994 rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_CLK_SELET_MASK, val); 1995 val = pdata->clock_input ? RK3562_GMAC0_IO_EXTCLK_SELET_IO : 1996 RK3562_GMAC0_IO_EXTCLK_SELET_CRU; 1997 rk_clrsetreg(&ioc->mac1_io_con1, 1998 RK3562_GMAC0_IO_EXTCLK_SELET_MASK, val); 1999 rk_clrsetreg(&ioc->mac0_io_con1, 2000 RK3562_GMAC0_IO_EXTCLK_SELET_MASK, val); 2001 2002 } else { 2003 val = pdata->clock_input ? RK3562_GMAC1_CLK_SELET_IO : 2004 RK3562_GMAC1_CLK_SELET_CRU; 2005 rk_clrsetreg(&grf->soc_con[1], RK3562_GMAC1_CLK_SELET_MASK, val); 2006 val = pdata->clock_input ? RK3562_GMAC1_IO_EXTCLK_SELET_IO : 2007 RK3562_GMAC1_IO_EXTCLK_SELET_CRU; 2008 rk_clrsetreg(&ioc->mac1_io_con1, 2009 RK3562_GMAC1_IO_EXTCLK_SELET_MASK, val); 2010 } 2011 } 2012 2013 static void rk3588_set_clock_selection(struct gmac_rockchip_platdata *pdata) 2014 { 2015 struct rk3588_php_grf *php_grf; 2016 unsigned int val, mask; 2017 2018 enum { 2019 RK3588_GMAC_CLK_SELET_SHIFT = 0x4, 2020 RK3588_GMAC_CLK_SELET_MASK = BIT(4), 2021 RK3588_GMAC_CLK_SELET_CRU = BIT(4), 2022 RK3588_GMAC_CLK_SELET_IO = 0, 2023 }; 2024 2025 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 2026 val = pdata->clock_input ? RK3588_GMAC_CLK_SELET_IO : 2027 RK3588_GMAC_CLK_SELET_CRU; 2028 mask = RK3588_GMAC_CLK_SELET_MASK; 2029 2030 if (pdata->bus_id == 1) { 2031 val <<= 5; 2032 mask <<= 5; 2033 } 2034 2035 rk_clrsetreg(&php_grf->clk_con1, mask, val); 2036 } 2037 #endif 2038 2039 static int gmac_rockchip_probe(struct udevice *dev) 2040 { 2041 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 2042 struct rk_gmac_ops *ops = 2043 (struct rk_gmac_ops *)dev_get_driver_data(dev); 2044 #ifdef CONFIG_DWC_ETH_QOS 2045 struct eqos_config *config; 2046 #else 2047 struct dw_eth_pdata *dw_pdata; 2048 #endif 2049 struct eth_pdata *eth_pdata; 2050 struct clk clk; 2051 ulong rate; 2052 int ret; 2053 2054 #ifdef CONFIG_DWC_ETH_QOS 2055 eth_pdata = &pdata->eth_pdata; 2056 config = (struct eqos_config *)&ops->config; 2057 memcpy(config, &eqos_rockchip_config, sizeof(struct eqos_config)); 2058 eth_pdata->phy_interface = config->ops->eqos_get_interface(dev); 2059 #else 2060 dw_pdata = &pdata->dw_eth_pdata; 2061 eth_pdata = &dw_pdata->eth_pdata; 2062 #endif 2063 pdata->bus_id = dev->seq; 2064 2065 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 2066 ret = clk_set_defaults(dev); 2067 if (ret) 2068 debug("%s clk_set_defaults failed %d\n", __func__, ret); 2069 2070 ret = clk_get_by_index(dev, 0, &clk); 2071 if (ret) 2072 debug("%s clk_get_by_index failed %d\n", __func__, ret); 2073 2074 pdata->phy_interface = eth_pdata->phy_interface; 2075 2076 if (ops->set_clock_selection) 2077 ops->set_clock_selection(pdata); 2078 2079 if (pdata->integrated_phy && ops->integrated_phy_powerup) 2080 ops->integrated_phy_powerup(pdata); 2081 2082 switch (eth_pdata->phy_interface) { 2083 case PHY_INTERFACE_MODE_RGMII: 2084 case PHY_INTERFACE_MODE_RGMII_RXID: 2085 /* 2086 * If the gmac clock is from internal pll, need to set and 2087 * check the return value for gmac clock at RGMII mode. If 2088 * the gmac clock is from external source, the clock rate 2089 * is not set, because of it is bypassed. 2090 */ 2091 if (!pdata->clock_input) { 2092 if (clk.id) { 2093 rate = clk_set_rate(&clk, 125000000); 2094 if (rate != 125000000) 2095 return -EINVAL; 2096 } 2097 } 2098 2099 if (eth_pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) 2100 pdata->rx_delay = -1; 2101 2102 /* Set to RGMII mode */ 2103 if (ops->set_to_rgmii) 2104 ops->set_to_rgmii(pdata); 2105 else 2106 return -EPERM; 2107 2108 break; 2109 case PHY_INTERFACE_MODE_RMII: 2110 /* The commet is the same as RGMII mode */ 2111 if (!pdata->clock_input) { 2112 if (clk.id) { 2113 rate = clk_set_rate(&clk, 50000000); 2114 if (rate != 50000000) 2115 return -EINVAL; 2116 } 2117 } 2118 2119 /* Set to RMII mode */ 2120 if (ops->set_to_rmii) 2121 ops->set_to_rmii(pdata); 2122 2123 break; 2124 default: 2125 debug("NO interface defined!\n"); 2126 return -ENXIO; 2127 } 2128 2129 #ifdef CONFIG_DWC_ETH_QOS 2130 return eqos_probe(dev); 2131 #else 2132 return designware_eth_probe(dev); 2133 #endif 2134 } 2135 2136 static int gmac_rockchip_eth_write_hwaddr(struct udevice *dev) 2137 { 2138 #if defined(CONFIG_DWC_ETH_QOS) 2139 return eqos_write_hwaddr(dev); 2140 #else 2141 return designware_eth_write_hwaddr(dev); 2142 #endif 2143 } 2144 2145 static int gmac_rockchip_eth_free_pkt(struct udevice *dev, uchar *packet, 2146 int length) 2147 { 2148 #ifdef CONFIG_DWC_ETH_QOS 2149 return eqos_free_pkt(dev, packet, length); 2150 #else 2151 return designware_eth_free_pkt(dev, packet, length); 2152 #endif 2153 } 2154 2155 static int gmac_rockchip_eth_send(struct udevice *dev, void *packet, 2156 int length) 2157 { 2158 #ifdef CONFIG_DWC_ETH_QOS 2159 return eqos_send(dev, packet, length); 2160 #else 2161 return designware_eth_send(dev, packet, length); 2162 #endif 2163 } 2164 2165 static int gmac_rockchip_eth_recv(struct udevice *dev, int flags, 2166 uchar **packetp) 2167 { 2168 #ifdef CONFIG_DWC_ETH_QOS 2169 return eqos_recv(dev, flags, packetp); 2170 #else 2171 return designware_eth_recv(dev, flags, packetp); 2172 #endif 2173 } 2174 2175 static int gmac_rockchip_eth_start(struct udevice *dev) 2176 { 2177 struct rockchip_eth_dev *priv = dev_get_priv(dev); 2178 struct rk_gmac_ops *ops = 2179 (struct rk_gmac_ops *)dev_get_driver_data(dev); 2180 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 2181 #ifndef CONFIG_DWC_ETH_QOS 2182 struct dw_eth_pdata *dw_pdata; 2183 struct eth_pdata *eth_pdata; 2184 #endif 2185 int ret; 2186 2187 #ifdef CONFIG_DWC_ETH_QOS 2188 ret = eqos_init(dev); 2189 #else 2190 dw_pdata = &pdata->dw_eth_pdata; 2191 eth_pdata = &dw_pdata->eth_pdata; 2192 ret = designware_eth_init((struct dw_eth_dev *)priv, 2193 eth_pdata->enetaddr); 2194 #endif 2195 if (ret) 2196 return ret; 2197 ret = ops->fix_mac_speed(pdata, priv); 2198 if (ret) 2199 return ret; 2200 2201 #ifdef CONFIG_DWC_ETH_QOS 2202 eqos_enable(dev); 2203 #else 2204 ret = designware_eth_enable((struct dw_eth_dev *)priv); 2205 if (ret) 2206 return ret; 2207 #endif 2208 2209 return 0; 2210 } 2211 2212 static void gmac_rockchip_eth_stop(struct udevice *dev) 2213 { 2214 #ifdef CONFIG_DWC_ETH_QOS 2215 eqos_stop(dev); 2216 #else 2217 designware_eth_stop(dev); 2218 #endif 2219 } 2220 2221 const struct eth_ops gmac_rockchip_eth_ops = { 2222 .start = gmac_rockchip_eth_start, 2223 .send = gmac_rockchip_eth_send, 2224 .recv = gmac_rockchip_eth_recv, 2225 .free_pkt = gmac_rockchip_eth_free_pkt, 2226 .stop = gmac_rockchip_eth_stop, 2227 .write_hwaddr = gmac_rockchip_eth_write_hwaddr, 2228 }; 2229 2230 #ifndef CONFIG_DWC_ETH_QOS 2231 const struct rk_gmac_ops px30_gmac_ops = { 2232 .fix_mac_speed = px30_gmac_fix_mac_speed, 2233 .set_to_rmii = px30_gmac_set_to_rmii, 2234 }; 2235 2236 const struct rk_gmac_ops rk1808_gmac_ops = { 2237 .fix_mac_speed = rk1808_gmac_fix_mac_speed, 2238 .set_to_rgmii = rk1808_gmac_set_to_rgmii, 2239 }; 2240 2241 const struct rk_gmac_ops rk3228_gmac_ops = { 2242 .fix_mac_speed = rk3228_gmac_fix_mac_speed, 2243 .set_to_rmii = rk3228_gmac_set_to_rmii, 2244 .set_to_rgmii = rk3228_gmac_set_to_rgmii, 2245 .integrated_phy_powerup = rk3228_gmac_integrated_phy_powerup, 2246 }; 2247 2248 const struct rk_gmac_ops rk3288_gmac_ops = { 2249 .fix_mac_speed = rk3288_gmac_fix_mac_speed, 2250 .set_to_rgmii = rk3288_gmac_set_to_rgmii, 2251 }; 2252 2253 const struct rk_gmac_ops rk3308_gmac_ops = { 2254 .fix_mac_speed = rk3308_gmac_fix_mac_speed, 2255 .set_to_rmii = rk3308_gmac_set_to_rmii, 2256 }; 2257 2258 const struct rk_gmac_ops rk3328_gmac_ops = { 2259 .fix_mac_speed = rk3328_gmac_fix_mac_speed, 2260 .set_to_rmii = rk3328_gmac_set_to_rmii, 2261 .set_to_rgmii = rk3328_gmac_set_to_rgmii, 2262 .integrated_phy_powerup = rk3328_gmac_integrated_phy_powerup, 2263 }; 2264 2265 const struct rk_gmac_ops rk3368_gmac_ops = { 2266 .fix_mac_speed = rk3368_gmac_fix_mac_speed, 2267 .set_to_rgmii = rk3368_gmac_set_to_rgmii, 2268 }; 2269 2270 const struct rk_gmac_ops rk3399_gmac_ops = { 2271 .fix_mac_speed = rk3399_gmac_fix_mac_speed, 2272 .set_to_rgmii = rk3399_gmac_set_to_rgmii, 2273 }; 2274 2275 const struct rk_gmac_ops rv1108_gmac_ops = { 2276 .fix_mac_speed = rv1108_set_rmii_speed, 2277 .set_to_rmii = rv1108_gmac_set_to_rmii, 2278 }; 2279 #else 2280 const struct rk_gmac_ops rk3506_gmac_ops = { 2281 .fix_mac_speed = rk3506_set_rmii_speed, 2282 .set_to_rmii = rk3506_set_to_rmii, 2283 .set_clock_selection = rk3506_set_clock_selection, 2284 }; 2285 2286 const struct rk_gmac_ops rk3528_gmac_ops = { 2287 .fix_mac_speed = rk3528_set_rgmii_speed, 2288 .set_to_rgmii = rk3528_set_to_rgmii, 2289 .set_to_rmii = rk3528_set_to_rmii, 2290 .set_clock_selection = rk3528_set_clock_selection, 2291 .integrated_phy_powerup = rk3528_gmac_integrated_phy_powerup, 2292 }; 2293 2294 const struct rk_gmac_ops rk3562_gmac_ops = { 2295 .fix_mac_speed = rk3562_set_gmac_speed, 2296 .set_to_rgmii = rk3562_set_to_rgmii, 2297 .set_to_rmii = rk3562_set_to_rmii, 2298 .set_clock_selection = rk3562_set_clock_selection, 2299 }; 2300 2301 const struct rk_gmac_ops rk3568_gmac_ops = { 2302 .fix_mac_speed = rv1126_set_rgmii_speed, 2303 .set_to_rgmii = rk3568_set_to_rgmii, 2304 .set_to_rmii = rk3568_set_to_rmii, 2305 }; 2306 2307 const struct rk_gmac_ops rk3588_gmac_ops = { 2308 .fix_mac_speed = rk3588_set_rgmii_speed, 2309 .set_to_rgmii = rk3588_set_to_rgmii, 2310 .set_to_rmii = rk3588_set_to_rmii, 2311 .set_clock_selection = rk3588_set_clock_selection, 2312 }; 2313 2314 const struct rk_gmac_ops rv1103b_gmac_ops = { 2315 .fix_mac_speed = rv1106_set_rmii_speed, 2316 .set_to_rmii = rv1103b_set_to_rmii, 2317 .integrated_phy_powerup = rv1106_gmac_integrated_phy_powerup, 2318 }; 2319 2320 const struct rk_gmac_ops rv1106_gmac_ops = { 2321 .fix_mac_speed = rv1106_set_rmii_speed, 2322 .set_to_rmii = rv1106_set_to_rmii, 2323 .integrated_phy_powerup = rv1106_gmac_integrated_phy_powerup, 2324 }; 2325 2326 const struct rk_gmac_ops rv1126_gmac_ops = { 2327 .fix_mac_speed = rv1126_set_rgmii_speed, 2328 .set_to_rgmii = rv1126_set_to_rgmii, 2329 .set_to_rmii = rv1126_set_to_rmii, 2330 }; 2331 #endif 2332 2333 static const struct udevice_id rockchip_gmac_ids[] = { 2334 #ifndef CONFIG_DWC_ETH_QOS 2335 #ifdef CONFIG_ROCKCHIP_PX30 2336 { .compatible = "rockchip,px30-gmac", 2337 .data = (ulong)&px30_gmac_ops }, 2338 #endif 2339 2340 #ifdef CONFIG_ROCKCHIP_RK1808 2341 { .compatible = "rockchip,rk1808-gmac", 2342 .data = (ulong)&rk1808_gmac_ops }, 2343 #endif 2344 2345 #ifdef CONFIG_ROCKCHIP_RK3228 2346 { .compatible = "rockchip,rk3228-gmac", 2347 .data = (ulong)&rk3228_gmac_ops }, 2348 #endif 2349 2350 #ifdef CONFIG_ROCKCHIP_RK3288 2351 { .compatible = "rockchip,rk3288-gmac", 2352 .data = (ulong)&rk3288_gmac_ops }, 2353 #endif 2354 2355 #ifdef CONFIG_ROCKCHIP_RK3308 2356 { .compatible = "rockchip,rk3308-mac", 2357 .data = (ulong)&rk3308_gmac_ops }, 2358 #endif 2359 2360 #ifdef CONFIG_ROCKCHIP_RK3328 2361 { .compatible = "rockchip,rk3328-gmac", 2362 .data = (ulong)&rk3328_gmac_ops }, 2363 #endif 2364 2365 #ifdef CONFIG_ROCKCHIP_RK3368 2366 { .compatible = "rockchip,rk3368-gmac", 2367 .data = (ulong)&rk3368_gmac_ops }, 2368 #endif 2369 2370 #ifdef CONFIG_ROCKCHIP_RK3399 2371 { .compatible = "rockchip,rk3399-gmac", 2372 .data = (ulong)&rk3399_gmac_ops }, 2373 #endif 2374 2375 #ifdef CONFIG_ROCKCHIP_RV1108 2376 { .compatible = "rockchip,rv1108-gmac", 2377 .data = (ulong)&rv1108_gmac_ops }, 2378 #endif 2379 #else 2380 #ifdef CONFIG_ROCKCHIP_RK3506 2381 { .compatible = "rockchip,rk3506-gmac", 2382 .data = (ulong)&rk3506_gmac_ops }, 2383 #endif 2384 2385 #ifdef CONFIG_ROCKCHIP_RK3528 2386 { .compatible = "rockchip,rk3528-gmac", 2387 .data = (ulong)&rk3528_gmac_ops }, 2388 #endif 2389 2390 #ifdef CONFIG_ROCKCHIP_RK3562 2391 { .compatible = "rockchip,rk3562-gmac", 2392 .data = (ulong)&rk3562_gmac_ops }, 2393 #endif 2394 2395 #ifdef CONFIG_ROCKCHIP_RK3568 2396 { .compatible = "rockchip,rk3568-gmac", 2397 .data = (ulong)&rk3568_gmac_ops }, 2398 #endif 2399 2400 #ifdef CONFIG_ROCKCHIP_RK3588 2401 { .compatible = "rockchip,rk3588-gmac", 2402 .data = (ulong)&rk3588_gmac_ops }, 2403 #endif 2404 2405 #ifdef CONFIG_ROCKCHIP_RV1103B 2406 { .compatible = "rockchip,rv1103b-gmac", 2407 .data = (ulong)&rv1103b_gmac_ops }, 2408 #endif 2409 2410 #ifdef CONFIG_ROCKCHIP_RV1106 2411 { .compatible = "rockchip,rv1106-gmac", 2412 .data = (ulong)&rv1106_gmac_ops }, 2413 #endif 2414 2415 #ifdef CONFIG_ROCKCHIP_RV1126 2416 { .compatible = "rockchip,rv1126-gmac", 2417 .data = (ulong)&rv1126_gmac_ops }, 2418 #endif 2419 #endif 2420 { } 2421 }; 2422 2423 U_BOOT_DRIVER(eth_gmac_rockchip) = { 2424 .name = "gmac_rockchip", 2425 .id = UCLASS_ETH, 2426 .of_match = rockchip_gmac_ids, 2427 .ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata, 2428 .probe = gmac_rockchip_probe, 2429 .ops = &gmac_rockchip_eth_ops, 2430 .priv_auto_alloc_size = sizeof(struct rockchip_eth_dev), 2431 .platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata), 2432 .flags = DM_FLAG_ALLOC_PRIV_DMA, 2433 }; 2434