1 /* 2 * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Rockchip GMAC ethernet IP driver for U-Boot 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <clk.h> 12 #include <phy.h> 13 #include <syscon.h> 14 #include <asm/io.h> 15 #include <asm/arch/periph.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/hardware.h> 18 #include <asm/arch/grf_rk322x.h> 19 #include <asm/arch/grf_rk3288.h> 20 #include <asm/arch/grf_rk3328.h> 21 #include <asm/arch/grf_rk3368.h> 22 #include <asm/arch/grf_rk3399.h> 23 #include <asm/arch/grf_rv1108.h> 24 #include <dm/pinctrl.h> 25 #include <dt-bindings/clock/rk3288-cru.h> 26 #include "designware.h" 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 /* 31 * Platform data for the gmac 32 * 33 * dw_eth_pdata: Required platform data for designware driver (must be first) 34 */ 35 struct gmac_rockchip_platdata { 36 struct dw_eth_pdata dw_eth_pdata; 37 bool clock_input; 38 int tx_delay; 39 int rx_delay; 40 }; 41 42 struct rk_gmac_ops { 43 int (*fix_mac_speed)(struct dw_eth_dev *priv); 44 void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata); 45 void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata); 46 }; 47 48 void gmac_set_rgmii(struct udevice *dev, u32 tx_delay, u32 rx_delay) 49 { 50 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 51 struct rk_gmac_ops *ops = 52 (struct rk_gmac_ops *)dev_get_driver_data(dev); 53 54 pdata->tx_delay = tx_delay; 55 pdata->rx_delay = rx_delay; 56 57 ops->set_to_rgmii(pdata); 58 } 59 60 static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) 61 { 62 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 63 const char *string; 64 65 string = dev_read_string(dev, "clock_in_out"); 66 if (!strcmp(string, "input")) 67 pdata->clock_input = true; 68 else 69 pdata->clock_input = false; 70 71 /* Check the new naming-style first... */ 72 pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT); 73 pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT); 74 75 /* ... and fall back to the old naming style or default, if necessary */ 76 if (pdata->tx_delay == -ENOENT) 77 pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30); 78 if (pdata->rx_delay == -ENOENT) 79 pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10); 80 81 return designware_eth_ofdata_to_platdata(dev); 82 } 83 84 static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv) 85 { 86 struct rk322x_grf *grf; 87 int clk; 88 enum { 89 RK3228_GMAC_CLK_SEL_SHIFT = 8, 90 RK3228_GMAC_CLK_SEL_MASK = GENMASK(9, 8), 91 RK3228_GMAC_CLK_SEL_125M = 0 << 8, 92 RK3228_GMAC_CLK_SEL_25M = 3 << 8, 93 RK3228_GMAC_CLK_SEL_2_5M = 2 << 8, 94 }; 95 96 switch (priv->phydev->speed) { 97 case 10: 98 clk = RK3228_GMAC_CLK_SEL_2_5M; 99 break; 100 case 100: 101 clk = RK3228_GMAC_CLK_SEL_25M; 102 break; 103 case 1000: 104 clk = RK3228_GMAC_CLK_SEL_125M; 105 break; 106 default: 107 debug("Unknown phy speed: %d\n", priv->phydev->speed); 108 return -EINVAL; 109 } 110 111 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 112 rk_clrsetreg(&grf->mac_con[1], RK3228_GMAC_CLK_SEL_MASK, clk); 113 114 return 0; 115 } 116 117 static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv) 118 { 119 struct rk3288_grf *grf; 120 int clk; 121 122 switch (priv->phydev->speed) { 123 case 10: 124 clk = RK3288_GMAC_CLK_SEL_2_5M; 125 break; 126 case 100: 127 clk = RK3288_GMAC_CLK_SEL_25M; 128 break; 129 case 1000: 130 clk = RK3288_GMAC_CLK_SEL_125M; 131 break; 132 default: 133 debug("Unknown phy speed: %d\n", priv->phydev->speed); 134 return -EINVAL; 135 } 136 137 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 138 rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk); 139 140 return 0; 141 } 142 143 static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv) 144 { 145 struct rk3328_grf_regs *grf; 146 int clk; 147 enum { 148 RK3328_GMAC_CLK_SEL_SHIFT = 11, 149 RK3328_GMAC_CLK_SEL_MASK = GENMASK(12, 11), 150 RK3328_GMAC_CLK_SEL_125M = 0 << 11, 151 RK3328_GMAC_CLK_SEL_25M = 3 << 11, 152 RK3328_GMAC_CLK_SEL_2_5M = 2 << 11, 153 }; 154 155 switch (priv->phydev->speed) { 156 case 10: 157 clk = RK3328_GMAC_CLK_SEL_2_5M; 158 break; 159 case 100: 160 clk = RK3328_GMAC_CLK_SEL_25M; 161 break; 162 case 1000: 163 clk = RK3328_GMAC_CLK_SEL_125M; 164 break; 165 default: 166 debug("Unknown phy speed: %d\n", priv->phydev->speed); 167 return -EINVAL; 168 } 169 170 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 171 rk_clrsetreg(&grf->mac_con[1], RK3328_GMAC_CLK_SEL_MASK, clk); 172 173 return 0; 174 } 175 176 static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv) 177 { 178 struct rk3368_grf *grf; 179 int clk; 180 enum { 181 RK3368_GMAC_CLK_SEL_2_5M = 2 << 4, 182 RK3368_GMAC_CLK_SEL_25M = 3 << 4, 183 RK3368_GMAC_CLK_SEL_125M = 0 << 4, 184 RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4), 185 }; 186 187 switch (priv->phydev->speed) { 188 case 10: 189 clk = RK3368_GMAC_CLK_SEL_2_5M; 190 break; 191 case 100: 192 clk = RK3368_GMAC_CLK_SEL_25M; 193 break; 194 case 1000: 195 clk = RK3368_GMAC_CLK_SEL_125M; 196 break; 197 default: 198 debug("Unknown phy speed: %d\n", priv->phydev->speed); 199 return -EINVAL; 200 } 201 202 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 203 rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk); 204 205 return 0; 206 } 207 208 static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv) 209 { 210 struct rk3399_grf_regs *grf; 211 int clk; 212 213 switch (priv->phydev->speed) { 214 case 10: 215 clk = RK3399_GMAC_CLK_SEL_2_5M; 216 break; 217 case 100: 218 clk = RK3399_GMAC_CLK_SEL_25M; 219 break; 220 case 1000: 221 clk = RK3399_GMAC_CLK_SEL_125M; 222 break; 223 default: 224 debug("Unknown phy speed: %d\n", priv->phydev->speed); 225 return -EINVAL; 226 } 227 228 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 229 rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk); 230 231 return 0; 232 } 233 234 static int rv1108_set_rmii_speed(struct dw_eth_dev *priv) 235 { 236 struct rv1108_grf *grf; 237 int clk, speed; 238 enum { 239 RV1108_GMAC_SPEED_MASK = BIT(2), 240 RV1108_GMAC_SPEED_10M = 0 << 2, 241 RV1108_GMAC_SPEED_100M = 1 << 2, 242 RV1108_GMAC_CLK_SEL_MASK = BIT(7), 243 RV1108_GMAC_CLK_SEL_2_5M = 0 << 7, 244 RV1108_GMAC_CLK_SEL_25M = 1 << 7, 245 }; 246 247 switch (priv->phydev->speed) { 248 case 10: 249 clk = RV1108_GMAC_CLK_SEL_2_5M; 250 speed = RV1108_GMAC_SPEED_10M; 251 break; 252 case 100: 253 clk = RV1108_GMAC_CLK_SEL_25M; 254 speed = RV1108_GMAC_SPEED_100M; 255 break; 256 default: 257 debug("Unknown phy speed: %d\n", priv->phydev->speed); 258 return -EINVAL; 259 } 260 261 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 262 rk_clrsetreg(&grf->gmac_con0, 263 RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK, 264 clk | speed); 265 266 return 0; 267 } 268 269 static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 270 { 271 struct rk322x_grf *grf; 272 enum { 273 RK3228_RMII_MODE_SHIFT = 10, 274 RK3228_RMII_MODE_MASK = BIT(10), 275 276 RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4, 277 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 278 RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 279 280 RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 281 RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 282 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 283 284 RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 285 RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 286 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 287 }; 288 enum { 289 RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 290 RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 291 292 RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 293 RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 294 }; 295 296 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 297 rk_clrsetreg(&grf->mac_con[1], 298 RK3228_RMII_MODE_MASK | 299 RK3228_GMAC_PHY_INTF_SEL_MASK | 300 RK3228_RXCLK_DLY_ENA_GMAC_MASK | 301 RK3228_TXCLK_DLY_ENA_GMAC_MASK, 302 RK3228_GMAC_PHY_INTF_SEL_RGMII | 303 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE | 304 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE); 305 306 rk_clrsetreg(&grf->mac_con[0], 307 RK3228_CLK_RX_DL_CFG_GMAC_MASK | 308 RK3228_CLK_TX_DL_CFG_GMAC_MASK, 309 pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT | 310 pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT); 311 } 312 313 static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 314 { 315 struct rk3288_grf *grf; 316 317 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 318 rk_clrsetreg(&grf->soc_con1, 319 RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK, 320 RK3288_GMAC_PHY_INTF_SEL_RGMII); 321 322 rk_clrsetreg(&grf->soc_con3, 323 RK3288_RXCLK_DLY_ENA_GMAC_MASK | 324 RK3288_TXCLK_DLY_ENA_GMAC_MASK | 325 RK3288_CLK_RX_DL_CFG_GMAC_MASK | 326 RK3288_CLK_TX_DL_CFG_GMAC_MASK, 327 RK3288_RXCLK_DLY_ENA_GMAC_ENABLE | 328 RK3288_TXCLK_DLY_ENA_GMAC_ENABLE | 329 pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT | 330 pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT); 331 } 332 333 static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 334 { 335 struct rk3328_grf_regs *grf; 336 enum { 337 RK3328_RMII_MODE_SHIFT = 9, 338 RK3328_RMII_MODE_MASK = BIT(9), 339 340 RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4, 341 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 342 RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 343 344 RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 345 RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 346 RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 347 348 RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 349 RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 350 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 351 }; 352 enum { 353 RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 354 RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 355 356 RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 357 RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 358 }; 359 360 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 361 rk_clrsetreg(&grf->mac_con[1], 362 RK3328_RMII_MODE_MASK | 363 RK3328_GMAC_PHY_INTF_SEL_MASK | 364 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 365 RK3328_TXCLK_DLY_ENA_GMAC_MASK, 366 RK3328_GMAC_PHY_INTF_SEL_RGMII | 367 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 368 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE); 369 370 rk_clrsetreg(&grf->mac_con[0], 371 RK3328_CLK_RX_DL_CFG_GMAC_MASK | 372 RK3328_CLK_TX_DL_CFG_GMAC_MASK, 373 pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT | 374 pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT); 375 } 376 377 static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 378 { 379 struct rk3368_grf *grf; 380 enum { 381 RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9, 382 RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9), 383 RK3368_RMII_MODE_MASK = BIT(6), 384 RK3368_RMII_MODE = BIT(6), 385 }; 386 enum { 387 RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15), 388 RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 389 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15), 390 RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7), 391 RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 392 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7), 393 RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8, 394 RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 395 RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0, 396 RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 397 }; 398 399 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 400 rk_clrsetreg(&grf->soc_con15, 401 RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK, 402 RK3368_GMAC_PHY_INTF_SEL_RGMII); 403 404 rk_clrsetreg(&grf->soc_con16, 405 RK3368_RXCLK_DLY_ENA_GMAC_MASK | 406 RK3368_TXCLK_DLY_ENA_GMAC_MASK | 407 RK3368_CLK_RX_DL_CFG_GMAC_MASK | 408 RK3368_CLK_TX_DL_CFG_GMAC_MASK, 409 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE | 410 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE | 411 pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT | 412 pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT); 413 } 414 415 static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 416 { 417 struct rk3399_grf_regs *grf; 418 419 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 420 421 rk_clrsetreg(&grf->soc_con5, 422 RK3399_GMAC_PHY_INTF_SEL_MASK, 423 RK3399_GMAC_PHY_INTF_SEL_RGMII); 424 425 rk_clrsetreg(&grf->soc_con6, 426 RK3399_RXCLK_DLY_ENA_GMAC_MASK | 427 RK3399_TXCLK_DLY_ENA_GMAC_MASK | 428 RK3399_CLK_RX_DL_CFG_GMAC_MASK | 429 RK3399_CLK_TX_DL_CFG_GMAC_MASK, 430 RK3399_RXCLK_DLY_ENA_GMAC_ENABLE | 431 RK3399_TXCLK_DLY_ENA_GMAC_ENABLE | 432 pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT | 433 pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT); 434 } 435 436 static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 437 { 438 struct rv1108_grf *grf; 439 440 enum { 441 RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 442 RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4, 443 }; 444 445 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 446 rk_clrsetreg(&grf->gmac_con0, 447 RV1108_GMAC_PHY_INTF_SEL_MASK, 448 RV1108_GMAC_PHY_INTF_SEL_RMII); 449 } 450 451 static int gmac_rockchip_probe(struct udevice *dev) 452 { 453 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 454 struct rk_gmac_ops *ops = 455 (struct rk_gmac_ops *)dev_get_driver_data(dev); 456 struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev); 457 struct eth_pdata *eth_pdata = &dw_pdata->eth_pdata; 458 struct clk clk; 459 ulong rate; 460 int ret; 461 462 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 463 ret = clk_set_defaults(dev); 464 if (ret) 465 debug("%s clk_set_defaults failed %d\n", __func__, ret); 466 467 ret = clk_get_by_index(dev, 0, &clk); 468 if (ret) 469 return ret; 470 471 switch (eth_pdata->phy_interface) { 472 case PHY_INTERFACE_MODE_RGMII: 473 /* 474 * If the gmac clock is from internal pll, need to set and 475 * check the return value for gmac clock at RGMII mode. If 476 * the gmac clock is from external source, the clock rate 477 * is not set, because of it is bypassed. 478 */ 479 if (!pdata->clock_input) { 480 rate = clk_set_rate(&clk, 125000000); 481 if (rate != 125000000) 482 return -EINVAL; 483 } 484 485 /* Set to RGMII mode */ 486 if (ops->set_to_rgmii) 487 ops->set_to_rgmii(pdata); 488 else 489 return -EPERM; 490 491 break; 492 case PHY_INTERFACE_MODE_RMII: 493 /* The commet is the same as RGMII mode */ 494 if (!pdata->clock_input) { 495 rate = clk_set_rate(&clk, 50000000); 496 if (rate != 50000000) 497 return -EINVAL; 498 } 499 500 /* Set to RMII mode */ 501 if (ops->set_to_rmii) 502 ops->set_to_rmii(pdata); 503 else 504 return -EPERM; 505 506 break; 507 default: 508 debug("NO interface defined!\n"); 509 return -ENXIO; 510 } 511 512 return designware_eth_probe(dev); 513 } 514 515 static int gmac_rockchip_eth_start(struct udevice *dev) 516 { 517 struct eth_pdata *pdata = dev_get_platdata(dev); 518 struct dw_eth_dev *priv = dev_get_priv(dev); 519 struct rk_gmac_ops *ops = 520 (struct rk_gmac_ops *)dev_get_driver_data(dev); 521 int ret; 522 523 ret = designware_eth_init(priv, pdata->enetaddr); 524 if (ret) 525 return ret; 526 ret = ops->fix_mac_speed(priv); 527 if (ret) 528 return ret; 529 ret = designware_eth_enable(priv); 530 if (ret) 531 return ret; 532 533 return 0; 534 } 535 536 const struct eth_ops gmac_rockchip_eth_ops = { 537 .start = gmac_rockchip_eth_start, 538 .send = designware_eth_send, 539 .recv = designware_eth_recv, 540 .free_pkt = designware_eth_free_pkt, 541 .stop = designware_eth_stop, 542 .write_hwaddr = designware_eth_write_hwaddr, 543 }; 544 545 const struct rk_gmac_ops rk3228_gmac_ops = { 546 .fix_mac_speed = rk3228_gmac_fix_mac_speed, 547 .set_to_rgmii = rk3228_gmac_set_to_rgmii, 548 }; 549 550 const struct rk_gmac_ops rk3288_gmac_ops = { 551 .fix_mac_speed = rk3288_gmac_fix_mac_speed, 552 .set_to_rgmii = rk3288_gmac_set_to_rgmii, 553 }; 554 555 const struct rk_gmac_ops rk3328_gmac_ops = { 556 .fix_mac_speed = rk3328_gmac_fix_mac_speed, 557 .set_to_rgmii = rk3328_gmac_set_to_rgmii, 558 }; 559 560 const struct rk_gmac_ops rk3368_gmac_ops = { 561 .fix_mac_speed = rk3368_gmac_fix_mac_speed, 562 .set_to_rgmii = rk3368_gmac_set_to_rgmii, 563 }; 564 565 const struct rk_gmac_ops rk3399_gmac_ops = { 566 .fix_mac_speed = rk3399_gmac_fix_mac_speed, 567 .set_to_rgmii = rk3399_gmac_set_to_rgmii, 568 }; 569 570 const struct rk_gmac_ops rv1108_gmac_ops = { 571 .fix_mac_speed = rv1108_set_rmii_speed, 572 .set_to_rmii = rv1108_gmac_set_to_rmii, 573 }; 574 575 static const struct udevice_id rockchip_gmac_ids[] = { 576 { .compatible = "rockchip,rk3228-gmac", 577 .data = (ulong)&rk3228_gmac_ops }, 578 { .compatible = "rockchip,rk3288-gmac", 579 .data = (ulong)&rk3288_gmac_ops }, 580 { .compatible = "rockchip,rk3328-gmac", 581 .data = (ulong)&rk3328_gmac_ops }, 582 { .compatible = "rockchip,rk3368-gmac", 583 .data = (ulong)&rk3368_gmac_ops }, 584 { .compatible = "rockchip,rk3399-gmac", 585 .data = (ulong)&rk3399_gmac_ops }, 586 { .compatible = "rockchip,rv1108-gmac", 587 .data = (ulong)&rv1108_gmac_ops }, 588 { } 589 }; 590 591 U_BOOT_DRIVER(eth_gmac_rockchip) = { 592 .name = "gmac_rockchip", 593 .id = UCLASS_ETH, 594 .of_match = rockchip_gmac_ids, 595 .ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata, 596 .probe = gmac_rockchip_probe, 597 .ops = &gmac_rockchip_eth_ops, 598 .priv_auto_alloc_size = sizeof(struct dw_eth_dev), 599 .platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata), 600 .flags = DM_FLAG_ALLOC_PRIV_DMA, 601 }; 602