1 /* 2 * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Rockchip GMAC ethernet IP driver for U-Boot 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <clk.h> 12 #include <misc.h> 13 #include <phy.h> 14 #include <reset.h> 15 #include <syscon.h> 16 #include <asm/io.h> 17 #include <asm/arch/periph.h> 18 #include <asm/arch/clock.h> 19 #include <asm/arch/hardware.h> 20 #ifdef CONFIG_DWC_ETH_QOS 21 #include <asm/arch/grf_rk3568.h> 22 #include <asm/arch/grf_rk3588.h> 23 #include <asm/arch/grf_rv1106.h> 24 #include <asm/arch/grf_rv1126.h> 25 #include "dwc_eth_qos.h" 26 #else 27 #include <asm/arch/grf_px30.h> 28 #include <asm/arch/grf_rk1808.h> 29 #include <asm/arch/grf_rk322x.h> 30 #include <asm/arch/grf_rk3288.h> 31 #include <asm/arch/grf_rk3308.h> 32 #include <asm/arch/grf_rk3328.h> 33 #include <asm/arch/grf_rk3368.h> 34 #include <asm/arch/grf_rk3399.h> 35 #include <asm/arch/grf_rv1108.h> 36 #include "designware.h" 37 #include <dt-bindings/clock/rk3288-cru.h> 38 #endif 39 #include <dm/pinctrl.h> 40 #include <dm/of_access.h> 41 42 DECLARE_GLOBAL_DATA_PTR; 43 44 struct rockchip_eth_dev { 45 #ifdef CONFIG_DWC_ETH_QOS 46 struct eqos_priv eqos; 47 #else 48 struct dw_eth_dev dw; 49 #endif 50 int phy_interface; 51 }; 52 53 /* 54 * Platform data for the gmac 55 * 56 * dw_eth_pdata: Required platform data for designware driver (must be first) 57 */ 58 struct gmac_rockchip_platdata { 59 #ifndef CONFIG_DWC_ETH_QOS 60 struct dw_eth_pdata dw_eth_pdata; 61 #else 62 struct eth_pdata eth_pdata; 63 #endif 64 struct reset_ctl phy_reset; 65 bool integrated_phy; 66 bool clock_input; 67 int phy_interface; 68 int tx_delay; 69 int rx_delay; 70 int bus_id; 71 }; 72 73 struct rk_gmac_ops { 74 #ifdef CONFIG_DWC_ETH_QOS 75 const struct eqos_config config; 76 #endif 77 int (*fix_mac_speed)(struct gmac_rockchip_platdata *pdata, 78 struct rockchip_eth_dev *dev); 79 void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata); 80 void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata); 81 void (*set_clock_selection)(struct gmac_rockchip_platdata *pdata); 82 void (*integrated_phy_powerup)(struct gmac_rockchip_platdata *pdata); 83 }; 84 85 #ifdef CONFIG_DWC_ETH_QOS 86 static const struct eqos_config eqos_rockchip_config = { 87 .reg_access_always_ok = false, 88 .mdio_wait = 10000, 89 .swr_wait = 200, 90 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED, 91 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_100_150, 92 .ops = &eqos_rockchip_ops, 93 }; 94 #endif 95 96 void gmac_set_rgmii(struct udevice *dev, u32 tx_delay, u32 rx_delay) 97 { 98 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 99 struct rk_gmac_ops *ops = 100 (struct rk_gmac_ops *)dev_get_driver_data(dev); 101 102 pdata->tx_delay = tx_delay; 103 pdata->rx_delay = rx_delay; 104 105 ops->set_to_rgmii(pdata); 106 } 107 108 static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) 109 { 110 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 111 struct ofnode_phandle_args args; 112 struct udevice *phydev; 113 const char *string; 114 int ret; 115 116 string = dev_read_string(dev, "clock_in_out"); 117 if (!strcmp(string, "input")) 118 pdata->clock_input = true; 119 else 120 pdata->clock_input = false; 121 122 /* If phy-handle property is passed from DT, use it as the PHY */ 123 ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &args); 124 if (ret) { 125 debug("Cannot get phy phandle: ret=%d\n", ret); 126 pdata->integrated_phy = dev_read_bool(dev, "phy-is-integrated"); 127 } else { 128 debug("Found phy-handle subnode\n"); 129 pdata->integrated_phy = ofnode_read_bool(args.node, 130 "phy-is-integrated"); 131 } 132 133 if (pdata->integrated_phy) { 134 ret = reset_get_by_name(dev, "mac-phy", &pdata->phy_reset); 135 if (ret) { 136 ret = uclass_get_device_by_ofnode(UCLASS_ETH_PHY, args.node, &phydev); 137 if (ret) { 138 debug("Get phydev by ofnode failed: err=%d\n", ret); 139 return ret; 140 } 141 142 ret = reset_get_by_index(phydev, 0, &pdata->phy_reset); 143 if (ret) { 144 debug("No PHY reset control found: ret=%d\n", ret); 145 return ret; 146 } 147 } 148 } 149 150 /* Check the new naming-style first... */ 151 pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT); 152 pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT); 153 154 /* ... and fall back to the old naming style or default, if necessary */ 155 if (pdata->tx_delay == -ENOENT) 156 pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30); 157 if (pdata->rx_delay == -ENOENT) 158 pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10); 159 160 #ifdef CONFIG_DWC_ETH_QOS 161 return 0; 162 #else 163 return designware_eth_ofdata_to_platdata(dev); 164 #endif 165 } 166 167 #ifndef CONFIG_DWC_ETH_QOS 168 static int px30_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 169 struct rockchip_eth_dev *dev) 170 { 171 struct dw_eth_dev *priv = &dev->dw; 172 struct px30_grf *grf; 173 struct clk clk_speed; 174 int speed, ret; 175 enum { 176 PX30_GMAC_SPEED_SHIFT = 0x2, 177 PX30_GMAC_SPEED_MASK = BIT(2), 178 PX30_GMAC_SPEED_10M = 0, 179 PX30_GMAC_SPEED_100M = BIT(2), 180 }; 181 182 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 183 &clk_speed); 184 if (ret) 185 return ret; 186 187 switch (priv->phydev->speed) { 188 case 10: 189 speed = PX30_GMAC_SPEED_10M; 190 ret = clk_set_rate(&clk_speed, 2500000); 191 if (ret) 192 return ret; 193 break; 194 case 100: 195 speed = PX30_GMAC_SPEED_100M; 196 ret = clk_set_rate(&clk_speed, 25000000); 197 if (ret) 198 return ret; 199 break; 200 default: 201 debug("Unknown phy speed: %d\n", priv->phydev->speed); 202 return -EINVAL; 203 } 204 205 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 206 rk_clrsetreg(&grf->mac_con1, PX30_GMAC_SPEED_MASK, speed); 207 208 return 0; 209 } 210 211 static int rk1808_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 212 struct rockchip_eth_dev *dev) 213 { 214 struct dw_eth_dev *priv = &dev->dw; 215 struct clk clk_speed; 216 int ret; 217 218 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 219 &clk_speed); 220 if (ret) 221 return ret; 222 223 switch (priv->phydev->speed) { 224 case 10: 225 ret = clk_set_rate(&clk_speed, 2500000); 226 if (ret) 227 return ret; 228 break; 229 case 100: 230 ret = clk_set_rate(&clk_speed, 25000000); 231 if (ret) 232 return ret; 233 break; 234 case 1000: 235 ret = clk_set_rate(&clk_speed, 125000000); 236 if (ret) 237 return ret; 238 break; 239 default: 240 debug("Unknown phy speed: %d\n", priv->phydev->speed); 241 return -EINVAL; 242 } 243 244 return 0; 245 } 246 247 static int rk3228_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 248 struct rockchip_eth_dev *dev) 249 { 250 struct dw_eth_dev *priv = &dev->dw; 251 struct rk322x_grf *grf; 252 int clk; 253 enum { 254 RK3228_GMAC_CLK_SEL_SHIFT = 8, 255 RK3228_GMAC_CLK_SEL_MASK = GENMASK(9, 8), 256 RK3228_GMAC_CLK_SEL_125M = 0 << 8, 257 RK3228_GMAC_CLK_SEL_25M = 3 << 8, 258 RK3228_GMAC_CLK_SEL_2_5M = 2 << 8, 259 260 RK3228_GMAC_RMII_CLK_MASK = BIT(7), 261 RK3228_GMAC_RMII_CLK_2_5M = 0, 262 RK3228_GMAC_RMII_CLK_25M = BIT(7), 263 264 RK3228_GMAC_RMII_SPEED_MASK = BIT(2), 265 RK3228_GMAC_RMII_SPEED_10 = 0, 266 RK3228_GMAC_RMII_SPEED_100 = BIT(2), 267 }; 268 269 switch (priv->phydev->speed) { 270 case 10: 271 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 272 (RK3228_GMAC_RMII_CLK_2_5M | RK3228_GMAC_RMII_SPEED_10) : 273 RK3228_GMAC_CLK_SEL_2_5M; 274 break; 275 case 100: 276 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 277 (RK3228_GMAC_RMII_CLK_25M | RK3228_GMAC_RMII_SPEED_100) : 278 RK3228_GMAC_CLK_SEL_25M; 279 break; 280 case 1000: 281 clk = RK3228_GMAC_CLK_SEL_125M; 282 break; 283 default: 284 debug("Unknown phy speed: %d\n", priv->phydev->speed); 285 return -EINVAL; 286 } 287 288 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 289 rk_clrsetreg(&grf->mac_con[1], 290 RK3228_GMAC_CLK_SEL_MASK | 291 RK3228_GMAC_RMII_CLK_MASK | 292 RK3228_GMAC_RMII_SPEED_MASK, 293 clk); 294 295 return 0; 296 } 297 298 static int rk3288_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 299 struct rockchip_eth_dev *dev) 300 { 301 struct dw_eth_dev *priv = &dev->dw; 302 struct rk3288_grf *grf; 303 int clk; 304 305 switch (priv->phydev->speed) { 306 case 10: 307 clk = RK3288_GMAC_CLK_SEL_2_5M; 308 break; 309 case 100: 310 clk = RK3288_GMAC_CLK_SEL_25M; 311 break; 312 case 1000: 313 clk = RK3288_GMAC_CLK_SEL_125M; 314 break; 315 default: 316 debug("Unknown phy speed: %d\n", priv->phydev->speed); 317 return -EINVAL; 318 } 319 320 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 321 rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk); 322 323 return 0; 324 } 325 326 static int rk3308_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 327 struct rockchip_eth_dev *dev) 328 { 329 struct dw_eth_dev *priv = &dev->dw; 330 struct rk3308_grf *grf; 331 struct clk clk_speed; 332 int speed, ret; 333 enum { 334 RK3308_GMAC_SPEED_SHIFT = 0x0, 335 RK3308_GMAC_SPEED_MASK = BIT(0), 336 RK3308_GMAC_SPEED_10M = 0, 337 RK3308_GMAC_SPEED_100M = BIT(0), 338 }; 339 340 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 341 &clk_speed); 342 if (ret) 343 return ret; 344 345 switch (priv->phydev->speed) { 346 case 10: 347 speed = RK3308_GMAC_SPEED_10M; 348 ret = clk_set_rate(&clk_speed, 2500000); 349 if (ret) 350 return ret; 351 break; 352 case 100: 353 speed = RK3308_GMAC_SPEED_100M; 354 ret = clk_set_rate(&clk_speed, 25000000); 355 if (ret) 356 return ret; 357 break; 358 default: 359 debug("Unknown phy speed: %d\n", priv->phydev->speed); 360 return -EINVAL; 361 } 362 363 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 364 rk_clrsetreg(&grf->mac_con0, RK3308_GMAC_SPEED_MASK, speed); 365 366 return 0; 367 } 368 369 static int rk3328_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 370 struct rockchip_eth_dev *dev) 371 { 372 struct dw_eth_dev *priv = &dev->dw; 373 struct rk3328_grf_regs *grf; 374 int clk; 375 enum { 376 RK3328_GMAC_CLK_SEL_SHIFT = 11, 377 RK3328_GMAC_CLK_SEL_MASK = GENMASK(12, 11), 378 RK3328_GMAC_CLK_SEL_125M = 0 << 11, 379 RK3328_GMAC_CLK_SEL_25M = 3 << 11, 380 RK3328_GMAC_CLK_SEL_2_5M = 2 << 11, 381 382 RK3328_GMAC_RMII_CLK_MASK = BIT(7), 383 RK3328_GMAC_RMII_CLK_2_5M = 0, 384 RK3328_GMAC_RMII_CLK_25M = BIT(7), 385 386 RK3328_GMAC_RMII_SPEED_MASK = BIT(2), 387 RK3328_GMAC_RMII_SPEED_10 = 0, 388 RK3328_GMAC_RMII_SPEED_100 = BIT(2), 389 }; 390 391 switch (priv->phydev->speed) { 392 case 10: 393 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 394 (RK3328_GMAC_RMII_CLK_2_5M | RK3328_GMAC_RMII_SPEED_10) : 395 RK3328_GMAC_CLK_SEL_2_5M; 396 break; 397 case 100: 398 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 399 (RK3328_GMAC_RMII_CLK_25M | RK3328_GMAC_RMII_SPEED_100) : 400 RK3328_GMAC_CLK_SEL_25M; 401 break; 402 case 1000: 403 clk = RK3328_GMAC_CLK_SEL_125M; 404 break; 405 default: 406 debug("Unknown phy speed: %d\n", priv->phydev->speed); 407 return -EINVAL; 408 } 409 410 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 411 rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1], 412 RK3328_GMAC_CLK_SEL_MASK | 413 RK3328_GMAC_RMII_CLK_MASK | 414 RK3328_GMAC_RMII_SPEED_MASK, 415 clk); 416 417 return 0; 418 } 419 420 static int rk3368_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 421 struct rockchip_eth_dev *dev) 422 { 423 struct dw_eth_dev *priv = &dev->dw; 424 struct rk3368_grf *grf; 425 int clk; 426 enum { 427 RK3368_GMAC_CLK_SEL_2_5M = 2 << 4, 428 RK3368_GMAC_CLK_SEL_25M = 3 << 4, 429 RK3368_GMAC_CLK_SEL_125M = 0 << 4, 430 RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4), 431 }; 432 433 switch (priv->phydev->speed) { 434 case 10: 435 clk = RK3368_GMAC_CLK_SEL_2_5M; 436 break; 437 case 100: 438 clk = RK3368_GMAC_CLK_SEL_25M; 439 break; 440 case 1000: 441 clk = RK3368_GMAC_CLK_SEL_125M; 442 break; 443 default: 444 debug("Unknown phy speed: %d\n", priv->phydev->speed); 445 return -EINVAL; 446 } 447 448 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 449 rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk); 450 451 return 0; 452 } 453 454 static int rk3399_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 455 struct rockchip_eth_dev *dev) 456 { 457 struct dw_eth_dev *priv = &dev->dw; 458 struct rk3399_grf_regs *grf; 459 int clk; 460 461 switch (priv->phydev->speed) { 462 case 10: 463 clk = RK3399_GMAC_CLK_SEL_2_5M; 464 break; 465 case 100: 466 clk = RK3399_GMAC_CLK_SEL_25M; 467 break; 468 case 1000: 469 clk = RK3399_GMAC_CLK_SEL_125M; 470 break; 471 default: 472 debug("Unknown phy speed: %d\n", priv->phydev->speed); 473 return -EINVAL; 474 } 475 476 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 477 rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk); 478 479 return 0; 480 } 481 482 static int rv1108_set_rmii_speed(struct gmac_rockchip_platdata *pdata, 483 struct rockchip_eth_dev *dev) 484 { 485 struct dw_eth_dev *priv = &dev->dw; 486 struct rv1108_grf *grf; 487 int clk, speed; 488 enum { 489 RV1108_GMAC_SPEED_MASK = BIT(2), 490 RV1108_GMAC_SPEED_10M = 0 << 2, 491 RV1108_GMAC_SPEED_100M = 1 << 2, 492 RV1108_GMAC_CLK_SEL_MASK = BIT(7), 493 RV1108_GMAC_CLK_SEL_2_5M = 0 << 7, 494 RV1108_GMAC_CLK_SEL_25M = 1 << 7, 495 }; 496 497 switch (priv->phydev->speed) { 498 case 10: 499 clk = RV1108_GMAC_CLK_SEL_2_5M; 500 speed = RV1108_GMAC_SPEED_10M; 501 break; 502 case 100: 503 clk = RV1108_GMAC_CLK_SEL_25M; 504 speed = RV1108_GMAC_SPEED_100M; 505 break; 506 default: 507 debug("Unknown phy speed: %d\n", priv->phydev->speed); 508 return -EINVAL; 509 } 510 511 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 512 rk_clrsetreg(&grf->gmac_con0, 513 RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK, 514 clk | speed); 515 516 return 0; 517 } 518 #else 519 static int rk3588_set_rgmii_speed(struct gmac_rockchip_platdata *pdata, 520 struct rockchip_eth_dev *dev) 521 { 522 struct eqos_priv *priv = &dev->eqos; 523 struct rk3588_php_grf *php_grf; 524 unsigned int div, div_mask; 525 526 enum { 527 RK3588_GMAC_CLK_RGMII_DIV_SHIFT = 2, 528 RK3588_GMAC_CLK_RGMII_DIV_MASK = GENMASK(3, 2), 529 RK3588_GMAC_CLK_RGMII_DIV1 = 0, 530 RK3588_GMAC_CLK_RGMII_DIV5 = GENMASK(3, 2), 531 RK3588_GMAC_CLK_RGMII_DIV50 = BIT(3), 532 RK3588_GMA_CLK_RMII_DIV2 = BIT(2), 533 RK3588_GMAC_CLK_RMII_DIV20 = 0, 534 }; 535 536 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 537 538 switch (priv->phy->speed) { 539 case 10: 540 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) 541 div = RK3588_GMAC_CLK_RMII_DIV20; 542 else 543 div = RK3588_GMAC_CLK_RGMII_DIV50; 544 break; 545 case 100: 546 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) 547 div = RK3588_GMA_CLK_RMII_DIV2; 548 else 549 div = RK3588_GMAC_CLK_RGMII_DIV5; 550 break; 551 case 1000: 552 if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII) 553 div = RK3588_GMAC_CLK_RGMII_DIV1; 554 else 555 return -EINVAL; 556 break; 557 default: 558 debug("Unknown phy speed: %d\n", priv->phy->speed); 559 return -EINVAL; 560 } 561 562 if (pdata->bus_id == 1) { 563 div <<= 5; 564 div_mask = RK3588_GMAC_CLK_RGMII_DIV_MASK << 5; 565 } 566 567 rk_clrsetreg(&php_grf->clk_con1, div_mask, div); 568 569 return 0; 570 } 571 572 static int rv1106_set_rmii_speed(struct gmac_rockchip_platdata *pdata, 573 struct rockchip_eth_dev *dev) 574 { 575 struct eqos_priv *priv = &dev->eqos; 576 struct rv1106_grf *grf; 577 unsigned int div; 578 579 enum { 580 RV1106_GMAC_CLK_RMII_DIV_SHIFT = 2, 581 RV1106_GMAC_CLK_RMII_DIV_MASK = GENMASK(3, 2), 582 RV1106_GMAC_CLK_RMII_DIV2 = BIT(2), 583 RV1106_GMAC_CLK_RMII_DIV20 = 0, 584 }; 585 586 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 587 588 switch (priv->phy->speed) { 589 case 10: 590 div = RV1106_GMAC_CLK_RMII_DIV20; 591 break; 592 case 100: 593 div = RV1106_GMAC_CLK_RMII_DIV2; 594 break; 595 default: 596 debug("Unknown phy speed: %d\n", priv->phy->speed); 597 return -EINVAL; 598 } 599 600 rk_clrsetreg(&grf->gmac_clk_con, RV1106_GMAC_CLK_RMII_DIV_MASK, div); 601 602 return 0; 603 } 604 605 static int rv1126_set_rgmii_speed(struct gmac_rockchip_platdata *pdata, 606 struct rockchip_eth_dev *dev) 607 { 608 struct eqos_priv *priv = &dev->eqos; 609 struct clk clk_speed; 610 int ret; 611 612 ret = clk_get_by_name(priv->phy->dev, "clk_mac_speed", 613 &clk_speed); 614 if (ret) { 615 printf("%s can't get clk_mac_speed clock (ret=%d):\n", 616 __func__, ret); 617 return ret; 618 } 619 620 switch ( priv->phy->speed) { 621 case 10: 622 ret = clk_set_rate(&clk_speed, 2500000); 623 if (ret) 624 return ret; 625 break; 626 case 100: 627 ret = clk_set_rate(&clk_speed, 25000000); 628 if (ret) 629 return ret; 630 break; 631 case 1000: 632 ret = clk_set_rate(&clk_speed, 125000000); 633 if (ret) 634 return ret; 635 break; 636 default: 637 debug("Unknown phy speed: %d\n", priv->phy->speed); 638 return -EINVAL; 639 } 640 641 return 0; 642 } 643 #endif 644 645 #ifndef CONFIG_DWC_ETH_QOS 646 static void px30_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 647 { 648 struct px30_grf *grf; 649 enum { 650 px30_GMAC_PHY_INTF_SEL_SHIFT = 4, 651 px30_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 6), 652 px30_GMAC_PHY_INTF_SEL_RMII = BIT(6), 653 }; 654 655 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 656 657 rk_clrsetreg(&grf->mac_con1, 658 px30_GMAC_PHY_INTF_SEL_MASK, 659 px30_GMAC_PHY_INTF_SEL_RMII); 660 } 661 662 static void rk1808_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 663 { 664 struct rk1808_grf *grf; 665 enum { 666 RK1808_GMAC_PHY_INTF_SEL_SHIFT = 4, 667 RK1808_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 668 RK1808_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 669 670 RK1808_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 671 RK1808_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 672 RK1808_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 673 674 RK1808_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 675 RK1808_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 676 RK1808_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 677 }; 678 enum { 679 RK1808_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 680 RK1808_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 7), 681 682 RK1808_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 683 RK1808_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 684 }; 685 686 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 687 rk_clrsetreg(&grf->mac_con1, 688 RK1808_GMAC_PHY_INTF_SEL_MASK | 689 RK1808_RXCLK_DLY_ENA_GMAC_MASK | 690 RK1808_TXCLK_DLY_ENA_GMAC_MASK, 691 RK1808_GMAC_PHY_INTF_SEL_RGMII | 692 RK1808_RXCLK_DLY_ENA_GMAC_ENABLE | 693 RK1808_TXCLK_DLY_ENA_GMAC_ENABLE); 694 695 rk_clrsetreg(&grf->mac_con0, 696 RK1808_CLK_RX_DL_CFG_GMAC_MASK | 697 RK1808_CLK_TX_DL_CFG_GMAC_MASK, 698 pdata->rx_delay << RK1808_CLK_RX_DL_CFG_GMAC_SHIFT | 699 pdata->tx_delay << RK1808_CLK_TX_DL_CFG_GMAC_SHIFT); 700 } 701 702 static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 703 { 704 struct rk322x_grf *grf; 705 enum { 706 RK3228_RMII_MODE_SHIFT = 10, 707 RK3228_RMII_MODE_MASK = BIT(10), 708 709 RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4, 710 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 711 RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 712 713 RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 714 RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 715 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 716 717 RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 718 RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 719 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 720 }; 721 enum { 722 RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 723 RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 724 725 RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 726 RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 727 }; 728 729 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 730 rk_clrsetreg(&grf->mac_con[1], 731 RK3228_RMII_MODE_MASK | 732 RK3228_GMAC_PHY_INTF_SEL_MASK | 733 RK3228_RXCLK_DLY_ENA_GMAC_MASK | 734 RK3228_TXCLK_DLY_ENA_GMAC_MASK, 735 RK3228_GMAC_PHY_INTF_SEL_RGMII | 736 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE | 737 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE); 738 739 rk_clrsetreg(&grf->mac_con[0], 740 RK3228_CLK_RX_DL_CFG_GMAC_MASK | 741 RK3228_CLK_TX_DL_CFG_GMAC_MASK, 742 pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT | 743 pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT); 744 } 745 746 static void rk3228_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 747 { 748 struct rk322x_grf *grf; 749 enum { 750 RK3228_GRF_CON_RMII_MODE_MASK = BIT(11), 751 RK3228_GRF_CON_RMII_MODE_SEL = BIT(11), 752 RK3228_RMII_MODE_MASK = BIT(10), 753 RK3228_RMII_MODE_SEL = BIT(10), 754 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 755 RK3228_GMAC_PHY_INTF_SEL_RMII = BIT(6), 756 }; 757 758 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 759 rk_clrsetreg(&grf->mac_con[1], 760 RK3228_GRF_CON_RMII_MODE_MASK | 761 RK3228_RMII_MODE_MASK | 762 RK3228_GMAC_PHY_INTF_SEL_MASK, 763 RK3228_GRF_CON_RMII_MODE_SEL | 764 RK3228_RMII_MODE_SEL | 765 RK3228_GMAC_PHY_INTF_SEL_RMII); 766 } 767 768 static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 769 { 770 struct rk3288_grf *grf; 771 772 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 773 rk_clrsetreg(&grf->soc_con1, 774 RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK, 775 RK3288_GMAC_PHY_INTF_SEL_RGMII); 776 777 rk_clrsetreg(&grf->soc_con3, 778 RK3288_RXCLK_DLY_ENA_GMAC_MASK | 779 RK3288_TXCLK_DLY_ENA_GMAC_MASK | 780 RK3288_CLK_RX_DL_CFG_GMAC_MASK | 781 RK3288_CLK_TX_DL_CFG_GMAC_MASK, 782 RK3288_RXCLK_DLY_ENA_GMAC_ENABLE | 783 RK3288_TXCLK_DLY_ENA_GMAC_ENABLE | 784 pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT | 785 pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT); 786 } 787 788 static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 789 { 790 struct rk3308_grf *grf; 791 enum { 792 RK3308_GMAC_PHY_INTF_SEL_SHIFT = 2, 793 RK3308_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 2), 794 RK3308_GMAC_PHY_INTF_SEL_RMII = BIT(4), 795 }; 796 797 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 798 799 rk_clrsetreg(&grf->mac_con0, 800 RK3308_GMAC_PHY_INTF_SEL_MASK, 801 RK3308_GMAC_PHY_INTF_SEL_RMII); 802 } 803 804 static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 805 { 806 struct rk3328_grf_regs *grf; 807 enum { 808 RK3328_RMII_MODE_SHIFT = 9, 809 RK3328_RMII_MODE_MASK = BIT(9), 810 811 RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4, 812 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 813 RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 814 815 RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 816 RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 817 RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 818 819 RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 820 RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 821 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 822 }; 823 enum { 824 RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 825 RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 826 827 RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 828 RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 829 }; 830 831 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 832 rk_clrsetreg(&grf->mac_con[1], 833 RK3328_RMII_MODE_MASK | 834 RK3328_GMAC_PHY_INTF_SEL_MASK | 835 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 836 RK3328_TXCLK_DLY_ENA_GMAC_MASK, 837 RK3328_GMAC_PHY_INTF_SEL_RGMII | 838 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 839 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE); 840 841 rk_clrsetreg(&grf->mac_con[0], 842 RK3328_CLK_RX_DL_CFG_GMAC_MASK | 843 RK3328_CLK_TX_DL_CFG_GMAC_MASK, 844 pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT | 845 pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT); 846 } 847 848 static void rk3328_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 849 { 850 struct rk3328_grf_regs *grf; 851 enum { 852 RK3328_RMII_MODE_MASK = BIT(9), 853 RK3328_RMII_MODE = BIT(9), 854 855 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 856 RK3328_GMAC_PHY_INTF_SEL_RMII = BIT(6), 857 }; 858 859 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 860 rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1], 861 RK3328_RMII_MODE_MASK | 862 RK3328_GMAC_PHY_INTF_SEL_MASK, 863 RK3328_GMAC_PHY_INTF_SEL_RMII | 864 RK3328_RMII_MODE); 865 } 866 867 static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 868 { 869 struct rk3368_grf *grf; 870 enum { 871 RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9, 872 RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9), 873 RK3368_RMII_MODE_MASK = BIT(6), 874 RK3368_RMII_MODE = BIT(6), 875 }; 876 enum { 877 RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15), 878 RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 879 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15), 880 RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7), 881 RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 882 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7), 883 RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8, 884 RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 885 RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0, 886 RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 887 }; 888 889 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 890 rk_clrsetreg(&grf->soc_con15, 891 RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK, 892 RK3368_GMAC_PHY_INTF_SEL_RGMII); 893 894 rk_clrsetreg(&grf->soc_con16, 895 RK3368_RXCLK_DLY_ENA_GMAC_MASK | 896 RK3368_TXCLK_DLY_ENA_GMAC_MASK | 897 RK3368_CLK_RX_DL_CFG_GMAC_MASK | 898 RK3368_CLK_TX_DL_CFG_GMAC_MASK, 899 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE | 900 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE | 901 pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT | 902 pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT); 903 } 904 905 static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 906 { 907 struct rk3399_grf_regs *grf; 908 909 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 910 911 rk_clrsetreg(&grf->soc_con5, 912 RK3399_GMAC_PHY_INTF_SEL_MASK, 913 RK3399_GMAC_PHY_INTF_SEL_RGMII); 914 915 rk_clrsetreg(&grf->soc_con6, 916 RK3399_RXCLK_DLY_ENA_GMAC_MASK | 917 RK3399_TXCLK_DLY_ENA_GMAC_MASK | 918 RK3399_CLK_RX_DL_CFG_GMAC_MASK | 919 RK3399_CLK_TX_DL_CFG_GMAC_MASK, 920 RK3399_RXCLK_DLY_ENA_GMAC_ENABLE | 921 RK3399_TXCLK_DLY_ENA_GMAC_ENABLE | 922 pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT | 923 pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT); 924 } 925 926 static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 927 { 928 struct rv1108_grf *grf; 929 930 enum { 931 RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 932 RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4, 933 }; 934 935 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 936 rk_clrsetreg(&grf->gmac_con0, 937 RV1108_GMAC_PHY_INTF_SEL_MASK, 938 RV1108_GMAC_PHY_INTF_SEL_RMII); 939 } 940 941 static void rk3228_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 942 { 943 struct rk322x_grf *grf; 944 enum { 945 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK = BIT(15), 946 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY = BIT(15), 947 }; 948 enum { 949 RK3228_MACPHY_CFG_CLK_50M_MASK = BIT(14), 950 RK3228_MACPHY_CFG_CLK_50M = BIT(14), 951 952 RK3228_MACPHY_RMII_MODE_MASK = GENMASK(7, 6), 953 RK3228_MACPHY_RMII_MODE = BIT(6), 954 955 RK3228_MACPHY_ENABLE_MASK = BIT(0), 956 RK3228_MACPHY_DISENABLE = 0, 957 RK3228_MACPHY_ENABLE = BIT(0), 958 }; 959 enum { 960 RK3228_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0), 961 RK3228_RK_GRF_CON2_MACPHY_ID = 0x1234, 962 }; 963 enum { 964 RK3228_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0), 965 RK3228_RK_GRF_CON3_MACPHY_ID = 0x35, 966 }; 967 968 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 969 rk_clrsetreg(&grf->con_iomux, 970 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK, 971 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY); 972 973 rk_clrsetreg(&grf->macphy_con[2], 974 RK3228_RK_GRF_CON2_MACPHY_ID_MASK, 975 RK3228_RK_GRF_CON2_MACPHY_ID); 976 977 rk_clrsetreg(&grf->macphy_con[3], 978 RK3228_RK_GRF_CON3_MACPHY_ID_MASK, 979 RK3228_RK_GRF_CON3_MACPHY_ID); 980 981 /* disabled before trying to reset it &*/ 982 rk_clrsetreg(&grf->macphy_con[0], 983 RK3228_MACPHY_CFG_CLK_50M_MASK | 984 RK3228_MACPHY_RMII_MODE_MASK | 985 RK3228_MACPHY_ENABLE_MASK, 986 RK3228_MACPHY_CFG_CLK_50M | 987 RK3228_MACPHY_RMII_MODE | 988 RK3228_MACPHY_DISENABLE); 989 990 reset_assert(&pdata->phy_reset); 991 udelay(10); 992 reset_deassert(&pdata->phy_reset); 993 udelay(10); 994 995 rk_clrsetreg(&grf->macphy_con[0], 996 RK3228_MACPHY_ENABLE_MASK, 997 RK3228_MACPHY_ENABLE); 998 udelay(30 * 1000); 999 } 1000 1001 static void rk3328_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 1002 { 1003 struct rk3328_grf_regs *grf; 1004 enum { 1005 RK3328_GRF_CON_RMII_MODE_MASK = BIT(9), 1006 RK3328_GRF_CON_RMII_MODE = BIT(9), 1007 }; 1008 enum { 1009 RK3328_MACPHY_CFG_CLK_50M_MASK = BIT(14), 1010 RK3328_MACPHY_CFG_CLK_50M = BIT(14), 1011 1012 RK3328_MACPHY_RMII_MODE_MASK = GENMASK(7, 6), 1013 RK3328_MACPHY_RMII_MODE = BIT(6), 1014 1015 RK3328_MACPHY_ENABLE_MASK = BIT(0), 1016 RK3328_MACPHY_DISENABLE = 0, 1017 RK3328_MACPHY_ENABLE = BIT(0), 1018 }; 1019 enum { 1020 RK3328_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0), 1021 RK3328_RK_GRF_CON2_MACPHY_ID = 0x1234, 1022 }; 1023 enum { 1024 RK3328_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0), 1025 RK3328_RK_GRF_CON3_MACPHY_ID = 0x35, 1026 }; 1027 1028 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1029 rk_clrsetreg(&grf->macphy_con[1], 1030 RK3328_GRF_CON_RMII_MODE_MASK, 1031 RK3328_GRF_CON_RMII_MODE); 1032 1033 rk_clrsetreg(&grf->macphy_con[2], 1034 RK3328_RK_GRF_CON2_MACPHY_ID_MASK, 1035 RK3328_RK_GRF_CON2_MACPHY_ID); 1036 1037 rk_clrsetreg(&grf->macphy_con[3], 1038 RK3328_RK_GRF_CON3_MACPHY_ID_MASK, 1039 RK3328_RK_GRF_CON3_MACPHY_ID); 1040 1041 /* disabled before trying to reset it &*/ 1042 rk_clrsetreg(&grf->macphy_con[0], 1043 RK3328_MACPHY_CFG_CLK_50M_MASK | 1044 RK3328_MACPHY_RMII_MODE_MASK | 1045 RK3328_MACPHY_ENABLE_MASK, 1046 RK3328_MACPHY_CFG_CLK_50M | 1047 RK3328_MACPHY_RMII_MODE | 1048 RK3328_MACPHY_DISENABLE); 1049 1050 reset_assert(&pdata->phy_reset); 1051 udelay(10); 1052 reset_deassert(&pdata->phy_reset); 1053 udelay(10); 1054 1055 rk_clrsetreg(&grf->macphy_con[0], 1056 RK3328_MACPHY_ENABLE_MASK, 1057 RK3328_MACPHY_ENABLE); 1058 udelay(30 * 1000); 1059 } 1060 1061 #else 1062 static void rk3568_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1063 { 1064 struct rk3568_grf *grf; 1065 void *con1; 1066 1067 enum { 1068 RK3568_GMAC_PHY_INTF_SEL_SHIFT = 4, 1069 RK3568_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1070 RK3568_GMAC_PHY_INTF_SEL_RMII = BIT(6), 1071 }; 1072 1073 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1074 1075 if (pdata->bus_id == 1) 1076 con1 = &grf->mac1_con1; 1077 else 1078 con1 = &grf->mac0_con1; 1079 1080 rk_clrsetreg(con1, 1081 RK3568_GMAC_PHY_INTF_SEL_MASK, 1082 RK3568_GMAC_PHY_INTF_SEL_RMII); 1083 } 1084 1085 static void rk3568_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1086 { 1087 struct rk3568_grf *grf; 1088 void *con0, *con1; 1089 1090 enum { 1091 RK3568_GMAC_PHY_INTF_SEL_SHIFT = 4, 1092 RK3568_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1093 RK3568_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 1094 1095 RK3568_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 1096 RK3568_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 1097 RK3568_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 1098 1099 RK3568_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 1100 RK3568_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 1101 RK3568_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 1102 }; 1103 1104 enum { 1105 RK3568_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1106 RK3568_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 8), 1107 1108 RK3568_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1109 RK3568_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 1110 }; 1111 1112 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1113 1114 if (pdata->bus_id == 1) { 1115 con0 = &grf->mac1_con0; 1116 con1 = &grf->mac1_con1; 1117 } else { 1118 con0 = &grf->mac0_con0; 1119 con1 = &grf->mac0_con1; 1120 } 1121 1122 rk_clrsetreg(con0, 1123 RK3568_CLK_RX_DL_CFG_GMAC_MASK | 1124 RK3568_CLK_TX_DL_CFG_GMAC_MASK, 1125 pdata->rx_delay << RK3568_CLK_RX_DL_CFG_GMAC_SHIFT | 1126 pdata->tx_delay << RK3568_CLK_TX_DL_CFG_GMAC_SHIFT); 1127 1128 rk_clrsetreg(con1, 1129 RK3568_TXCLK_DLY_ENA_GMAC_MASK | 1130 RK3568_RXCLK_DLY_ENA_GMAC_MASK | 1131 RK3568_GMAC_PHY_INTF_SEL_MASK, 1132 RK3568_TXCLK_DLY_ENA_GMAC_ENABLE | 1133 RK3568_RXCLK_DLY_ENA_GMAC_ENABLE | 1134 RK3568_GMAC_PHY_INTF_SEL_RGMII); 1135 } 1136 1137 static void rk3588_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1138 { 1139 unsigned int intf_sel, intf_sel_mask; 1140 unsigned int clk_mode, clk_mode_mask; 1141 struct rk3588_php_grf *php_grf; 1142 1143 enum { 1144 RK3588_GMAC_PHY_INTF_SEL_SHIFT = 3, 1145 RK3588_GMAC_PHY_INTF_SEL_MASK = GENMASK(5, 3), 1146 RK3588_GMAC_PHY_INTF_SEL_RMII = BIT(5), 1147 }; 1148 1149 enum { 1150 RK3588_GMAC_CLK_RMII_MODE_SHIFT = 0x0, 1151 RK3588_GMAC_CLK_RMII_MODE_MASK = BIT(0), 1152 RK3588_GMAC_CLK_RMII_MODE = 0x1, 1153 }; 1154 1155 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 1156 1157 if (pdata->bus_id == 1) { 1158 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RMII << 6; 1159 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK << 6; 1160 clk_mode = RK3588_GMAC_CLK_RMII_MODE << 5; 1161 clk_mode_mask = RK3588_GMAC_CLK_RMII_MODE_MASK << 5; 1162 } else { 1163 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RMII; 1164 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK; 1165 clk_mode = RK3588_GMAC_CLK_RMII_MODE; 1166 clk_mode_mask = RK3588_GMAC_CLK_RMII_MODE_MASK; 1167 } 1168 1169 rk_clrsetreg(&php_grf->gmac_con0, intf_sel_mask, intf_sel); 1170 rk_clrsetreg(&php_grf->clk_con1, clk_mode_mask, clk_mode); 1171 } 1172 1173 static void rk3588_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1174 { 1175 unsigned int rx_enable, rx_enable_mask, tx_enable, tx_enable_mask; 1176 unsigned int intf_sel, intf_sel_mask; 1177 unsigned int clk_mode, clk_mode_mask; 1178 unsigned int rx_delay; 1179 struct rk3588_php_grf *php_grf; 1180 struct rk3588_sys_grf *grf; 1181 void *offset_con; 1182 1183 enum { 1184 RK3588_GMAC_PHY_INTF_SEL_SHIFT = 3, 1185 RK3588_GMAC_PHY_INTF_SEL_MASK = GENMASK(5, 3), 1186 RK3588_GMAC_PHY_INTF_SEL_RGMII = BIT(3), 1187 1188 RK3588_RXCLK_DLY_ENA_GMAC_MASK = BIT(3), 1189 RK3588_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 1190 RK3588_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(3), 1191 1192 RK3588_TXCLK_DLY_ENA_GMAC_MASK = BIT(2), 1193 RK3588_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 1194 RK3588_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(2), 1195 }; 1196 1197 enum { 1198 RK3588_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1199 RK3588_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 8), 1200 1201 RK3588_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1202 RK3588_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 1203 }; 1204 1205 enum { 1206 RK3588_GMAC_CLK_RGMII_MODE_SHIFT = 0x0, 1207 RK3588_GMAC_CLK_RGMII_MODE_MASK = BIT(0), 1208 RK3588_GMAC_CLK_RGMII_MODE = 0x0, 1209 }; 1210 1211 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1212 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 1213 1214 if (pdata->rx_delay < 0) { 1215 rx_enable = RK3588_RXCLK_DLY_ENA_GMAC_DISABLE; 1216 rx_delay = 0; 1217 } else { 1218 rx_enable = RK3588_RXCLK_DLY_ENA_GMAC_ENABLE; 1219 rx_delay = pdata->rx_delay << RK3588_CLK_RX_DL_CFG_GMAC_SHIFT; 1220 } 1221 1222 if (pdata->bus_id == 1) { 1223 offset_con = &grf->soc_con9; 1224 rx_enable = rx_delay << 2; 1225 rx_enable_mask = RK3588_RXCLK_DLY_ENA_GMAC_MASK << 2; 1226 tx_enable = RK3588_TXCLK_DLY_ENA_GMAC_ENABLE << 2; 1227 tx_enable_mask = RK3588_TXCLK_DLY_ENA_GMAC_MASK << 2; 1228 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RGMII << 6; 1229 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK << 6; 1230 clk_mode = RK3588_GMAC_CLK_RGMII_MODE << 5; 1231 clk_mode_mask = RK3588_GMAC_CLK_RGMII_MODE_MASK << 5; 1232 } else { 1233 offset_con = &grf->soc_con8; 1234 rx_enable_mask = RK3588_RXCLK_DLY_ENA_GMAC_MASK; 1235 tx_enable = RK3588_TXCLK_DLY_ENA_GMAC_ENABLE; 1236 tx_enable_mask = RK3588_TXCLK_DLY_ENA_GMAC_MASK; 1237 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RGMII; 1238 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK; 1239 clk_mode = RK3588_GMAC_CLK_RGMII_MODE; 1240 clk_mode_mask = RK3588_GMAC_CLK_RGMII_MODE_MASK; 1241 } 1242 1243 rk_clrsetreg(offset_con, 1244 RK3588_CLK_TX_DL_CFG_GMAC_MASK | 1245 RK3588_CLK_RX_DL_CFG_GMAC_MASK, 1246 pdata->tx_delay << RK3588_CLK_TX_DL_CFG_GMAC_SHIFT | 1247 rx_delay); 1248 1249 rk_clrsetreg(&grf->soc_con7, tx_enable_mask | rx_enable_mask, 1250 tx_enable | rx_enable); 1251 1252 rk_clrsetreg(&php_grf->gmac_con0, intf_sel_mask, intf_sel); 1253 rk_clrsetreg(&php_grf->clk_con1, clk_mode_mask, clk_mode); 1254 } 1255 1256 static void rv1106_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 1257 { 1258 struct rv1106_grf *grf; 1259 unsigned char bgs[1] = {0}; 1260 1261 enum { 1262 RV1106_VOGRF_GMAC_CLK_RMII_MODE_MASK = BIT(0), 1263 RV1106_VOGRF_GMAC_CLK_RMII_MODE = BIT(0), 1264 }; 1265 1266 enum { 1267 RV1106_MACPHY_ENABLE_MASK = BIT(1), 1268 RV1106_MACPHY_DISENABLE = BIT(1), 1269 RV1106_MACPHY_ENABLE = 0, 1270 RV1106_MACPHY_XMII_SEL_MASK = GENMASK(6, 5), 1271 RV1106_MACPHY_XMII_SEL = BIT(6), 1272 RV1106_MACPHY_24M_CLK_SEL_MASK = GENMASK(9, 7), 1273 RV1106_MACPHY_24M_CLK_SEL_24M = (BIT(8) | BIT(9)), 1274 RV1106_MACPHY_PHY_ID_MASK = GENMASK(14, 10), 1275 RV1106_MACPHY_PHY_ID = BIT(11), 1276 }; 1277 1278 enum { 1279 RV1106_MACPHY_BGS_MASK = GENMASK(3, 0), 1280 RV1106_MACPHY_BGS = BIT(2), 1281 }; 1282 1283 #if defined(CONFIG_ROCKCHIP_EFUSE) || defined(CONFIG_ROCKCHIP_OTP) 1284 struct udevice *dev; 1285 u32 regs[2] = {0}; 1286 ofnode node; 1287 int ret = 0; 1288 1289 /* retrieve the device */ 1290 if (IS_ENABLED(CONFIG_ROCKCHIP_EFUSE)) 1291 ret = uclass_get_device_by_driver(UCLASS_MISC, 1292 DM_GET_DRIVER(rockchip_efuse), 1293 &dev); 1294 else 1295 ret = uclass_get_device_by_driver(UCLASS_MISC, 1296 DM_GET_DRIVER(rockchip_otp), 1297 &dev); 1298 if (!ret) { 1299 node = dev_read_subnode(dev, "macphy-bgs"); 1300 if (ofnode_valid(node)) { 1301 if (!ofnode_read_u32_array(node, "reg", regs, 2)) { 1302 /* read the bgs from the efuses */ 1303 ret = misc_read(dev, regs[0], &bgs, 1); 1304 if (ret) { 1305 printf("read bgs from efuse/otp failed, ret=%d\n", 1306 ret); 1307 bgs[0] = 0; 1308 } 1309 } 1310 } 1311 } 1312 #endif 1313 1314 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1315 1316 reset_assert(&pdata->phy_reset); 1317 udelay(20); 1318 rk_clrsetreg(&grf->macphy_con0, 1319 RV1106_MACPHY_ENABLE_MASK | 1320 RV1106_MACPHY_XMII_SEL_MASK | 1321 RV1106_MACPHY_24M_CLK_SEL_MASK | 1322 RV1106_MACPHY_PHY_ID_MASK, 1323 RV1106_MACPHY_ENABLE | 1324 RV1106_MACPHY_XMII_SEL | 1325 RV1106_MACPHY_24M_CLK_SEL_24M | 1326 RV1106_MACPHY_PHY_ID); 1327 1328 rk_clrsetreg(&grf->macphy_con1, 1329 RV1106_MACPHY_BGS_MASK, 1330 bgs[0]); 1331 udelay(20); 1332 reset_deassert(&pdata->phy_reset); 1333 udelay(30 * 1000); 1334 } 1335 1336 static void rv1106_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1337 { 1338 struct rv1106_grf *grf; 1339 enum { 1340 RV1106_VOGRF_GMAC_CLK_RMII_MODE_MASK = BIT(0), 1341 RV1106_VOGRF_GMAC_CLK_RMII_MODE = BIT(0), 1342 }; 1343 1344 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1345 rk_clrsetreg(&grf->gmac_clk_con, 1346 RV1106_VOGRF_GMAC_CLK_RMII_MODE_MASK, 1347 RV1106_VOGRF_GMAC_CLK_RMII_MODE); 1348 }; 1349 1350 static void rv1126_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1351 { 1352 struct rv1126_grf *grf; 1353 1354 enum { 1355 RV1126_GMAC_PHY_INTF_SEL_SHIFT = 4, 1356 RV1126_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1357 RV1126_GMAC_PHY_INTF_SEL_RMII = BIT(6), 1358 }; 1359 1360 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1361 1362 rk_clrsetreg(&grf->mac_con0, 1363 RV1126_GMAC_PHY_INTF_SEL_MASK, 1364 RV1126_GMAC_PHY_INTF_SEL_RMII); 1365 } 1366 1367 static void rv1126_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1368 { 1369 struct rv1126_grf *grf; 1370 1371 enum { 1372 RV1126_GMAC_PHY_INTF_SEL_SHIFT = 4, 1373 RV1126_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1374 RV1126_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 1375 1376 RV1126_RXCLK_M1_DLY_ENA_GMAC_MASK = BIT(3), 1377 RV1126_RXCLK_M1_DLY_ENA_GMAC_DISABLE = 0, 1378 RV1126_RXCLK_M1_DLY_ENA_GMAC_ENABLE = BIT(3), 1379 1380 RV1126_TXCLK_M1_DLY_ENA_GMAC_MASK = BIT(2), 1381 RV1126_TXCLK_M1_DLY_ENA_GMAC_DISABLE = 0, 1382 RV1126_TXCLK_M1_DLY_ENA_GMAC_ENABLE = BIT(2), 1383 1384 RV1126_RXCLK_M0_DLY_ENA_GMAC_MASK = BIT(1), 1385 RV1126_RXCLK_M0_DLY_ENA_GMAC_DISABLE = 0, 1386 RV1126_RXCLK_M0_DLY_ENA_GMAC_ENABLE = BIT(1), 1387 1388 RV1126_TXCLK_M0_DLY_ENA_GMAC_MASK = BIT(0), 1389 RV1126_TXCLK_M0_DLY_ENA_GMAC_DISABLE = 0, 1390 RV1126_TXCLK_M0_DLY_ENA_GMAC_ENABLE = BIT(0), 1391 }; 1392 enum { 1393 RV1126_M0_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1394 RV1126_M0_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 1395 1396 RV1126_M0_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1397 RV1126_M0_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 1398 }; 1399 enum { 1400 RV1126_M1_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1401 RV1126_M1_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 1402 1403 RV1126_M1_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1404 RV1126_M1_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 1405 }; 1406 1407 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1408 1409 rk_clrsetreg(&grf->mac_con0, 1410 RV1126_TXCLK_M0_DLY_ENA_GMAC_MASK | 1411 RV1126_RXCLK_M0_DLY_ENA_GMAC_MASK | 1412 RV1126_TXCLK_M1_DLY_ENA_GMAC_MASK | 1413 RV1126_RXCLK_M1_DLY_ENA_GMAC_MASK | 1414 RV1126_GMAC_PHY_INTF_SEL_MASK, 1415 RV1126_TXCLK_M0_DLY_ENA_GMAC_ENABLE | 1416 RV1126_RXCLK_M0_DLY_ENA_GMAC_ENABLE | 1417 RV1126_TXCLK_M1_DLY_ENA_GMAC_ENABLE | 1418 RV1126_RXCLK_M1_DLY_ENA_GMAC_ENABLE | 1419 RV1126_GMAC_PHY_INTF_SEL_RGMII); 1420 1421 rk_clrsetreg(&grf->mac_con1, 1422 RV1126_M0_CLK_RX_DL_CFG_GMAC_MASK | 1423 RV1126_M0_CLK_TX_DL_CFG_GMAC_MASK, 1424 pdata->rx_delay << RV1126_M0_CLK_RX_DL_CFG_GMAC_SHIFT | 1425 pdata->tx_delay << RV1126_M0_CLK_TX_DL_CFG_GMAC_SHIFT); 1426 1427 rk_clrsetreg(&grf->mac_con2, 1428 RV1126_M1_CLK_RX_DL_CFG_GMAC_MASK | 1429 RV1126_M1_CLK_TX_DL_CFG_GMAC_MASK, 1430 pdata->rx_delay << RV1126_M1_CLK_RX_DL_CFG_GMAC_SHIFT | 1431 pdata->tx_delay << RV1126_M1_CLK_TX_DL_CFG_GMAC_SHIFT); 1432 } 1433 #endif 1434 1435 #ifdef CONFIG_DWC_ETH_QOS 1436 static void rk3588_set_clock_selection(struct gmac_rockchip_platdata *pdata) 1437 { 1438 struct rk3588_php_grf *php_grf; 1439 unsigned int val, mask; 1440 1441 enum { 1442 RK3588_GMAC_CLK_SELET_SHIFT = 0x4, 1443 RK3588_GMAC_CLK_SELET_MASK = BIT(4), 1444 RK3588_GMAC_CLK_SELET_CRU = BIT(4), 1445 RK3588_GMAC_CLK_SELET_IO = 0, 1446 }; 1447 1448 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 1449 val = pdata->clock_input ? RK3588_GMAC_CLK_SELET_IO : 1450 RK3588_GMAC_CLK_SELET_CRU; 1451 mask = RK3588_GMAC_CLK_SELET_MASK; 1452 1453 if (pdata->bus_id == 1) { 1454 val <<= 5; 1455 mask <<= 5; 1456 } 1457 1458 rk_clrsetreg(&php_grf->clk_con1, mask, val); 1459 } 1460 #endif 1461 1462 static int gmac_rockchip_probe(struct udevice *dev) 1463 { 1464 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 1465 struct rk_gmac_ops *ops = 1466 (struct rk_gmac_ops *)dev_get_driver_data(dev); 1467 #ifdef CONFIG_DWC_ETH_QOS 1468 struct eqos_config *config; 1469 #else 1470 struct dw_eth_pdata *dw_pdata; 1471 #endif 1472 struct eth_pdata *eth_pdata; 1473 struct clk clk; 1474 ulong rate; 1475 int ret; 1476 1477 #ifdef CONFIG_DWC_ETH_QOS 1478 eth_pdata = &pdata->eth_pdata; 1479 config = (struct eqos_config *)&ops->config; 1480 memcpy(config, &eqos_rockchip_config, sizeof(struct eqos_config)); 1481 eth_pdata->phy_interface = config->ops->eqos_get_interface(dev); 1482 #else 1483 dw_pdata = &pdata->dw_eth_pdata; 1484 eth_pdata = &dw_pdata->eth_pdata; 1485 #endif 1486 pdata->bus_id = dev->seq; 1487 1488 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 1489 ret = clk_set_defaults(dev); 1490 if (ret) 1491 debug("%s clk_set_defaults failed %d\n", __func__, ret); 1492 1493 ret = clk_get_by_index(dev, 0, &clk); 1494 if (ret) 1495 return ret; 1496 1497 pdata->phy_interface = eth_pdata->phy_interface; 1498 1499 if (ops->set_clock_selection) 1500 ops->set_clock_selection(pdata); 1501 1502 if (pdata->integrated_phy && ops->integrated_phy_powerup) 1503 ops->integrated_phy_powerup(pdata); 1504 1505 switch (eth_pdata->phy_interface) { 1506 case PHY_INTERFACE_MODE_RGMII: 1507 case PHY_INTERFACE_MODE_RGMII_RXID: 1508 /* 1509 * If the gmac clock is from internal pll, need to set and 1510 * check the return value for gmac clock at RGMII mode. If 1511 * the gmac clock is from external source, the clock rate 1512 * is not set, because of it is bypassed. 1513 */ 1514 if (!pdata->clock_input) { 1515 rate = clk_set_rate(&clk, 125000000); 1516 if (rate != 125000000) 1517 return -EINVAL; 1518 } 1519 1520 if (eth_pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) 1521 pdata->rx_delay = -1; 1522 1523 /* Set to RGMII mode */ 1524 if (ops->set_to_rgmii) 1525 ops->set_to_rgmii(pdata); 1526 else 1527 return -EPERM; 1528 1529 break; 1530 case PHY_INTERFACE_MODE_RMII: 1531 /* The commet is the same as RGMII mode */ 1532 if (!pdata->clock_input) { 1533 rate = clk_set_rate(&clk, 50000000); 1534 if (rate != 50000000) 1535 return -EINVAL; 1536 } 1537 1538 /* Set to RMII mode */ 1539 if (ops->set_to_rmii) 1540 ops->set_to_rmii(pdata); 1541 1542 break; 1543 default: 1544 debug("NO interface defined!\n"); 1545 return -ENXIO; 1546 } 1547 1548 #ifdef CONFIG_DWC_ETH_QOS 1549 return eqos_probe(dev); 1550 #else 1551 return designware_eth_probe(dev); 1552 #endif 1553 } 1554 1555 static int gmac_rockchip_eth_write_hwaddr(struct udevice *dev) 1556 { 1557 #if defined(CONFIG_DWC_ETH_QOS) 1558 return eqos_write_hwaddr(dev); 1559 #else 1560 return designware_eth_write_hwaddr(dev); 1561 #endif 1562 } 1563 1564 static int gmac_rockchip_eth_free_pkt(struct udevice *dev, uchar *packet, 1565 int length) 1566 { 1567 #ifdef CONFIG_DWC_ETH_QOS 1568 return eqos_free_pkt(dev, packet, length); 1569 #else 1570 return designware_eth_free_pkt(dev, packet, length); 1571 #endif 1572 } 1573 1574 static int gmac_rockchip_eth_send(struct udevice *dev, void *packet, 1575 int length) 1576 { 1577 #ifdef CONFIG_DWC_ETH_QOS 1578 return eqos_send(dev, packet, length); 1579 #else 1580 return designware_eth_send(dev, packet, length); 1581 #endif 1582 } 1583 1584 static int gmac_rockchip_eth_recv(struct udevice *dev, int flags, 1585 uchar **packetp) 1586 { 1587 #ifdef CONFIG_DWC_ETH_QOS 1588 return eqos_recv(dev, flags, packetp); 1589 #else 1590 return designware_eth_recv(dev, flags, packetp); 1591 #endif 1592 } 1593 1594 static int gmac_rockchip_eth_start(struct udevice *dev) 1595 { 1596 struct rockchip_eth_dev *priv = dev_get_priv(dev); 1597 struct rk_gmac_ops *ops = 1598 (struct rk_gmac_ops *)dev_get_driver_data(dev); 1599 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 1600 #ifndef CONFIG_DWC_ETH_QOS 1601 struct dw_eth_pdata *dw_pdata; 1602 struct eth_pdata *eth_pdata; 1603 #endif 1604 int ret; 1605 1606 #ifdef CONFIG_DWC_ETH_QOS 1607 ret = eqos_init(dev); 1608 #else 1609 dw_pdata = &pdata->dw_eth_pdata; 1610 eth_pdata = &dw_pdata->eth_pdata; 1611 ret = designware_eth_init((struct dw_eth_dev *)priv, 1612 eth_pdata->enetaddr); 1613 #endif 1614 if (ret) 1615 return ret; 1616 ret = ops->fix_mac_speed(pdata, priv); 1617 if (ret) 1618 return ret; 1619 1620 #ifdef CONFIG_DWC_ETH_QOS 1621 eqos_enable(dev); 1622 #else 1623 ret = designware_eth_enable((struct dw_eth_dev *)priv); 1624 if (ret) 1625 return ret; 1626 #endif 1627 1628 return 0; 1629 } 1630 1631 static void gmac_rockchip_eth_stop(struct udevice *dev) 1632 { 1633 #ifdef CONFIG_DWC_ETH_QOS 1634 eqos_stop(dev); 1635 #else 1636 designware_eth_stop(dev); 1637 #endif 1638 } 1639 1640 const struct eth_ops gmac_rockchip_eth_ops = { 1641 .start = gmac_rockchip_eth_start, 1642 .send = gmac_rockchip_eth_send, 1643 .recv = gmac_rockchip_eth_recv, 1644 .free_pkt = gmac_rockchip_eth_free_pkt, 1645 .stop = gmac_rockchip_eth_stop, 1646 .write_hwaddr = gmac_rockchip_eth_write_hwaddr, 1647 }; 1648 1649 #ifndef CONFIG_DWC_ETH_QOS 1650 const struct rk_gmac_ops px30_gmac_ops = { 1651 .fix_mac_speed = px30_gmac_fix_mac_speed, 1652 .set_to_rmii = px30_gmac_set_to_rmii, 1653 }; 1654 1655 const struct rk_gmac_ops rk1808_gmac_ops = { 1656 .fix_mac_speed = rk1808_gmac_fix_mac_speed, 1657 .set_to_rgmii = rk1808_gmac_set_to_rgmii, 1658 }; 1659 1660 const struct rk_gmac_ops rk3228_gmac_ops = { 1661 .fix_mac_speed = rk3228_gmac_fix_mac_speed, 1662 .set_to_rmii = rk3228_gmac_set_to_rmii, 1663 .set_to_rgmii = rk3228_gmac_set_to_rgmii, 1664 .integrated_phy_powerup = rk3228_gmac_integrated_phy_powerup, 1665 }; 1666 1667 const struct rk_gmac_ops rk3288_gmac_ops = { 1668 .fix_mac_speed = rk3288_gmac_fix_mac_speed, 1669 .set_to_rgmii = rk3288_gmac_set_to_rgmii, 1670 }; 1671 1672 const struct rk_gmac_ops rk3308_gmac_ops = { 1673 .fix_mac_speed = rk3308_gmac_fix_mac_speed, 1674 .set_to_rmii = rk3308_gmac_set_to_rmii, 1675 }; 1676 1677 const struct rk_gmac_ops rk3328_gmac_ops = { 1678 .fix_mac_speed = rk3328_gmac_fix_mac_speed, 1679 .set_to_rmii = rk3328_gmac_set_to_rmii, 1680 .set_to_rgmii = rk3328_gmac_set_to_rgmii, 1681 .integrated_phy_powerup = rk3328_gmac_integrated_phy_powerup, 1682 }; 1683 1684 const struct rk_gmac_ops rk3368_gmac_ops = { 1685 .fix_mac_speed = rk3368_gmac_fix_mac_speed, 1686 .set_to_rgmii = rk3368_gmac_set_to_rgmii, 1687 }; 1688 1689 const struct rk_gmac_ops rk3399_gmac_ops = { 1690 .fix_mac_speed = rk3399_gmac_fix_mac_speed, 1691 .set_to_rgmii = rk3399_gmac_set_to_rgmii, 1692 }; 1693 1694 const struct rk_gmac_ops rv1108_gmac_ops = { 1695 .fix_mac_speed = rv1108_set_rmii_speed, 1696 .set_to_rmii = rv1108_gmac_set_to_rmii, 1697 }; 1698 #else 1699 const struct rk_gmac_ops rk3568_gmac_ops = { 1700 .fix_mac_speed = rv1126_set_rgmii_speed, 1701 .set_to_rgmii = rk3568_set_to_rgmii, 1702 .set_to_rmii = rk3568_set_to_rmii, 1703 }; 1704 1705 const struct rk_gmac_ops rk3588_gmac_ops = { 1706 .fix_mac_speed = rk3588_set_rgmii_speed, 1707 .set_to_rgmii = rk3588_set_to_rgmii, 1708 .set_to_rmii = rk3588_set_to_rmii, 1709 .set_clock_selection = rk3588_set_clock_selection, 1710 }; 1711 1712 const struct rk_gmac_ops rv1106_gmac_ops = { 1713 .fix_mac_speed = rv1106_set_rmii_speed, 1714 .set_to_rmii = rv1106_set_to_rmii, 1715 .integrated_phy_powerup = rv1106_gmac_integrated_phy_powerup, 1716 }; 1717 1718 const struct rk_gmac_ops rv1126_gmac_ops = { 1719 .fix_mac_speed = rv1126_set_rgmii_speed, 1720 .set_to_rgmii = rv1126_set_to_rgmii, 1721 .set_to_rmii = rv1126_set_to_rmii, 1722 }; 1723 #endif 1724 1725 static const struct udevice_id rockchip_gmac_ids[] = { 1726 #ifndef CONFIG_DWC_ETH_QOS 1727 #ifdef CONFIG_ROCKCHIP_PX30 1728 { .compatible = "rockchip,px30-gmac", 1729 .data = (ulong)&px30_gmac_ops }, 1730 #endif 1731 1732 #ifdef CONFIG_ROCKCHIP_RK1808 1733 { .compatible = "rockchip,rk1808-gmac", 1734 .data = (ulong)&rk1808_gmac_ops }, 1735 #endif 1736 1737 #ifdef CONFIG_ROCKCHIP_RK3228 1738 { .compatible = "rockchip,rk3228-gmac", 1739 .data = (ulong)&rk3228_gmac_ops }, 1740 #endif 1741 1742 #ifdef CONFIG_ROCKCHIP_RK3288 1743 { .compatible = "rockchip,rk3288-gmac", 1744 .data = (ulong)&rk3288_gmac_ops }, 1745 #endif 1746 1747 #ifdef CONFIG_ROCKCHIP_RK3308 1748 { .compatible = "rockchip,rk3308-mac", 1749 .data = (ulong)&rk3308_gmac_ops }, 1750 #endif 1751 1752 #ifdef CONFIG_ROCKCHIP_RK3328 1753 { .compatible = "rockchip,rk3328-gmac", 1754 .data = (ulong)&rk3328_gmac_ops }, 1755 #endif 1756 1757 #ifdef CONFIG_ROCKCHIP_RK3368 1758 { .compatible = "rockchip,rk3368-gmac", 1759 .data = (ulong)&rk3368_gmac_ops }, 1760 #endif 1761 1762 #ifdef CONFIG_ROCKCHIP_RK3399 1763 { .compatible = "rockchip,rk3399-gmac", 1764 .data = (ulong)&rk3399_gmac_ops }, 1765 #endif 1766 1767 #ifdef CONFIG_ROCKCHIP_RV1108 1768 { .compatible = "rockchip,rv1108-gmac", 1769 .data = (ulong)&rv1108_gmac_ops }, 1770 #endif 1771 #else 1772 #ifdef CONFIG_ROCKCHIP_RK3568 1773 { .compatible = "rockchip,rk3568-gmac", 1774 .data = (ulong)&rk3568_gmac_ops }, 1775 #endif 1776 1777 #ifdef CONFIG_ROCKCHIP_RK3588 1778 { .compatible = "rockchip,rk3588-gmac", 1779 .data = (ulong)&rk3588_gmac_ops }, 1780 #endif 1781 1782 #ifdef CONFIG_ROCKCHIP_RV1106 1783 { .compatible = "rockchip,rv1106-gmac", 1784 .data = (ulong)&rv1106_gmac_ops }, 1785 #endif 1786 1787 #ifdef CONFIG_ROCKCHIP_RV1126 1788 { .compatible = "rockchip,rv1126-gmac", 1789 .data = (ulong)&rv1126_gmac_ops }, 1790 #endif 1791 #endif 1792 { } 1793 }; 1794 1795 U_BOOT_DRIVER(eth_gmac_rockchip) = { 1796 .name = "gmac_rockchip", 1797 .id = UCLASS_ETH, 1798 .of_match = rockchip_gmac_ids, 1799 .ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata, 1800 .probe = gmac_rockchip_probe, 1801 .ops = &gmac_rockchip_eth_ops, 1802 .priv_auto_alloc_size = sizeof(struct rockchip_eth_dev), 1803 .platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata), 1804 .flags = DM_FLAG_ALLOC_PRIV_DMA, 1805 }; 1806