1 /* 2 * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Rockchip GMAC ethernet IP driver for U-Boot 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <clk.h> 12 #include <phy.h> 13 #include <reset.h> 14 #include <syscon.h> 15 #include <asm/io.h> 16 #include <asm/arch/periph.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/hardware.h> 19 #ifdef CONFIG_DWC_ETH_QOS 20 #include <asm/arch/grf_rk3568.h> 21 #include <asm/arch/grf_rk3588.h> 22 #include <asm/arch/grf_rv1126.h> 23 #include "dwc_eth_qos.h" 24 #else 25 #include <asm/arch/grf_px30.h> 26 #include <asm/arch/grf_rk1808.h> 27 #include <asm/arch/grf_rk322x.h> 28 #include <asm/arch/grf_rk3288.h> 29 #include <asm/arch/grf_rk3308.h> 30 #include <asm/arch/grf_rk3328.h> 31 #include <asm/arch/grf_rk3368.h> 32 #include <asm/arch/grf_rk3399.h> 33 #include <asm/arch/grf_rv1108.h> 34 #include "designware.h" 35 #include <dt-bindings/clock/rk3288-cru.h> 36 #endif 37 #include <dm/pinctrl.h> 38 #include <dm/of_access.h> 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 struct rockchip_eth_dev { 43 #ifdef CONFIG_DWC_ETH_QOS 44 struct eqos_priv eqos; 45 #else 46 struct dw_eth_dev dw; 47 #endif 48 int phy_interface; 49 }; 50 51 /* 52 * Platform data for the gmac 53 * 54 * dw_eth_pdata: Required platform data for designware driver (must be first) 55 */ 56 struct gmac_rockchip_platdata { 57 #ifndef CONFIG_DWC_ETH_QOS 58 struct dw_eth_pdata dw_eth_pdata; 59 #else 60 struct eth_pdata eth_pdata; 61 #endif 62 struct reset_ctl phy_reset; 63 bool integrated_phy; 64 bool clock_input; 65 int phy_interface; 66 int tx_delay; 67 int rx_delay; 68 int bus_id; 69 }; 70 71 struct rk_gmac_ops { 72 #ifdef CONFIG_DWC_ETH_QOS 73 const struct eqos_config config; 74 #endif 75 int (*fix_mac_speed)(struct gmac_rockchip_platdata *pdata, 76 struct rockchip_eth_dev *dev); 77 void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata); 78 void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata); 79 void (*set_clock_selection)(struct gmac_rockchip_platdata *pdata); 80 void (*integrated_phy_powerup)(struct gmac_rockchip_platdata *pdata); 81 }; 82 83 #ifdef CONFIG_DWC_ETH_QOS 84 static const struct eqos_config eqos_rockchip_config = { 85 .reg_access_always_ok = false, 86 .mdio_wait = 10000, 87 .swr_wait = 200, 88 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED, 89 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_100_150, 90 .ops = &eqos_rockchip_ops, 91 }; 92 #endif 93 94 void gmac_set_rgmii(struct udevice *dev, u32 tx_delay, u32 rx_delay) 95 { 96 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 97 struct rk_gmac_ops *ops = 98 (struct rk_gmac_ops *)dev_get_driver_data(dev); 99 100 pdata->tx_delay = tx_delay; 101 pdata->rx_delay = rx_delay; 102 103 ops->set_to_rgmii(pdata); 104 } 105 106 static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) 107 { 108 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 109 struct ofnode_phandle_args args; 110 const char *string; 111 int ret; 112 113 string = dev_read_string(dev, "clock_in_out"); 114 if (!strcmp(string, "input")) 115 pdata->clock_input = true; 116 else 117 pdata->clock_input = false; 118 119 /* If phy-handle property is passed from DT, use it as the PHY */ 120 ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &args); 121 if (ret) { 122 debug("Cannot get phy phandle: ret=%d\n", ret); 123 pdata->integrated_phy = dev_read_bool(dev, "phy-is-integrated"); 124 } else { 125 debug("Found phy-handle subnode\n"); 126 pdata->integrated_phy = ofnode_read_bool(args.node, 127 "phy-is-integrated"); 128 } 129 130 if (pdata->integrated_phy) { 131 ret = reset_get_by_name(dev, "mac-phy", &pdata->phy_reset); 132 if (ret) { 133 debug("No PHY reset control found: ret=%d\n", ret); 134 return ret; 135 } 136 } 137 138 /* Check the new naming-style first... */ 139 pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT); 140 pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT); 141 142 /* ... and fall back to the old naming style or default, if necessary */ 143 if (pdata->tx_delay == -ENOENT) 144 pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30); 145 if (pdata->rx_delay == -ENOENT) 146 pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10); 147 148 #ifdef CONFIG_DWC_ETH_QOS 149 return 0; 150 #else 151 return designware_eth_ofdata_to_platdata(dev); 152 #endif 153 } 154 155 #ifndef CONFIG_DWC_ETH_QOS 156 static int px30_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 157 struct rockchip_eth_dev *dev) 158 { 159 struct dw_eth_dev *priv = &dev->dw; 160 struct px30_grf *grf; 161 struct clk clk_speed; 162 int speed, ret; 163 enum { 164 PX30_GMAC_SPEED_SHIFT = 0x2, 165 PX30_GMAC_SPEED_MASK = BIT(2), 166 PX30_GMAC_SPEED_10M = 0, 167 PX30_GMAC_SPEED_100M = BIT(2), 168 }; 169 170 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 171 &clk_speed); 172 if (ret) 173 return ret; 174 175 switch (priv->phydev->speed) { 176 case 10: 177 speed = PX30_GMAC_SPEED_10M; 178 ret = clk_set_rate(&clk_speed, 2500000); 179 if (ret) 180 return ret; 181 break; 182 case 100: 183 speed = PX30_GMAC_SPEED_100M; 184 ret = clk_set_rate(&clk_speed, 25000000); 185 if (ret) 186 return ret; 187 break; 188 default: 189 debug("Unknown phy speed: %d\n", priv->phydev->speed); 190 return -EINVAL; 191 } 192 193 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 194 rk_clrsetreg(&grf->mac_con1, PX30_GMAC_SPEED_MASK, speed); 195 196 return 0; 197 } 198 199 static int rk1808_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 200 struct rockchip_eth_dev *dev) 201 { 202 struct dw_eth_dev *priv = &dev->dw; 203 struct clk clk_speed; 204 int ret; 205 206 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 207 &clk_speed); 208 if (ret) 209 return ret; 210 211 switch (priv->phydev->speed) { 212 case 10: 213 ret = clk_set_rate(&clk_speed, 2500000); 214 if (ret) 215 return ret; 216 break; 217 case 100: 218 ret = clk_set_rate(&clk_speed, 25000000); 219 if (ret) 220 return ret; 221 break; 222 case 1000: 223 ret = clk_set_rate(&clk_speed, 125000000); 224 if (ret) 225 return ret; 226 break; 227 default: 228 debug("Unknown phy speed: %d\n", priv->phydev->speed); 229 return -EINVAL; 230 } 231 232 return 0; 233 } 234 235 static int rk3228_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 236 struct rockchip_eth_dev *dev) 237 { 238 struct dw_eth_dev *priv = &dev->dw; 239 struct rk322x_grf *grf; 240 int clk; 241 enum { 242 RK3228_GMAC_CLK_SEL_SHIFT = 8, 243 RK3228_GMAC_CLK_SEL_MASK = GENMASK(9, 8), 244 RK3228_GMAC_CLK_SEL_125M = 0 << 8, 245 RK3228_GMAC_CLK_SEL_25M = 3 << 8, 246 RK3228_GMAC_CLK_SEL_2_5M = 2 << 8, 247 248 RK3228_GMAC_RMII_CLK_MASK = BIT(7), 249 RK3228_GMAC_RMII_CLK_2_5M = 0, 250 RK3228_GMAC_RMII_CLK_25M = BIT(7), 251 252 RK3228_GMAC_RMII_SPEED_MASK = BIT(2), 253 RK3228_GMAC_RMII_SPEED_10 = 0, 254 RK3228_GMAC_RMII_SPEED_100 = BIT(2), 255 }; 256 257 switch (priv->phydev->speed) { 258 case 10: 259 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 260 (RK3228_GMAC_RMII_CLK_2_5M | RK3228_GMAC_RMII_SPEED_10) : 261 RK3228_GMAC_CLK_SEL_2_5M; 262 break; 263 case 100: 264 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 265 (RK3228_GMAC_RMII_CLK_25M | RK3228_GMAC_RMII_SPEED_100) : 266 RK3228_GMAC_CLK_SEL_25M; 267 break; 268 case 1000: 269 clk = RK3228_GMAC_CLK_SEL_125M; 270 break; 271 default: 272 debug("Unknown phy speed: %d\n", priv->phydev->speed); 273 return -EINVAL; 274 } 275 276 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 277 rk_clrsetreg(&grf->mac_con[1], 278 RK3228_GMAC_CLK_SEL_MASK | 279 RK3228_GMAC_RMII_CLK_MASK | 280 RK3228_GMAC_RMII_SPEED_MASK, 281 clk); 282 283 return 0; 284 } 285 286 static int rk3288_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 287 struct rockchip_eth_dev *dev) 288 { 289 struct dw_eth_dev *priv = &dev->dw; 290 struct rk3288_grf *grf; 291 int clk; 292 293 switch (priv->phydev->speed) { 294 case 10: 295 clk = RK3288_GMAC_CLK_SEL_2_5M; 296 break; 297 case 100: 298 clk = RK3288_GMAC_CLK_SEL_25M; 299 break; 300 case 1000: 301 clk = RK3288_GMAC_CLK_SEL_125M; 302 break; 303 default: 304 debug("Unknown phy speed: %d\n", priv->phydev->speed); 305 return -EINVAL; 306 } 307 308 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 309 rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk); 310 311 return 0; 312 } 313 314 static int rk3308_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 315 struct rockchip_eth_dev *dev) 316 { 317 struct dw_eth_dev *priv = &dev->dw; 318 struct rk3308_grf *grf; 319 struct clk clk_speed; 320 int speed, ret; 321 enum { 322 RK3308_GMAC_SPEED_SHIFT = 0x0, 323 RK3308_GMAC_SPEED_MASK = BIT(0), 324 RK3308_GMAC_SPEED_10M = 0, 325 RK3308_GMAC_SPEED_100M = BIT(0), 326 }; 327 328 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 329 &clk_speed); 330 if (ret) 331 return ret; 332 333 switch (priv->phydev->speed) { 334 case 10: 335 speed = RK3308_GMAC_SPEED_10M; 336 ret = clk_set_rate(&clk_speed, 2500000); 337 if (ret) 338 return ret; 339 break; 340 case 100: 341 speed = RK3308_GMAC_SPEED_100M; 342 ret = clk_set_rate(&clk_speed, 25000000); 343 if (ret) 344 return ret; 345 break; 346 default: 347 debug("Unknown phy speed: %d\n", priv->phydev->speed); 348 return -EINVAL; 349 } 350 351 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 352 rk_clrsetreg(&grf->mac_con0, RK3308_GMAC_SPEED_MASK, speed); 353 354 return 0; 355 } 356 357 static int rk3328_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 358 struct rockchip_eth_dev *dev) 359 { 360 struct dw_eth_dev *priv = &dev->dw; 361 struct rk3328_grf_regs *grf; 362 int clk; 363 enum { 364 RK3328_GMAC_CLK_SEL_SHIFT = 11, 365 RK3328_GMAC_CLK_SEL_MASK = GENMASK(12, 11), 366 RK3328_GMAC_CLK_SEL_125M = 0 << 11, 367 RK3328_GMAC_CLK_SEL_25M = 3 << 11, 368 RK3328_GMAC_CLK_SEL_2_5M = 2 << 11, 369 370 RK3328_GMAC_RMII_CLK_MASK = BIT(7), 371 RK3328_GMAC_RMII_CLK_2_5M = 0, 372 RK3328_GMAC_RMII_CLK_25M = BIT(7), 373 374 RK3328_GMAC_RMII_SPEED_MASK = BIT(2), 375 RK3328_GMAC_RMII_SPEED_10 = 0, 376 RK3328_GMAC_RMII_SPEED_100 = BIT(2), 377 }; 378 379 switch (priv->phydev->speed) { 380 case 10: 381 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 382 (RK3328_GMAC_RMII_CLK_2_5M | RK3328_GMAC_RMII_SPEED_10) : 383 RK3328_GMAC_CLK_SEL_2_5M; 384 break; 385 case 100: 386 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 387 (RK3328_GMAC_RMII_CLK_25M | RK3328_GMAC_RMII_SPEED_100) : 388 RK3328_GMAC_CLK_SEL_25M; 389 break; 390 case 1000: 391 clk = RK3328_GMAC_CLK_SEL_125M; 392 break; 393 default: 394 debug("Unknown phy speed: %d\n", priv->phydev->speed); 395 return -EINVAL; 396 } 397 398 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 399 rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1], 400 RK3328_GMAC_CLK_SEL_MASK | 401 RK3328_GMAC_RMII_CLK_MASK | 402 RK3328_GMAC_RMII_SPEED_MASK, 403 clk); 404 405 return 0; 406 } 407 408 static int rk3368_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 409 struct rockchip_eth_dev *dev) 410 { 411 struct dw_eth_dev *priv = &dev->dw; 412 struct rk3368_grf *grf; 413 int clk; 414 enum { 415 RK3368_GMAC_CLK_SEL_2_5M = 2 << 4, 416 RK3368_GMAC_CLK_SEL_25M = 3 << 4, 417 RK3368_GMAC_CLK_SEL_125M = 0 << 4, 418 RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4), 419 }; 420 421 switch (priv->phydev->speed) { 422 case 10: 423 clk = RK3368_GMAC_CLK_SEL_2_5M; 424 break; 425 case 100: 426 clk = RK3368_GMAC_CLK_SEL_25M; 427 break; 428 case 1000: 429 clk = RK3368_GMAC_CLK_SEL_125M; 430 break; 431 default: 432 debug("Unknown phy speed: %d\n", priv->phydev->speed); 433 return -EINVAL; 434 } 435 436 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 437 rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk); 438 439 return 0; 440 } 441 442 static int rk3399_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 443 struct rockchip_eth_dev *dev) 444 { 445 struct dw_eth_dev *priv = &dev->dw; 446 struct rk3399_grf_regs *grf; 447 int clk; 448 449 switch (priv->phydev->speed) { 450 case 10: 451 clk = RK3399_GMAC_CLK_SEL_2_5M; 452 break; 453 case 100: 454 clk = RK3399_GMAC_CLK_SEL_25M; 455 break; 456 case 1000: 457 clk = RK3399_GMAC_CLK_SEL_125M; 458 break; 459 default: 460 debug("Unknown phy speed: %d\n", priv->phydev->speed); 461 return -EINVAL; 462 } 463 464 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 465 rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk); 466 467 return 0; 468 } 469 470 static int rv1108_set_rmii_speed(struct gmac_rockchip_platdata *pdata, 471 struct rockchip_eth_dev *dev) 472 { 473 struct dw_eth_dev *priv = &dev->dw; 474 struct rv1108_grf *grf; 475 int clk, speed; 476 enum { 477 RV1108_GMAC_SPEED_MASK = BIT(2), 478 RV1108_GMAC_SPEED_10M = 0 << 2, 479 RV1108_GMAC_SPEED_100M = 1 << 2, 480 RV1108_GMAC_CLK_SEL_MASK = BIT(7), 481 RV1108_GMAC_CLK_SEL_2_5M = 0 << 7, 482 RV1108_GMAC_CLK_SEL_25M = 1 << 7, 483 }; 484 485 switch (priv->phydev->speed) { 486 case 10: 487 clk = RV1108_GMAC_CLK_SEL_2_5M; 488 speed = RV1108_GMAC_SPEED_10M; 489 break; 490 case 100: 491 clk = RV1108_GMAC_CLK_SEL_25M; 492 speed = RV1108_GMAC_SPEED_100M; 493 break; 494 default: 495 debug("Unknown phy speed: %d\n", priv->phydev->speed); 496 return -EINVAL; 497 } 498 499 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 500 rk_clrsetreg(&grf->gmac_con0, 501 RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK, 502 clk | speed); 503 504 return 0; 505 } 506 #else 507 static int rk3588_set_rgmii_speed(struct gmac_rockchip_platdata *pdata, 508 struct rockchip_eth_dev *dev) 509 { 510 struct eqos_priv *priv = &dev->eqos; 511 struct rk3588_php_grf *php_grf; 512 unsigned int div, div_mask; 513 514 enum { 515 RK3588_GMAC_CLK_RGMII_DIV_SHIFT = 2, 516 RK3588_GMAC_CLK_RGMII_DIV_MASK = GENMASK(3, 2), 517 RK3588_GMAC_CLK_RGMII_DIV1 = 0, 518 RK3588_GMAC_CLK_RGMII_DIV5 = GENMASK(3, 2), 519 RK3588_GMAC_CLK_RGMII_DIV50 = BIT(3), 520 RK3588_GMA_CLK_RMII_DIV2 = BIT(2), 521 RK3588_GMAC_CLK_RMII_DIV20 = 0, 522 }; 523 524 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 525 526 switch (priv->phy->speed) { 527 case 10: 528 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) 529 div = RK3588_GMAC_CLK_RMII_DIV20; 530 else 531 div = RK3588_GMAC_CLK_RGMII_DIV50; 532 break; 533 case 100: 534 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) 535 div = RK3588_GMA_CLK_RMII_DIV2; 536 else 537 div = RK3588_GMAC_CLK_RGMII_DIV5; 538 break; 539 case 1000: 540 if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII) 541 div = RK3588_GMAC_CLK_RGMII_DIV1; 542 else 543 return -EINVAL; 544 break; 545 default: 546 debug("Unknown phy speed: %d\n", priv->phy->speed); 547 return -EINVAL; 548 } 549 550 if (pdata->bus_id == 1) { 551 div <<= 5; 552 div_mask = RK3588_GMAC_CLK_RGMII_DIV_MASK << 5; 553 } 554 555 rk_clrsetreg(&php_grf->clk_con1, div_mask, div); 556 557 return 0; 558 } 559 560 static int rv1126_set_rgmii_speed(struct gmac_rockchip_platdata *pdata, 561 struct rockchip_eth_dev *dev) 562 { 563 struct eqos_priv *priv = &dev->eqos; 564 struct clk clk_speed; 565 int ret; 566 567 ret = clk_get_by_name(priv->phy->dev, "clk_mac_speed", 568 &clk_speed); 569 if (ret) { 570 printf("%s can't get clk_mac_speed clock (ret=%d):\n", 571 __func__, ret); 572 return ret; 573 } 574 575 switch ( priv->phy->speed) { 576 case 10: 577 ret = clk_set_rate(&clk_speed, 2500000); 578 if (ret) 579 return ret; 580 break; 581 case 100: 582 ret = clk_set_rate(&clk_speed, 25000000); 583 if (ret) 584 return ret; 585 break; 586 case 1000: 587 ret = clk_set_rate(&clk_speed, 125000000); 588 if (ret) 589 return ret; 590 break; 591 default: 592 debug("Unknown phy speed: %d\n", priv->phy->speed); 593 return -EINVAL; 594 } 595 596 return 0; 597 } 598 #endif 599 600 #ifndef CONFIG_DWC_ETH_QOS 601 static void px30_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 602 { 603 struct px30_grf *grf; 604 enum { 605 px30_GMAC_PHY_INTF_SEL_SHIFT = 4, 606 px30_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 6), 607 px30_GMAC_PHY_INTF_SEL_RMII = BIT(6), 608 }; 609 610 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 611 612 rk_clrsetreg(&grf->mac_con1, 613 px30_GMAC_PHY_INTF_SEL_MASK, 614 px30_GMAC_PHY_INTF_SEL_RMII); 615 } 616 617 static void rk1808_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 618 { 619 struct rk1808_grf *grf; 620 enum { 621 RK1808_GMAC_PHY_INTF_SEL_SHIFT = 4, 622 RK1808_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 623 RK1808_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 624 625 RK1808_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 626 RK1808_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 627 RK1808_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 628 629 RK1808_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 630 RK1808_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 631 RK1808_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 632 }; 633 enum { 634 RK1808_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 635 RK1808_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 7), 636 637 RK1808_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 638 RK1808_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 639 }; 640 641 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 642 rk_clrsetreg(&grf->mac_con1, 643 RK1808_GMAC_PHY_INTF_SEL_MASK | 644 RK1808_RXCLK_DLY_ENA_GMAC_MASK | 645 RK1808_TXCLK_DLY_ENA_GMAC_MASK, 646 RK1808_GMAC_PHY_INTF_SEL_RGMII | 647 RK1808_RXCLK_DLY_ENA_GMAC_ENABLE | 648 RK1808_TXCLK_DLY_ENA_GMAC_ENABLE); 649 650 rk_clrsetreg(&grf->mac_con0, 651 RK1808_CLK_RX_DL_CFG_GMAC_MASK | 652 RK1808_CLK_TX_DL_CFG_GMAC_MASK, 653 pdata->rx_delay << RK1808_CLK_RX_DL_CFG_GMAC_SHIFT | 654 pdata->tx_delay << RK1808_CLK_TX_DL_CFG_GMAC_SHIFT); 655 } 656 657 static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 658 { 659 struct rk322x_grf *grf; 660 enum { 661 RK3228_RMII_MODE_SHIFT = 10, 662 RK3228_RMII_MODE_MASK = BIT(10), 663 664 RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4, 665 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 666 RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 667 668 RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 669 RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 670 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 671 672 RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 673 RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 674 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 675 }; 676 enum { 677 RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 678 RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 679 680 RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 681 RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 682 }; 683 684 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 685 rk_clrsetreg(&grf->mac_con[1], 686 RK3228_RMII_MODE_MASK | 687 RK3228_GMAC_PHY_INTF_SEL_MASK | 688 RK3228_RXCLK_DLY_ENA_GMAC_MASK | 689 RK3228_TXCLK_DLY_ENA_GMAC_MASK, 690 RK3228_GMAC_PHY_INTF_SEL_RGMII | 691 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE | 692 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE); 693 694 rk_clrsetreg(&grf->mac_con[0], 695 RK3228_CLK_RX_DL_CFG_GMAC_MASK | 696 RK3228_CLK_TX_DL_CFG_GMAC_MASK, 697 pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT | 698 pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT); 699 } 700 701 static void rk3228_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 702 { 703 struct rk322x_grf *grf; 704 enum { 705 RK3228_GRF_CON_RMII_MODE_MASK = BIT(11), 706 RK3228_GRF_CON_RMII_MODE_SEL = BIT(11), 707 RK3228_RMII_MODE_MASK = BIT(10), 708 RK3228_RMII_MODE_SEL = BIT(10), 709 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 710 RK3228_GMAC_PHY_INTF_SEL_RMII = BIT(6), 711 }; 712 713 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 714 rk_clrsetreg(&grf->mac_con[1], 715 RK3228_GRF_CON_RMII_MODE_MASK | 716 RK3228_RMII_MODE_MASK | 717 RK3228_GMAC_PHY_INTF_SEL_MASK, 718 RK3228_GRF_CON_RMII_MODE_SEL | 719 RK3228_RMII_MODE_SEL | 720 RK3228_GMAC_PHY_INTF_SEL_RMII); 721 } 722 723 static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 724 { 725 struct rk3288_grf *grf; 726 727 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 728 rk_clrsetreg(&grf->soc_con1, 729 RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK, 730 RK3288_GMAC_PHY_INTF_SEL_RGMII); 731 732 rk_clrsetreg(&grf->soc_con3, 733 RK3288_RXCLK_DLY_ENA_GMAC_MASK | 734 RK3288_TXCLK_DLY_ENA_GMAC_MASK | 735 RK3288_CLK_RX_DL_CFG_GMAC_MASK | 736 RK3288_CLK_TX_DL_CFG_GMAC_MASK, 737 RK3288_RXCLK_DLY_ENA_GMAC_ENABLE | 738 RK3288_TXCLK_DLY_ENA_GMAC_ENABLE | 739 pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT | 740 pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT); 741 } 742 743 static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 744 { 745 struct rk3308_grf *grf; 746 enum { 747 RK3308_GMAC_PHY_INTF_SEL_SHIFT = 2, 748 RK3308_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 2), 749 RK3308_GMAC_PHY_INTF_SEL_RMII = BIT(4), 750 }; 751 752 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 753 754 rk_clrsetreg(&grf->mac_con0, 755 RK3308_GMAC_PHY_INTF_SEL_MASK, 756 RK3308_GMAC_PHY_INTF_SEL_RMII); 757 } 758 759 static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 760 { 761 struct rk3328_grf_regs *grf; 762 enum { 763 RK3328_RMII_MODE_SHIFT = 9, 764 RK3328_RMII_MODE_MASK = BIT(9), 765 766 RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4, 767 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 768 RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 769 770 RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 771 RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 772 RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 773 774 RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 775 RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 776 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 777 }; 778 enum { 779 RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 780 RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 781 782 RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 783 RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 784 }; 785 786 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 787 rk_clrsetreg(&grf->mac_con[1], 788 RK3328_RMII_MODE_MASK | 789 RK3328_GMAC_PHY_INTF_SEL_MASK | 790 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 791 RK3328_TXCLK_DLY_ENA_GMAC_MASK, 792 RK3328_GMAC_PHY_INTF_SEL_RGMII | 793 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 794 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE); 795 796 rk_clrsetreg(&grf->mac_con[0], 797 RK3328_CLK_RX_DL_CFG_GMAC_MASK | 798 RK3328_CLK_TX_DL_CFG_GMAC_MASK, 799 pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT | 800 pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT); 801 } 802 803 static void rk3328_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 804 { 805 struct rk3328_grf_regs *grf; 806 enum { 807 RK3328_RMII_MODE_MASK = BIT(9), 808 RK3328_RMII_MODE = BIT(9), 809 810 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 811 RK3328_GMAC_PHY_INTF_SEL_RMII = BIT(6), 812 }; 813 814 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 815 rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1], 816 RK3328_RMII_MODE_MASK | 817 RK3328_GMAC_PHY_INTF_SEL_MASK, 818 RK3328_GMAC_PHY_INTF_SEL_RMII | 819 RK3328_RMII_MODE); 820 } 821 822 static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 823 { 824 struct rk3368_grf *grf; 825 enum { 826 RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9, 827 RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9), 828 RK3368_RMII_MODE_MASK = BIT(6), 829 RK3368_RMII_MODE = BIT(6), 830 }; 831 enum { 832 RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15), 833 RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 834 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15), 835 RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7), 836 RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 837 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7), 838 RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8, 839 RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 840 RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0, 841 RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 842 }; 843 844 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 845 rk_clrsetreg(&grf->soc_con15, 846 RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK, 847 RK3368_GMAC_PHY_INTF_SEL_RGMII); 848 849 rk_clrsetreg(&grf->soc_con16, 850 RK3368_RXCLK_DLY_ENA_GMAC_MASK | 851 RK3368_TXCLK_DLY_ENA_GMAC_MASK | 852 RK3368_CLK_RX_DL_CFG_GMAC_MASK | 853 RK3368_CLK_TX_DL_CFG_GMAC_MASK, 854 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE | 855 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE | 856 pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT | 857 pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT); 858 } 859 860 static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 861 { 862 struct rk3399_grf_regs *grf; 863 864 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 865 866 rk_clrsetreg(&grf->soc_con5, 867 RK3399_GMAC_PHY_INTF_SEL_MASK, 868 RK3399_GMAC_PHY_INTF_SEL_RGMII); 869 870 rk_clrsetreg(&grf->soc_con6, 871 RK3399_RXCLK_DLY_ENA_GMAC_MASK | 872 RK3399_TXCLK_DLY_ENA_GMAC_MASK | 873 RK3399_CLK_RX_DL_CFG_GMAC_MASK | 874 RK3399_CLK_TX_DL_CFG_GMAC_MASK, 875 RK3399_RXCLK_DLY_ENA_GMAC_ENABLE | 876 RK3399_TXCLK_DLY_ENA_GMAC_ENABLE | 877 pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT | 878 pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT); 879 } 880 881 static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 882 { 883 struct rv1108_grf *grf; 884 885 enum { 886 RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 887 RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4, 888 }; 889 890 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 891 rk_clrsetreg(&grf->gmac_con0, 892 RV1108_GMAC_PHY_INTF_SEL_MASK, 893 RV1108_GMAC_PHY_INTF_SEL_RMII); 894 } 895 896 static void rk3228_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 897 { 898 struct rk322x_grf *grf; 899 enum { 900 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK = BIT(15), 901 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY = BIT(15), 902 }; 903 enum { 904 RK3228_MACPHY_CFG_CLK_50M_MASK = BIT(14), 905 RK3228_MACPHY_CFG_CLK_50M = BIT(14), 906 907 RK3228_MACPHY_RMII_MODE_MASK = GENMASK(7, 6), 908 RK3228_MACPHY_RMII_MODE = BIT(6), 909 910 RK3228_MACPHY_ENABLE_MASK = BIT(0), 911 RK3228_MACPHY_DISENABLE = 0, 912 RK3228_MACPHY_ENABLE = BIT(0), 913 }; 914 enum { 915 RK3228_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0), 916 RK3228_RK_GRF_CON2_MACPHY_ID = 0x1234, 917 }; 918 enum { 919 RK3228_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0), 920 RK3228_RK_GRF_CON3_MACPHY_ID = 0x35, 921 }; 922 923 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 924 rk_clrsetreg(&grf->con_iomux, 925 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK, 926 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY); 927 928 rk_clrsetreg(&grf->macphy_con[2], 929 RK3228_RK_GRF_CON2_MACPHY_ID_MASK, 930 RK3228_RK_GRF_CON2_MACPHY_ID); 931 932 rk_clrsetreg(&grf->macphy_con[3], 933 RK3228_RK_GRF_CON3_MACPHY_ID_MASK, 934 RK3228_RK_GRF_CON3_MACPHY_ID); 935 936 /* disabled before trying to reset it &*/ 937 rk_clrsetreg(&grf->macphy_con[0], 938 RK3228_MACPHY_CFG_CLK_50M_MASK | 939 RK3228_MACPHY_RMII_MODE_MASK | 940 RK3228_MACPHY_ENABLE_MASK, 941 RK3228_MACPHY_CFG_CLK_50M | 942 RK3228_MACPHY_RMII_MODE | 943 RK3228_MACPHY_DISENABLE); 944 945 reset_assert(&pdata->phy_reset); 946 udelay(10); 947 reset_deassert(&pdata->phy_reset); 948 udelay(10); 949 950 rk_clrsetreg(&grf->macphy_con[0], 951 RK3228_MACPHY_ENABLE_MASK, 952 RK3228_MACPHY_ENABLE); 953 udelay(30 * 1000); 954 } 955 956 static void rk3328_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 957 { 958 struct rk3328_grf_regs *grf; 959 enum { 960 RK3328_GRF_CON_RMII_MODE_MASK = BIT(9), 961 RK3328_GRF_CON_RMII_MODE = BIT(9), 962 }; 963 enum { 964 RK3328_MACPHY_CFG_CLK_50M_MASK = BIT(14), 965 RK3328_MACPHY_CFG_CLK_50M = BIT(14), 966 967 RK3328_MACPHY_RMII_MODE_MASK = GENMASK(7, 6), 968 RK3328_MACPHY_RMII_MODE = BIT(6), 969 970 RK3328_MACPHY_ENABLE_MASK = BIT(0), 971 RK3328_MACPHY_DISENABLE = 0, 972 RK3328_MACPHY_ENABLE = BIT(0), 973 }; 974 enum { 975 RK3328_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0), 976 RK3328_RK_GRF_CON2_MACPHY_ID = 0x1234, 977 }; 978 enum { 979 RK3328_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0), 980 RK3328_RK_GRF_CON3_MACPHY_ID = 0x35, 981 }; 982 983 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 984 rk_clrsetreg(&grf->macphy_con[1], 985 RK3328_GRF_CON_RMII_MODE_MASK, 986 RK3328_GRF_CON_RMII_MODE); 987 988 rk_clrsetreg(&grf->macphy_con[2], 989 RK3328_RK_GRF_CON2_MACPHY_ID_MASK, 990 RK3328_RK_GRF_CON2_MACPHY_ID); 991 992 rk_clrsetreg(&grf->macphy_con[3], 993 RK3328_RK_GRF_CON3_MACPHY_ID_MASK, 994 RK3328_RK_GRF_CON3_MACPHY_ID); 995 996 /* disabled before trying to reset it &*/ 997 rk_clrsetreg(&grf->macphy_con[0], 998 RK3328_MACPHY_CFG_CLK_50M_MASK | 999 RK3328_MACPHY_RMII_MODE_MASK | 1000 RK3328_MACPHY_ENABLE_MASK, 1001 RK3328_MACPHY_CFG_CLK_50M | 1002 RK3328_MACPHY_RMII_MODE | 1003 RK3328_MACPHY_DISENABLE); 1004 1005 reset_assert(&pdata->phy_reset); 1006 udelay(10); 1007 reset_deassert(&pdata->phy_reset); 1008 udelay(10); 1009 1010 rk_clrsetreg(&grf->macphy_con[0], 1011 RK3328_MACPHY_ENABLE_MASK, 1012 RK3328_MACPHY_ENABLE); 1013 udelay(30 * 1000); 1014 } 1015 1016 #else 1017 static void rk3568_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1018 { 1019 struct rk3568_grf *grf; 1020 void *con1; 1021 1022 enum { 1023 RK3568_GMAC_PHY_INTF_SEL_SHIFT = 4, 1024 RK3568_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1025 RK3568_GMAC_PHY_INTF_SEL_RMII = BIT(6), 1026 }; 1027 1028 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1029 1030 if (pdata->bus_id == 1) 1031 con1 = &grf->mac1_con1; 1032 else 1033 con1 = &grf->mac0_con1; 1034 1035 rk_clrsetreg(con1, 1036 RK3568_GMAC_PHY_INTF_SEL_MASK, 1037 RK3568_GMAC_PHY_INTF_SEL_RMII); 1038 } 1039 1040 static void rk3568_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1041 { 1042 struct rk3568_grf *grf; 1043 void *con0, *con1; 1044 1045 enum { 1046 RK3568_GMAC_PHY_INTF_SEL_SHIFT = 4, 1047 RK3568_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1048 RK3568_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 1049 1050 RK3568_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 1051 RK3568_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 1052 RK3568_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 1053 1054 RK3568_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 1055 RK3568_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 1056 RK3568_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 1057 }; 1058 1059 enum { 1060 RK3568_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1061 RK3568_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 8), 1062 1063 RK3568_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1064 RK3568_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 1065 }; 1066 1067 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1068 1069 if (pdata->bus_id == 1) { 1070 con0 = &grf->mac1_con0; 1071 con1 = &grf->mac1_con1; 1072 } else { 1073 con0 = &grf->mac0_con0; 1074 con1 = &grf->mac0_con1; 1075 } 1076 1077 rk_clrsetreg(con0, 1078 RK3568_CLK_RX_DL_CFG_GMAC_MASK | 1079 RK3568_CLK_TX_DL_CFG_GMAC_MASK, 1080 pdata->rx_delay << RK3568_CLK_RX_DL_CFG_GMAC_SHIFT | 1081 pdata->tx_delay << RK3568_CLK_TX_DL_CFG_GMAC_SHIFT); 1082 1083 rk_clrsetreg(con1, 1084 RK3568_TXCLK_DLY_ENA_GMAC_MASK | 1085 RK3568_RXCLK_DLY_ENA_GMAC_MASK | 1086 RK3568_GMAC_PHY_INTF_SEL_MASK, 1087 RK3568_TXCLK_DLY_ENA_GMAC_ENABLE | 1088 RK3568_RXCLK_DLY_ENA_GMAC_ENABLE | 1089 RK3568_GMAC_PHY_INTF_SEL_RGMII); 1090 } 1091 1092 static void rk3588_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1093 { 1094 unsigned int intf_sel, intf_sel_mask; 1095 unsigned int clk_mode, clk_mode_mask; 1096 struct rk3588_php_grf *php_grf; 1097 1098 enum { 1099 RK3588_GMAC_PHY_INTF_SEL_SHIFT = 3, 1100 RK3588_GMAC_PHY_INTF_SEL_MASK = GENMASK(5, 3), 1101 RK3588_GMAC_PHY_INTF_SEL_RMII = BIT(5), 1102 }; 1103 1104 enum { 1105 RK3588_GMAC_CLK_RMII_MODE_SHIFT = 0x0, 1106 RK3588_GMAC_CLK_RMII_MODE_MASK = BIT(0), 1107 RK3588_GMAC_CLK_RMII_MODE = 0x1, 1108 }; 1109 1110 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 1111 1112 if (pdata->bus_id == 1) { 1113 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RMII << 6; 1114 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK << 6; 1115 clk_mode = RK3588_GMAC_CLK_RMII_MODE << 5; 1116 clk_mode_mask = RK3588_GMAC_CLK_RMII_MODE_MASK << 5; 1117 } else { 1118 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RMII; 1119 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK; 1120 clk_mode = RK3588_GMAC_CLK_RMII_MODE; 1121 clk_mode_mask = RK3588_GMAC_CLK_RMII_MODE_MASK; 1122 } 1123 1124 rk_clrsetreg(&php_grf->gmac_con0, intf_sel_mask, intf_sel); 1125 rk_clrsetreg(&php_grf->clk_con1, clk_mode_mask, clk_mode); 1126 } 1127 1128 static void rk3588_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1129 { 1130 unsigned int rx_enable, rx_enable_mask, tx_enable, tx_enable_mask; 1131 unsigned int intf_sel, intf_sel_mask; 1132 unsigned int clk_mode, clk_mode_mask; 1133 unsigned int rx_delay; 1134 struct rk3588_php_grf *php_grf; 1135 struct rk3588_sys_grf *grf; 1136 void *offset_con; 1137 1138 enum { 1139 RK3588_GMAC_PHY_INTF_SEL_SHIFT = 3, 1140 RK3588_GMAC_PHY_INTF_SEL_MASK = GENMASK(5, 3), 1141 RK3588_GMAC_PHY_INTF_SEL_RGMII = BIT(3), 1142 1143 RK3588_RXCLK_DLY_ENA_GMAC_MASK = BIT(3), 1144 RK3588_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 1145 RK3588_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(3), 1146 1147 RK3588_TXCLK_DLY_ENA_GMAC_MASK = BIT(2), 1148 RK3588_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 1149 RK3588_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(2), 1150 }; 1151 1152 enum { 1153 RK3588_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1154 RK3588_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 8), 1155 1156 RK3588_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1157 RK3588_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 1158 }; 1159 1160 enum { 1161 RK3588_GMAC_CLK_RGMII_MODE_SHIFT = 0x0, 1162 RK3588_GMAC_CLK_RGMII_MODE_MASK = BIT(0), 1163 RK3588_GMAC_CLK_RGMII_MODE = 0x0, 1164 }; 1165 1166 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1167 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 1168 1169 if (pdata->rx_delay < 0) { 1170 rx_enable = RK3588_RXCLK_DLY_ENA_GMAC_DISABLE; 1171 rx_delay = 0; 1172 } else { 1173 rx_enable = RK3588_RXCLK_DLY_ENA_GMAC_ENABLE; 1174 rx_delay = pdata->rx_delay << RK3588_CLK_RX_DL_CFG_GMAC_SHIFT; 1175 } 1176 1177 if (pdata->bus_id == 1) { 1178 offset_con = &grf->soc_con9; 1179 rx_enable = rx_delay << 2; 1180 rx_enable_mask = RK3588_RXCLK_DLY_ENA_GMAC_MASK << 2; 1181 tx_enable = RK3588_TXCLK_DLY_ENA_GMAC_ENABLE << 2; 1182 tx_enable_mask = RK3588_TXCLK_DLY_ENA_GMAC_MASK << 2; 1183 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RGMII << 6; 1184 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK << 6; 1185 clk_mode = RK3588_GMAC_CLK_RGMII_MODE << 5; 1186 clk_mode_mask = RK3588_GMAC_CLK_RGMII_MODE_MASK << 5; 1187 } else { 1188 offset_con = &grf->soc_con8; 1189 rx_enable_mask = RK3588_RXCLK_DLY_ENA_GMAC_MASK; 1190 tx_enable = RK3588_TXCLK_DLY_ENA_GMAC_ENABLE; 1191 tx_enable_mask = RK3588_TXCLK_DLY_ENA_GMAC_MASK; 1192 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RGMII; 1193 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK; 1194 clk_mode = RK3588_GMAC_CLK_RGMII_MODE; 1195 clk_mode_mask = RK3588_GMAC_CLK_RGMII_MODE_MASK; 1196 } 1197 1198 rk_clrsetreg(offset_con, 1199 RK3588_CLK_TX_DL_CFG_GMAC_MASK | 1200 RK3588_CLK_RX_DL_CFG_GMAC_MASK, 1201 pdata->tx_delay << RK3588_CLK_TX_DL_CFG_GMAC_SHIFT | 1202 rx_delay); 1203 1204 rk_clrsetreg(&grf->soc_con7, tx_enable_mask | rx_enable_mask, 1205 tx_enable | rx_enable); 1206 1207 rk_clrsetreg(&php_grf->gmac_con0, intf_sel_mask, intf_sel); 1208 rk_clrsetreg(&php_grf->clk_con1, clk_mode_mask, clk_mode); 1209 } 1210 1211 static void rv1126_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1212 { 1213 struct rv1126_grf *grf; 1214 1215 enum { 1216 RV1126_GMAC_PHY_INTF_SEL_SHIFT = 4, 1217 RV1126_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1218 RV1126_GMAC_PHY_INTF_SEL_RMII = BIT(6), 1219 }; 1220 1221 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1222 1223 rk_clrsetreg(&grf->mac_con0, 1224 RV1126_GMAC_PHY_INTF_SEL_MASK, 1225 RV1126_GMAC_PHY_INTF_SEL_RMII); 1226 } 1227 1228 static void rv1126_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1229 { 1230 struct rv1126_grf *grf; 1231 1232 enum { 1233 RV1126_GMAC_PHY_INTF_SEL_SHIFT = 4, 1234 RV1126_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1235 RV1126_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 1236 1237 RV1126_RXCLK_M1_DLY_ENA_GMAC_MASK = BIT(3), 1238 RV1126_RXCLK_M1_DLY_ENA_GMAC_DISABLE = 0, 1239 RV1126_RXCLK_M1_DLY_ENA_GMAC_ENABLE = BIT(3), 1240 1241 RV1126_TXCLK_M1_DLY_ENA_GMAC_MASK = BIT(2), 1242 RV1126_TXCLK_M1_DLY_ENA_GMAC_DISABLE = 0, 1243 RV1126_TXCLK_M1_DLY_ENA_GMAC_ENABLE = BIT(2), 1244 1245 RV1126_RXCLK_M0_DLY_ENA_GMAC_MASK = BIT(1), 1246 RV1126_RXCLK_M0_DLY_ENA_GMAC_DISABLE = 0, 1247 RV1126_RXCLK_M0_DLY_ENA_GMAC_ENABLE = BIT(1), 1248 1249 RV1126_TXCLK_M0_DLY_ENA_GMAC_MASK = BIT(0), 1250 RV1126_TXCLK_M0_DLY_ENA_GMAC_DISABLE = 0, 1251 RV1126_TXCLK_M0_DLY_ENA_GMAC_ENABLE = BIT(0), 1252 }; 1253 enum { 1254 RV1126_M0_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1255 RV1126_M0_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 1256 1257 RV1126_M0_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1258 RV1126_M0_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 1259 }; 1260 enum { 1261 RV1126_M1_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1262 RV1126_M1_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 1263 1264 RV1126_M1_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1265 RV1126_M1_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 1266 }; 1267 1268 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1269 1270 rk_clrsetreg(&grf->mac_con0, 1271 RV1126_TXCLK_M0_DLY_ENA_GMAC_MASK | 1272 RV1126_RXCLK_M0_DLY_ENA_GMAC_MASK | 1273 RV1126_TXCLK_M1_DLY_ENA_GMAC_MASK | 1274 RV1126_RXCLK_M1_DLY_ENA_GMAC_MASK | 1275 RV1126_GMAC_PHY_INTF_SEL_MASK, 1276 RV1126_TXCLK_M0_DLY_ENA_GMAC_ENABLE | 1277 RV1126_RXCLK_M0_DLY_ENA_GMAC_ENABLE | 1278 RV1126_TXCLK_M1_DLY_ENA_GMAC_ENABLE | 1279 RV1126_RXCLK_M1_DLY_ENA_GMAC_ENABLE | 1280 RV1126_GMAC_PHY_INTF_SEL_RGMII); 1281 1282 rk_clrsetreg(&grf->mac_con1, 1283 RV1126_M0_CLK_RX_DL_CFG_GMAC_MASK | 1284 RV1126_M0_CLK_TX_DL_CFG_GMAC_MASK, 1285 pdata->rx_delay << RV1126_M0_CLK_RX_DL_CFG_GMAC_SHIFT | 1286 pdata->tx_delay << RV1126_M0_CLK_TX_DL_CFG_GMAC_SHIFT); 1287 1288 rk_clrsetreg(&grf->mac_con2, 1289 RV1126_M1_CLK_RX_DL_CFG_GMAC_MASK | 1290 RV1126_M1_CLK_TX_DL_CFG_GMAC_MASK, 1291 pdata->rx_delay << RV1126_M1_CLK_RX_DL_CFG_GMAC_SHIFT | 1292 pdata->tx_delay << RV1126_M1_CLK_TX_DL_CFG_GMAC_SHIFT); 1293 } 1294 #endif 1295 1296 #ifdef CONFIG_DWC_ETH_QOS 1297 static void rk3588_set_clock_selection(struct gmac_rockchip_platdata *pdata) 1298 { 1299 struct rk3588_php_grf *php_grf; 1300 unsigned int val, mask; 1301 1302 enum { 1303 RK3588_GMAC_CLK_SELET_SHIFT = 0x4, 1304 RK3588_GMAC_CLK_SELET_MASK = BIT(4), 1305 RK3588_GMAC_CLK_SELET_CRU = BIT(4), 1306 RK3588_GMAC_CLK_SELET_IO = 0, 1307 }; 1308 1309 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 1310 val = pdata->clock_input ? RK3588_GMAC_CLK_SELET_IO : 1311 RK3588_GMAC_CLK_SELET_CRU; 1312 mask = RK3588_GMAC_CLK_SELET_MASK; 1313 1314 if (pdata->bus_id == 1) { 1315 val <<= 5; 1316 mask <<= 5; 1317 } 1318 1319 rk_clrsetreg(&php_grf->clk_con1, mask, val); 1320 } 1321 #endif 1322 1323 static int gmac_rockchip_probe(struct udevice *dev) 1324 { 1325 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 1326 struct rk_gmac_ops *ops = 1327 (struct rk_gmac_ops *)dev_get_driver_data(dev); 1328 #ifdef CONFIG_DWC_ETH_QOS 1329 struct eqos_config *config; 1330 #else 1331 struct dw_eth_pdata *dw_pdata; 1332 #endif 1333 struct eth_pdata *eth_pdata; 1334 struct clk clk; 1335 ulong rate; 1336 int ret; 1337 1338 #ifdef CONFIG_DWC_ETH_QOS 1339 eth_pdata = &pdata->eth_pdata; 1340 config = (struct eqos_config *)&ops->config; 1341 memcpy(config, &eqos_rockchip_config, sizeof(struct eqos_config)); 1342 eth_pdata->phy_interface = config->ops->eqos_get_interface(dev); 1343 #else 1344 dw_pdata = &pdata->dw_eth_pdata; 1345 eth_pdata = &dw_pdata->eth_pdata; 1346 #endif 1347 pdata->bus_id = dev->seq; 1348 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 1349 ret = clk_set_defaults(dev); 1350 if (ret) 1351 debug("%s clk_set_defaults failed %d\n", __func__, ret); 1352 1353 ret = clk_get_by_index(dev, 0, &clk); 1354 if (ret) 1355 return ret; 1356 1357 pdata->phy_interface = eth_pdata->phy_interface; 1358 1359 if (ops->set_clock_selection) 1360 ops->set_clock_selection(pdata); 1361 1362 if (pdata->integrated_phy && ops->integrated_phy_powerup) 1363 ops->integrated_phy_powerup(pdata); 1364 1365 switch (eth_pdata->phy_interface) { 1366 case PHY_INTERFACE_MODE_RGMII: 1367 case PHY_INTERFACE_MODE_RGMII_RXID: 1368 /* 1369 * If the gmac clock is from internal pll, need to set and 1370 * check the return value for gmac clock at RGMII mode. If 1371 * the gmac clock is from external source, the clock rate 1372 * is not set, because of it is bypassed. 1373 */ 1374 if (!pdata->clock_input) { 1375 rate = clk_set_rate(&clk, 125000000); 1376 if (rate != 125000000) 1377 return -EINVAL; 1378 } 1379 1380 if (eth_pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) 1381 pdata->rx_delay = -1; 1382 1383 /* Set to RGMII mode */ 1384 if (ops->set_to_rgmii) 1385 ops->set_to_rgmii(pdata); 1386 else 1387 return -EPERM; 1388 1389 break; 1390 case PHY_INTERFACE_MODE_RMII: 1391 /* The commet is the same as RGMII mode */ 1392 if (!pdata->clock_input) { 1393 rate = clk_set_rate(&clk, 50000000); 1394 if (rate != 50000000) 1395 return -EINVAL; 1396 } 1397 1398 /* Set to RMII mode */ 1399 if (ops->set_to_rmii) 1400 ops->set_to_rmii(pdata); 1401 else 1402 return -EPERM; 1403 1404 break; 1405 default: 1406 debug("NO interface defined!\n"); 1407 return -ENXIO; 1408 } 1409 1410 #ifdef CONFIG_DWC_ETH_QOS 1411 return eqos_probe(dev); 1412 #else 1413 return designware_eth_probe(dev); 1414 #endif 1415 } 1416 1417 static int gmac_rockchip_eth_write_hwaddr(struct udevice *dev) 1418 { 1419 #if defined(CONFIG_DWC_ETH_QOS) 1420 return eqos_write_hwaddr(dev); 1421 #else 1422 return designware_eth_write_hwaddr(dev); 1423 #endif 1424 } 1425 1426 static int gmac_rockchip_eth_free_pkt(struct udevice *dev, uchar *packet, 1427 int length) 1428 { 1429 #ifdef CONFIG_DWC_ETH_QOS 1430 return eqos_free_pkt(dev, packet, length); 1431 #else 1432 return designware_eth_free_pkt(dev, packet, length); 1433 #endif 1434 } 1435 1436 static int gmac_rockchip_eth_send(struct udevice *dev, void *packet, 1437 int length) 1438 { 1439 #ifdef CONFIG_DWC_ETH_QOS 1440 return eqos_send(dev, packet, length); 1441 #else 1442 return designware_eth_send(dev, packet, length); 1443 #endif 1444 } 1445 1446 static int gmac_rockchip_eth_recv(struct udevice *dev, int flags, 1447 uchar **packetp) 1448 { 1449 #ifdef CONFIG_DWC_ETH_QOS 1450 return eqos_recv(dev, flags, packetp); 1451 #else 1452 return designware_eth_recv(dev, flags, packetp); 1453 #endif 1454 } 1455 1456 static int gmac_rockchip_eth_start(struct udevice *dev) 1457 { 1458 struct rockchip_eth_dev *priv = dev_get_priv(dev); 1459 struct rk_gmac_ops *ops = 1460 (struct rk_gmac_ops *)dev_get_driver_data(dev); 1461 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 1462 #ifndef CONFIG_DWC_ETH_QOS 1463 struct dw_eth_pdata *dw_pdata; 1464 struct eth_pdata *eth_pdata; 1465 #endif 1466 int ret; 1467 1468 #ifdef CONFIG_DWC_ETH_QOS 1469 ret = eqos_init(dev); 1470 #else 1471 dw_pdata = &pdata->dw_eth_pdata; 1472 eth_pdata = &dw_pdata->eth_pdata; 1473 ret = designware_eth_init((struct dw_eth_dev *)priv, 1474 eth_pdata->enetaddr); 1475 #endif 1476 if (ret) 1477 return ret; 1478 ret = ops->fix_mac_speed(pdata, priv); 1479 if (ret) 1480 return ret; 1481 1482 #ifdef CONFIG_DWC_ETH_QOS 1483 eqos_enable(dev); 1484 #else 1485 ret = designware_eth_enable((struct dw_eth_dev *)priv); 1486 if (ret) 1487 return ret; 1488 #endif 1489 1490 return 0; 1491 } 1492 1493 static void gmac_rockchip_eth_stop(struct udevice *dev) 1494 { 1495 #ifdef CONFIG_DWC_ETH_QOS 1496 eqos_stop(dev); 1497 #else 1498 designware_eth_stop(dev); 1499 #endif 1500 } 1501 1502 const struct eth_ops gmac_rockchip_eth_ops = { 1503 .start = gmac_rockchip_eth_start, 1504 .send = gmac_rockchip_eth_send, 1505 .recv = gmac_rockchip_eth_recv, 1506 .free_pkt = gmac_rockchip_eth_free_pkt, 1507 .stop = gmac_rockchip_eth_stop, 1508 .write_hwaddr = gmac_rockchip_eth_write_hwaddr, 1509 }; 1510 1511 #ifndef CONFIG_DWC_ETH_QOS 1512 const struct rk_gmac_ops px30_gmac_ops = { 1513 .fix_mac_speed = px30_gmac_fix_mac_speed, 1514 .set_to_rmii = px30_gmac_set_to_rmii, 1515 }; 1516 1517 const struct rk_gmac_ops rk1808_gmac_ops = { 1518 .fix_mac_speed = rk1808_gmac_fix_mac_speed, 1519 .set_to_rgmii = rk1808_gmac_set_to_rgmii, 1520 }; 1521 1522 const struct rk_gmac_ops rk3228_gmac_ops = { 1523 .fix_mac_speed = rk3228_gmac_fix_mac_speed, 1524 .set_to_rmii = rk3228_gmac_set_to_rmii, 1525 .set_to_rgmii = rk3228_gmac_set_to_rgmii, 1526 .integrated_phy_powerup = rk3228_gmac_integrated_phy_powerup, 1527 }; 1528 1529 const struct rk_gmac_ops rk3288_gmac_ops = { 1530 .fix_mac_speed = rk3288_gmac_fix_mac_speed, 1531 .set_to_rgmii = rk3288_gmac_set_to_rgmii, 1532 }; 1533 1534 const struct rk_gmac_ops rk3308_gmac_ops = { 1535 .fix_mac_speed = rk3308_gmac_fix_mac_speed, 1536 .set_to_rmii = rk3308_gmac_set_to_rmii, 1537 }; 1538 1539 const struct rk_gmac_ops rk3328_gmac_ops = { 1540 .fix_mac_speed = rk3328_gmac_fix_mac_speed, 1541 .set_to_rmii = rk3328_gmac_set_to_rmii, 1542 .set_to_rgmii = rk3328_gmac_set_to_rgmii, 1543 .integrated_phy_powerup = rk3328_gmac_integrated_phy_powerup, 1544 }; 1545 1546 const struct rk_gmac_ops rk3368_gmac_ops = { 1547 .fix_mac_speed = rk3368_gmac_fix_mac_speed, 1548 .set_to_rgmii = rk3368_gmac_set_to_rgmii, 1549 }; 1550 1551 const struct rk_gmac_ops rk3399_gmac_ops = { 1552 .fix_mac_speed = rk3399_gmac_fix_mac_speed, 1553 .set_to_rgmii = rk3399_gmac_set_to_rgmii, 1554 }; 1555 1556 const struct rk_gmac_ops rv1108_gmac_ops = { 1557 .fix_mac_speed = rv1108_set_rmii_speed, 1558 .set_to_rmii = rv1108_gmac_set_to_rmii, 1559 }; 1560 #else 1561 const struct rk_gmac_ops rk3568_gmac_ops = { 1562 .fix_mac_speed = rv1126_set_rgmii_speed, 1563 .set_to_rgmii = rk3568_set_to_rgmii, 1564 .set_to_rmii = rk3568_set_to_rmii, 1565 }; 1566 1567 const struct rk_gmac_ops rk3588_gmac_ops = { 1568 .fix_mac_speed = rk3588_set_rgmii_speed, 1569 .set_to_rgmii = rk3588_set_to_rgmii, 1570 .set_to_rmii = rk3588_set_to_rmii, 1571 .set_clock_selection = rk3588_set_clock_selection, 1572 }; 1573 1574 const struct rk_gmac_ops rv1126_gmac_ops = { 1575 .fix_mac_speed = rv1126_set_rgmii_speed, 1576 .set_to_rgmii = rv1126_set_to_rgmii, 1577 .set_to_rmii = rv1126_set_to_rmii, 1578 }; 1579 #endif 1580 1581 static const struct udevice_id rockchip_gmac_ids[] = { 1582 #ifndef CONFIG_DWC_ETH_QOS 1583 #ifdef CONFIG_ROCKCHIP_PX30 1584 { .compatible = "rockchip,px30-gmac", 1585 .data = (ulong)&px30_gmac_ops }, 1586 #endif 1587 1588 #ifdef CONFIG_ROCKCHIP_RK1808 1589 { .compatible = "rockchip,rk1808-gmac", 1590 .data = (ulong)&rk1808_gmac_ops }, 1591 #endif 1592 1593 #ifdef CONFIG_ROCKCHIP_RK3228 1594 { .compatible = "rockchip,rk3228-gmac", 1595 .data = (ulong)&rk3228_gmac_ops }, 1596 #endif 1597 1598 #ifdef CONFIG_ROCKCHIP_RK3288 1599 { .compatible = "rockchip,rk3288-gmac", 1600 .data = (ulong)&rk3288_gmac_ops }, 1601 #endif 1602 1603 #ifdef CONFIG_ROCKCHIP_RK3308 1604 { .compatible = "rockchip,rk3308-mac", 1605 .data = (ulong)&rk3308_gmac_ops }, 1606 #endif 1607 1608 #ifdef CONFIG_ROCKCHIP_RK3328 1609 { .compatible = "rockchip,rk3328-gmac", 1610 .data = (ulong)&rk3328_gmac_ops }, 1611 #endif 1612 1613 #ifdef CONFIG_ROCKCHIP_RK3368 1614 { .compatible = "rockchip,rk3368-gmac", 1615 .data = (ulong)&rk3368_gmac_ops }, 1616 #endif 1617 1618 #ifdef CONFIG_ROCKCHIP_RK3399 1619 { .compatible = "rockchip,rk3399-gmac", 1620 .data = (ulong)&rk3399_gmac_ops }, 1621 #endif 1622 1623 #ifdef CONFIG_ROCKCHIP_RV1108 1624 { .compatible = "rockchip,rv1108-gmac", 1625 .data = (ulong)&rv1108_gmac_ops }, 1626 #endif 1627 #else 1628 #ifdef CONFIG_ROCKCHIP_RK3568 1629 { .compatible = "rockchip,rk3568-gmac", 1630 .data = (ulong)&rk3568_gmac_ops }, 1631 #endif 1632 1633 #ifdef CONFIG_ROCKCHIP_RK3588 1634 { .compatible = "rockchip,rk3588-gmac", 1635 .data = (ulong)&rk3588_gmac_ops }, 1636 #endif 1637 1638 #ifdef CONFIG_ROCKCHIP_RV1126 1639 { .compatible = "rockchip,rv1126-gmac", 1640 .data = (ulong)&rv1126_gmac_ops }, 1641 #endif 1642 #endif 1643 { } 1644 }; 1645 1646 U_BOOT_DRIVER(eth_gmac_rockchip) = { 1647 .name = "gmac_rockchip", 1648 .id = UCLASS_ETH, 1649 .of_match = rockchip_gmac_ids, 1650 .ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata, 1651 .probe = gmac_rockchip_probe, 1652 .ops = &gmac_rockchip_eth_ops, 1653 .priv_auto_alloc_size = sizeof(struct rockchip_eth_dev), 1654 .platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata), 1655 .flags = DM_FLAG_ALLOC_PRIV_DMA, 1656 }; 1657