1 /* 2 * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Rockchip GMAC ethernet IP driver for U-Boot 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <clk.h> 12 #include <misc.h> 13 #include <phy.h> 14 #include <reset.h> 15 #include <syscon.h> 16 #include <asm/io.h> 17 #include <asm/arch/periph.h> 18 #include <asm/arch/clock.h> 19 #include <asm/arch/hardware.h> 20 #ifdef CONFIG_DWC_ETH_QOS 21 #include <asm/arch/grf_rk3506.h> 22 #include <asm/arch/grf_rk3528.h> 23 #include <asm/arch/grf_rk3562.h> 24 #include <asm/arch/ioc_rk3562.h> 25 #include <asm/arch/grf_rk3568.h> 26 #include <asm/arch/grf_rk3576.h> 27 #include <asm/arch/ioc_rk3576.h> 28 #include <asm/arch/grf_rk3588.h> 29 #include <asm/arch/grf_rv1103b.h> 30 #include <asm/arch/grf_rv1106.h> 31 #include <asm/arch/grf_rv1126.h> 32 #include "dwc_eth_qos.h" 33 #else 34 #include <asm/arch/grf_px30.h> 35 #include <asm/arch/grf_rk1808.h> 36 #include <asm/arch/grf_rk322x.h> 37 #include <asm/arch/grf_rk3288.h> 38 #include <asm/arch/grf_rk3308.h> 39 #include <asm/arch/grf_rk3328.h> 40 #include <asm/arch/grf_rk3368.h> 41 #include <asm/arch/grf_rk3399.h> 42 #include <asm/arch/grf_rv1108.h> 43 #include "designware.h" 44 #include <dt-bindings/clock/rk3288-cru.h> 45 #endif 46 #include <dm/pinctrl.h> 47 #include <dm/of_access.h> 48 49 DECLARE_GLOBAL_DATA_PTR; 50 51 struct rockchip_eth_dev { 52 #ifdef CONFIG_DWC_ETH_QOS 53 struct eqos_priv eqos; 54 #else 55 struct dw_eth_dev dw; 56 #endif 57 int phy_interface; 58 }; 59 60 #define HIWORD_UPDATE(val, mask, shift) ((val) << (shift) | (mask) << ((shift) + 16)) 61 62 #define DELAY_VALUE(soc, tx, rx) ((((tx) >= 0) ? soc##_GMAC_CLK_TX_DL_CFG(tx) : 0) | (((rx) >= 0) ? soc##_GMAC_CLK_RX_DL_CFG(rx) : 0)) 63 64 #define RK3576_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 65 #define RK3576_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 66 67 /* 68 * Platform data for the gmac 69 * 70 * dw_eth_pdata: Required platform data for designware driver (must be first) 71 */ 72 struct gmac_rockchip_platdata { 73 #ifndef CONFIG_DWC_ETH_QOS 74 struct dw_eth_pdata dw_eth_pdata; 75 #else 76 struct eth_pdata eth_pdata; 77 #endif 78 struct reset_ctl phy_reset; 79 bool integrated_phy; 80 bool clock_input; 81 int phy_interface; 82 int tx_delay; 83 int rx_delay; 84 int bus_id; 85 }; 86 87 struct rk_gmac_ops { 88 #ifdef CONFIG_DWC_ETH_QOS 89 const struct eqos_config config; 90 #endif 91 int (*fix_mac_speed)(struct gmac_rockchip_platdata *pdata, 92 struct rockchip_eth_dev *dev); 93 void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata); 94 void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata); 95 void (*set_clock_selection)(struct gmac_rockchip_platdata *pdata); 96 void (*integrated_phy_powerup)(struct gmac_rockchip_platdata *pdata); 97 }; 98 99 #ifdef CONFIG_DWC_ETH_QOS 100 static const struct eqos_config eqos_rockchip_config = { 101 .reg_access_always_ok = false, 102 .mdio_wait = 10000, 103 .swr_wait = 200, 104 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED, 105 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_100_150, 106 .ops = &eqos_rockchip_ops, 107 }; 108 #endif 109 110 void gmac_set_rgmii(struct udevice *dev, u32 tx_delay, u32 rx_delay) 111 { 112 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 113 struct rk_gmac_ops *ops = 114 (struct rk_gmac_ops *)dev_get_driver_data(dev); 115 116 pdata->tx_delay = tx_delay; 117 pdata->rx_delay = rx_delay; 118 119 ops->set_to_rgmii(pdata); 120 } 121 122 static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) 123 { 124 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 125 struct ofnode_phandle_args args; 126 struct udevice *phydev; 127 const char *string; 128 int ret; 129 130 string = dev_read_string(dev, "clock_in_out"); 131 if (!strcmp(string, "input")) 132 pdata->clock_input = true; 133 else 134 pdata->clock_input = false; 135 136 /* If phy-handle property is passed from DT, use it as the PHY */ 137 ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &args); 138 if (ret) { 139 debug("Cannot get phy phandle: ret=%d\n", ret); 140 pdata->integrated_phy = dev_read_bool(dev, "phy-is-integrated"); 141 } else { 142 debug("Found phy-handle subnode\n"); 143 pdata->integrated_phy = ofnode_read_bool(args.node, 144 "phy-is-integrated"); 145 } 146 147 if (pdata->integrated_phy) { 148 ret = reset_get_by_name(dev, "mac-phy", &pdata->phy_reset); 149 if (ret) { 150 ret = uclass_get_device_by_ofnode(UCLASS_ETH_PHY, args.node, &phydev); 151 if (ret) { 152 debug("Get phydev by ofnode failed: err=%d\n", ret); 153 return ret; 154 } 155 156 ret = reset_get_by_index(phydev, 0, &pdata->phy_reset); 157 if (ret) { 158 debug("No PHY reset control found: ret=%d\n", ret); 159 return ret; 160 } 161 } 162 } 163 164 /* Check the new naming-style first... */ 165 pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT); 166 pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT); 167 168 /* ... and fall back to the old naming style or default, if necessary */ 169 if (pdata->tx_delay == -ENOENT) 170 pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30); 171 if (pdata->rx_delay == -ENOENT) 172 pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10); 173 174 #ifdef CONFIG_DWC_ETH_QOS 175 return 0; 176 #else 177 return designware_eth_ofdata_to_platdata(dev); 178 #endif 179 } 180 181 #ifndef CONFIG_DWC_ETH_QOS 182 static int px30_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 183 struct rockchip_eth_dev *dev) 184 { 185 struct dw_eth_dev *priv = &dev->dw; 186 struct px30_grf *grf; 187 struct clk clk_speed; 188 int speed, ret; 189 enum { 190 PX30_GMAC_SPEED_SHIFT = 0x2, 191 PX30_GMAC_SPEED_MASK = BIT(2), 192 PX30_GMAC_SPEED_10M = 0, 193 PX30_GMAC_SPEED_100M = BIT(2), 194 }; 195 196 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 197 &clk_speed); 198 if (ret) 199 return ret; 200 201 switch (priv->phydev->speed) { 202 case 10: 203 speed = PX30_GMAC_SPEED_10M; 204 ret = clk_set_rate(&clk_speed, 2500000); 205 if (ret) 206 return ret; 207 break; 208 case 100: 209 speed = PX30_GMAC_SPEED_100M; 210 ret = clk_set_rate(&clk_speed, 25000000); 211 if (ret) 212 return ret; 213 break; 214 default: 215 debug("Unknown phy speed: %d\n", priv->phydev->speed); 216 return -EINVAL; 217 } 218 219 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 220 rk_clrsetreg(&grf->mac_con1, PX30_GMAC_SPEED_MASK, speed); 221 222 return 0; 223 } 224 225 static int rk1808_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 226 struct rockchip_eth_dev *dev) 227 { 228 struct dw_eth_dev *priv = &dev->dw; 229 struct clk clk_speed; 230 int ret; 231 232 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 233 &clk_speed); 234 if (ret) 235 return ret; 236 237 switch (priv->phydev->speed) { 238 case 10: 239 ret = clk_set_rate(&clk_speed, 2500000); 240 if (ret) 241 return ret; 242 break; 243 case 100: 244 ret = clk_set_rate(&clk_speed, 25000000); 245 if (ret) 246 return ret; 247 break; 248 case 1000: 249 ret = clk_set_rate(&clk_speed, 125000000); 250 if (ret) 251 return ret; 252 break; 253 default: 254 debug("Unknown phy speed: %d\n", priv->phydev->speed); 255 return -EINVAL; 256 } 257 258 return 0; 259 } 260 261 static int rk3228_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 262 struct rockchip_eth_dev *dev) 263 { 264 struct dw_eth_dev *priv = &dev->dw; 265 struct rk322x_grf *grf; 266 int clk; 267 enum { 268 RK3228_GMAC_CLK_SEL_SHIFT = 8, 269 RK3228_GMAC_CLK_SEL_MASK = GENMASK(9, 8), 270 RK3228_GMAC_CLK_SEL_125M = 0 << 8, 271 RK3228_GMAC_CLK_SEL_25M = 3 << 8, 272 RK3228_GMAC_CLK_SEL_2_5M = 2 << 8, 273 274 RK3228_GMAC_RMII_CLK_MASK = BIT(7), 275 RK3228_GMAC_RMII_CLK_2_5M = 0, 276 RK3228_GMAC_RMII_CLK_25M = BIT(7), 277 278 RK3228_GMAC_RMII_SPEED_MASK = BIT(2), 279 RK3228_GMAC_RMII_SPEED_10 = 0, 280 RK3228_GMAC_RMII_SPEED_100 = BIT(2), 281 }; 282 283 switch (priv->phydev->speed) { 284 case 10: 285 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 286 (RK3228_GMAC_RMII_CLK_2_5M | RK3228_GMAC_RMII_SPEED_10) : 287 RK3228_GMAC_CLK_SEL_2_5M; 288 break; 289 case 100: 290 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 291 (RK3228_GMAC_RMII_CLK_25M | RK3228_GMAC_RMII_SPEED_100) : 292 RK3228_GMAC_CLK_SEL_25M; 293 break; 294 case 1000: 295 clk = RK3228_GMAC_CLK_SEL_125M; 296 break; 297 default: 298 debug("Unknown phy speed: %d\n", priv->phydev->speed); 299 return -EINVAL; 300 } 301 302 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 303 rk_clrsetreg(&grf->mac_con[1], 304 RK3228_GMAC_CLK_SEL_MASK | 305 RK3228_GMAC_RMII_CLK_MASK | 306 RK3228_GMAC_RMII_SPEED_MASK, 307 clk); 308 309 return 0; 310 } 311 312 static int rk3288_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 313 struct rockchip_eth_dev *dev) 314 { 315 struct dw_eth_dev *priv = &dev->dw; 316 struct rk3288_grf *grf; 317 int clk; 318 319 switch (priv->phydev->speed) { 320 case 10: 321 clk = RK3288_GMAC_CLK_SEL_2_5M; 322 break; 323 case 100: 324 clk = RK3288_GMAC_CLK_SEL_25M; 325 break; 326 case 1000: 327 clk = RK3288_GMAC_CLK_SEL_125M; 328 break; 329 default: 330 debug("Unknown phy speed: %d\n", priv->phydev->speed); 331 return -EINVAL; 332 } 333 334 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 335 rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk); 336 337 return 0; 338 } 339 340 static int rk3308_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 341 struct rockchip_eth_dev *dev) 342 { 343 struct dw_eth_dev *priv = &dev->dw; 344 struct rk3308_grf *grf; 345 struct clk clk_speed; 346 int speed, ret; 347 enum { 348 RK3308_GMAC_SPEED_SHIFT = 0x0, 349 RK3308_GMAC_SPEED_MASK = BIT(0), 350 RK3308_GMAC_SPEED_10M = 0, 351 RK3308_GMAC_SPEED_100M = BIT(0), 352 }; 353 354 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 355 &clk_speed); 356 if (ret) 357 return ret; 358 359 switch (priv->phydev->speed) { 360 case 10: 361 speed = RK3308_GMAC_SPEED_10M; 362 ret = clk_set_rate(&clk_speed, 2500000); 363 if (ret) 364 return ret; 365 break; 366 case 100: 367 speed = RK3308_GMAC_SPEED_100M; 368 ret = clk_set_rate(&clk_speed, 25000000); 369 if (ret) 370 return ret; 371 break; 372 default: 373 debug("Unknown phy speed: %d\n", priv->phydev->speed); 374 return -EINVAL; 375 } 376 377 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 378 rk_clrsetreg(&grf->mac_con0, RK3308_GMAC_SPEED_MASK, speed); 379 380 return 0; 381 } 382 383 static int rk3328_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 384 struct rockchip_eth_dev *dev) 385 { 386 struct dw_eth_dev *priv = &dev->dw; 387 struct rk3328_grf_regs *grf; 388 int clk; 389 enum { 390 RK3328_GMAC_CLK_SEL_SHIFT = 11, 391 RK3328_GMAC_CLK_SEL_MASK = GENMASK(12, 11), 392 RK3328_GMAC_CLK_SEL_125M = 0 << 11, 393 RK3328_GMAC_CLK_SEL_25M = 3 << 11, 394 RK3328_GMAC_CLK_SEL_2_5M = 2 << 11, 395 396 RK3328_GMAC_RMII_CLK_MASK = BIT(7), 397 RK3328_GMAC_RMII_CLK_2_5M = 0, 398 RK3328_GMAC_RMII_CLK_25M = BIT(7), 399 400 RK3328_GMAC_RMII_SPEED_MASK = BIT(2), 401 RK3328_GMAC_RMII_SPEED_10 = 0, 402 RK3328_GMAC_RMII_SPEED_100 = BIT(2), 403 }; 404 405 switch (priv->phydev->speed) { 406 case 10: 407 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 408 (RK3328_GMAC_RMII_CLK_2_5M | RK3328_GMAC_RMII_SPEED_10) : 409 RK3328_GMAC_CLK_SEL_2_5M; 410 break; 411 case 100: 412 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 413 (RK3328_GMAC_RMII_CLK_25M | RK3328_GMAC_RMII_SPEED_100) : 414 RK3328_GMAC_CLK_SEL_25M; 415 break; 416 case 1000: 417 clk = RK3328_GMAC_CLK_SEL_125M; 418 break; 419 default: 420 debug("Unknown phy speed: %d\n", priv->phydev->speed); 421 return -EINVAL; 422 } 423 424 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 425 rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1], 426 RK3328_GMAC_CLK_SEL_MASK | 427 RK3328_GMAC_RMII_CLK_MASK | 428 RK3328_GMAC_RMII_SPEED_MASK, 429 clk); 430 431 return 0; 432 } 433 434 static int rk3368_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 435 struct rockchip_eth_dev *dev) 436 { 437 struct dw_eth_dev *priv = &dev->dw; 438 struct rk3368_grf *grf; 439 int clk; 440 enum { 441 RK3368_GMAC_CLK_SEL_2_5M = 2 << 4, 442 RK3368_GMAC_CLK_SEL_25M = 3 << 4, 443 RK3368_GMAC_CLK_SEL_125M = 0 << 4, 444 RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4), 445 }; 446 447 switch (priv->phydev->speed) { 448 case 10: 449 clk = RK3368_GMAC_CLK_SEL_2_5M; 450 break; 451 case 100: 452 clk = RK3368_GMAC_CLK_SEL_25M; 453 break; 454 case 1000: 455 clk = RK3368_GMAC_CLK_SEL_125M; 456 break; 457 default: 458 debug("Unknown phy speed: %d\n", priv->phydev->speed); 459 return -EINVAL; 460 } 461 462 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 463 rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk); 464 465 return 0; 466 } 467 468 static int rk3399_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 469 struct rockchip_eth_dev *dev) 470 { 471 struct dw_eth_dev *priv = &dev->dw; 472 struct rk3399_grf_regs *grf; 473 int clk; 474 475 switch (priv->phydev->speed) { 476 case 10: 477 clk = RK3399_GMAC_CLK_SEL_2_5M; 478 break; 479 case 100: 480 clk = RK3399_GMAC_CLK_SEL_25M; 481 break; 482 case 1000: 483 clk = RK3399_GMAC_CLK_SEL_125M; 484 break; 485 default: 486 debug("Unknown phy speed: %d\n", priv->phydev->speed); 487 return -EINVAL; 488 } 489 490 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 491 rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk); 492 493 return 0; 494 } 495 496 static int rv1108_set_rmii_speed(struct gmac_rockchip_platdata *pdata, 497 struct rockchip_eth_dev *dev) 498 { 499 struct dw_eth_dev *priv = &dev->dw; 500 struct rv1108_grf *grf; 501 int clk, speed; 502 enum { 503 RV1108_GMAC_SPEED_MASK = BIT(2), 504 RV1108_GMAC_SPEED_10M = 0 << 2, 505 RV1108_GMAC_SPEED_100M = 1 << 2, 506 RV1108_GMAC_CLK_SEL_MASK = BIT(7), 507 RV1108_GMAC_CLK_SEL_2_5M = 0 << 7, 508 RV1108_GMAC_CLK_SEL_25M = 1 << 7, 509 }; 510 511 switch (priv->phydev->speed) { 512 case 10: 513 clk = RV1108_GMAC_CLK_SEL_2_5M; 514 speed = RV1108_GMAC_SPEED_10M; 515 break; 516 case 100: 517 clk = RV1108_GMAC_CLK_SEL_25M; 518 speed = RV1108_GMAC_SPEED_100M; 519 break; 520 default: 521 debug("Unknown phy speed: %d\n", priv->phydev->speed); 522 return -EINVAL; 523 } 524 525 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 526 rk_clrsetreg(&grf->gmac_con0, 527 RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK, 528 clk | speed); 529 530 return 0; 531 } 532 #else 533 static int rk3506_set_rmii_speed(struct gmac_rockchip_platdata *pdata, 534 struct rockchip_eth_dev *dev) 535 { 536 struct eqos_priv *priv = &dev->eqos; 537 struct rk3506_grf_reg *grf; 538 unsigned int div; 539 540 enum { 541 RK3506_GMAC_CLK_RMII_DIV_SHIFT = 3, 542 RK3506_GMAC_CLK_RMII_DIV_MASK = BIT(3), 543 RK3506_GMAC_CLK_RMII_DIV2 = BIT(3), 544 RK3506_GMAC_CLK_RMII_DIV20 = 0, 545 }; 546 547 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 548 549 switch (priv->phy->speed) { 550 case 10: 551 div = RK3506_GMAC_CLK_RMII_DIV20; 552 break; 553 case 100: 554 div = RK3506_GMAC_CLK_RMII_DIV2; 555 break; 556 default: 557 debug("Unknown phy speed: %d\n", priv->phy->speed); 558 return -EINVAL; 559 } 560 561 if (pdata->bus_id) 562 rk_clrsetreg(&grf->soc_con11, RK3506_GMAC_CLK_RMII_DIV_MASK, div); 563 else 564 rk_clrsetreg(&grf->soc_con8, RK3506_GMAC_CLK_RMII_DIV_MASK, div); 565 566 return 0; 567 } 568 569 static int rk3528_set_rgmii_speed(struct gmac_rockchip_platdata *pdata, 570 struct rockchip_eth_dev *dev) 571 { 572 struct eqos_priv *priv = &dev->eqos; 573 struct rk3528_grf *grf; 574 unsigned int div; 575 576 enum { 577 RK3528_GMAC0_CLK_RMII_DIV_SHIFT = 3, 578 RK3528_GMAC0_CLK_RMII_DIV_MASK = GENMASK(4, 3), 579 RK3528_GMAC0_CLK_RMII_DIV2 = BIT(3), 580 RK3528_GMAC0_CLK_RMII_DIV20 = 0, 581 }; 582 583 enum { 584 RK3528_GMAC1_CLK_RGMII_DIV_SHIFT = 10, 585 RK3528_GMAC1_CLK_RGMII_DIV_MASK = GENMASK(11, 10), 586 RK3528_GMAC1_CLK_RGMII_DIV1 = 0, 587 RK3528_GMAC1_CLK_RGMII_DIV5 = GENMASK(11, 10), 588 RK3528_GMAC1_CLK_RGMII_DIV50 = BIT(11), 589 RK3528_GMAC1_CLK_RMII_DIV2 = BIT(11), 590 RK3528_GMAC1_CLK_RMII_DIV20 = 0, 591 }; 592 593 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 594 595 switch (priv->phy->speed) { 596 case 10: 597 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) 598 div = pdata->bus_id ? RK3528_GMAC1_CLK_RMII_DIV20 : 599 RK3528_GMAC0_CLK_RMII_DIV20; 600 else 601 div = RK3528_GMAC1_CLK_RGMII_DIV50; 602 break; 603 case 100: 604 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) 605 div = pdata->bus_id ? RK3528_GMAC1_CLK_RMII_DIV2 : 606 RK3528_GMAC0_CLK_RMII_DIV2; 607 else 608 div = RK3528_GMAC1_CLK_RGMII_DIV5; 609 break; 610 case 1000: 611 if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII) 612 div = RK3528_GMAC1_CLK_RGMII_DIV1; 613 else 614 return -EINVAL; 615 break; 616 default: 617 debug("Unknown phy speed: %d\n", priv->phy->speed); 618 return -EINVAL; 619 } 620 621 if (pdata->bus_id) 622 rk_clrsetreg(&grf->gmac1_con0, RK3528_GMAC1_CLK_RGMII_DIV_MASK, div); 623 else 624 rk_clrsetreg(&grf->gmac0_con, RK3528_GMAC0_CLK_RMII_DIV_MASK, div); 625 626 return 0; 627 } 628 629 static int rk3562_set_gmac_speed(struct gmac_rockchip_platdata *pdata, 630 struct rockchip_eth_dev *dev) 631 { 632 struct eqos_priv *priv = &dev->eqos; 633 struct rk3562_grf *grf; 634 unsigned int div; 635 636 enum { 637 RK3562_GMAC0_CLK_RGMII_DIV_SHIFT = 7, 638 RK3562_GMAC0_CLK_RGMII_DIV_MASK = GENMASK(8, 7), 639 RK3562_GMAC0_CLK_RGMII_DIV1 = 0, 640 RK3562_GMAC0_CLK_RGMII_DIV5 = GENMASK(8, 7), 641 RK3562_GMAC0_CLK_RGMII_DIV50 = BIT(8), 642 RK3562_GMAC0_CLK_RMII_DIV2 = BIT(7), 643 RK3562_GMAC0_CLK_RMII_DIV20 = 0, 644 }; 645 646 enum { 647 RK3562_GMAC1_SPEED_SHIFT = 0x0, 648 RK3562_GMAC1_SPEED_MASK = BIT(0), 649 RK3562_GMAC1_SPEED_10M = 0, 650 RK3562_GMAC1_SPEED_100M = BIT(0), 651 }; 652 653 enum { 654 RK3562_GMAC1_CLK_RMII_DIV_SHIFT = 13, 655 RK3562_GMAC1_CLK_RMII_DIV_MASK = BIT(13), 656 RK3562_GMAC1_CLK_RMII_DIV2 = BIT(13), 657 RK3562_GMAC1_CLK_RMII_DIV20 = 0, 658 }; 659 660 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 661 662 switch (priv->phy->speed) { 663 case 10: 664 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) { 665 if (pdata->bus_id > 0) { 666 div = RK3562_GMAC1_CLK_RMII_DIV20; 667 rk_clrsetreg(&grf->soc_con[0], 668 RK3562_GMAC1_SPEED_MASK, 669 RK3562_GMAC1_SPEED_10M); 670 } else { 671 div = RK3562_GMAC0_CLK_RMII_DIV20; 672 } 673 } else { 674 div = RK3562_GMAC0_CLK_RGMII_DIV50; 675 } 676 break; 677 case 100: 678 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) { 679 if (pdata->bus_id > 0) { 680 div = RK3562_GMAC1_CLK_RMII_DIV2; 681 rk_clrsetreg(&grf->soc_con[0], 682 RK3562_GMAC1_SPEED_MASK, 683 RK3562_GMAC1_SPEED_100M); 684 } else { 685 div = RK3562_GMAC0_CLK_RMII_DIV2; 686 } 687 } else { 688 div = RK3562_GMAC0_CLK_RGMII_DIV5; 689 } 690 break; 691 case 1000: 692 if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII) 693 div = RK3562_GMAC0_CLK_RGMII_DIV1; 694 else 695 return -EINVAL; 696 break; 697 default: 698 debug("Unknown phy speed: %d\n", priv->phy->speed); 699 return -EINVAL; 700 } 701 702 if (pdata->bus_id) 703 rk_clrsetreg(&grf->soc_con[1], RK3562_GMAC1_CLK_RMII_DIV_MASK, div); 704 else 705 rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_CLK_RGMII_DIV_MASK, div); 706 707 return 0; 708 } 709 710 static int rk3576_set_rgmii_speed(struct gmac_rockchip_platdata *pdata, 711 struct rockchip_eth_dev *dev) 712 { 713 struct eqos_priv *priv = &dev->eqos; 714 struct rk3576_sdgmac_grf_reg *s_grf; 715 unsigned int div, div_mask; 716 717 enum { 718 RK3576_GMAC_CLK_RGMII_DIV_MASK = GENMASK(6, 5), 719 RK3576_GMAC_CLK_RGMII_DIV1 = 0, 720 RK3576_GMAC_CLK_RGMII_DIV5 = GENMASK(6, 5), 721 RK3576_GMAC_CLK_RGMII_DIV50 = BIT(6), 722 RK3576_GMAC_CLK_RMII_DIV2 = BIT(5), 723 RK3576_GMAC_CLK_RMII_DIV20 = 0, 724 }; 725 726 s_grf = syscon_get_first_range(ROCKCHIP_SYSCON_SDGMAC_GRF); 727 728 switch (priv->phy->speed) { 729 case 10: 730 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) 731 div = RK3576_GMAC_CLK_RMII_DIV20; 732 else 733 div = RK3576_GMAC_CLK_RGMII_DIV50; 734 break; 735 case 100: 736 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) 737 div = RK3576_GMAC_CLK_RMII_DIV2; 738 else 739 div = RK3576_GMAC_CLK_RGMII_DIV5; 740 break; 741 case 1000: 742 if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII) 743 div = RK3576_GMAC_CLK_RGMII_DIV1; 744 else 745 return -EINVAL; 746 break; 747 default: 748 debug("Unknown phy speed: %d\n", priv->phy->speed); 749 return -EINVAL; 750 } 751 752 div_mask = RK3576_GMAC_CLK_RGMII_DIV_MASK; 753 754 if (pdata->bus_id == 1) 755 rk_clrsetreg(&s_grf->gmac1_con, div_mask, div); 756 else 757 rk_clrsetreg(&s_grf->gmac0_con, div_mask, div); 758 759 return 0; 760 } 761 762 static int rk3588_set_rgmii_speed(struct gmac_rockchip_platdata *pdata, 763 struct rockchip_eth_dev *dev) 764 { 765 struct eqos_priv *priv = &dev->eqos; 766 struct rk3588_php_grf *php_grf; 767 unsigned int div, div_mask; 768 769 enum { 770 RK3588_GMAC_CLK_RGMII_DIV_SHIFT = 2, 771 RK3588_GMAC_CLK_RGMII_DIV_MASK = GENMASK(3, 2), 772 RK3588_GMAC_CLK_RGMII_DIV1 = 0, 773 RK3588_GMAC_CLK_RGMII_DIV5 = GENMASK(3, 2), 774 RK3588_GMAC_CLK_RGMII_DIV50 = BIT(3), 775 RK3588_GMAC_CLK_RMII_DIV2 = BIT(2), 776 RK3588_GMAC_CLK_RMII_DIV20 = 0, 777 RK3588_GMAC1_ID_SHIFT = 5, 778 }; 779 780 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 781 782 switch (priv->phy->speed) { 783 case 10: 784 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) 785 div = RK3588_GMAC_CLK_RMII_DIV20; 786 else 787 div = RK3588_GMAC_CLK_RGMII_DIV50; 788 break; 789 case 100: 790 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) 791 div = RK3588_GMAC_CLK_RMII_DIV2; 792 else 793 div = RK3588_GMAC_CLK_RGMII_DIV5; 794 break; 795 case 1000: 796 if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII) 797 div = RK3588_GMAC_CLK_RGMII_DIV1; 798 else 799 return -EINVAL; 800 break; 801 default: 802 debug("Unknown phy speed: %d\n", priv->phy->speed); 803 return -EINVAL; 804 } 805 806 if (pdata->bus_id == 1) { 807 div <<= 5; 808 div_mask = RK3588_GMAC_CLK_RGMII_DIV_MASK << 5; 809 } 810 811 div <<= pdata->bus_id ? RK3588_GMAC1_ID_SHIFT : 0; 812 div_mask = pdata->bus_id ? (RK3588_GMAC_CLK_RGMII_DIV_MASK << 5) : 813 RK3588_GMAC_CLK_RGMII_DIV_MASK; 814 815 rk_clrsetreg(&php_grf->clk_con1, div_mask, div); 816 817 return 0; 818 } 819 820 static int rv1106_set_rmii_speed(struct gmac_rockchip_platdata *pdata, 821 struct rockchip_eth_dev *dev) 822 { 823 struct eqos_priv *priv = &dev->eqos; 824 #ifdef CONFIG_ROCKCHIP_RV1103B 825 struct rv1103b_grf *grf; 826 #else 827 struct rv1106_grf *grf; 828 #endif 829 unsigned int div; 830 831 enum { 832 RV1106_GMAC_CLK_RMII_DIV_SHIFT = 2, 833 RV1106_GMAC_CLK_RMII_DIV_MASK = GENMASK(3, 2), 834 RV1106_GMAC_CLK_RMII_DIV2 = BIT(2), 835 RV1106_GMAC_CLK_RMII_DIV20 = 0, 836 }; 837 838 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 839 840 switch (priv->phy->speed) { 841 case 10: 842 div = RV1106_GMAC_CLK_RMII_DIV20; 843 break; 844 case 100: 845 div = RV1106_GMAC_CLK_RMII_DIV2; 846 break; 847 default: 848 debug("Unknown phy speed: %d\n", priv->phy->speed); 849 return -EINVAL; 850 } 851 852 rk_clrsetreg(&grf->gmac_clk_con, RV1106_GMAC_CLK_RMII_DIV_MASK, div); 853 854 return 0; 855 } 856 857 static int rv1126_set_rgmii_speed(struct gmac_rockchip_platdata *pdata, 858 struct rockchip_eth_dev *dev) 859 { 860 struct eqos_priv *priv = &dev->eqos; 861 struct clk clk_speed; 862 int ret; 863 864 ret = clk_get_by_name(priv->phy->dev, "clk_mac_speed", 865 &clk_speed); 866 if (ret) { 867 printf("%s can't get clk_mac_speed clock (ret=%d):\n", 868 __func__, ret); 869 return ret; 870 } 871 872 switch ( priv->phy->speed) { 873 case 10: 874 ret = clk_set_rate(&clk_speed, 2500000); 875 if (ret) 876 return ret; 877 break; 878 case 100: 879 ret = clk_set_rate(&clk_speed, 25000000); 880 if (ret) 881 return ret; 882 break; 883 case 1000: 884 ret = clk_set_rate(&clk_speed, 125000000); 885 if (ret) 886 return ret; 887 break; 888 default: 889 debug("Unknown phy speed: %d\n", priv->phy->speed); 890 return -EINVAL; 891 } 892 893 return 0; 894 } 895 #endif 896 897 #ifndef CONFIG_DWC_ETH_QOS 898 static void px30_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 899 { 900 struct px30_grf *grf; 901 enum { 902 px30_GMAC_PHY_INTF_SEL_SHIFT = 4, 903 px30_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 6), 904 px30_GMAC_PHY_INTF_SEL_RMII = BIT(6), 905 }; 906 907 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 908 909 rk_clrsetreg(&grf->mac_con1, 910 px30_GMAC_PHY_INTF_SEL_MASK, 911 px30_GMAC_PHY_INTF_SEL_RMII); 912 } 913 914 static void rk1808_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 915 { 916 struct rk1808_grf *grf; 917 enum { 918 RK1808_GMAC_PHY_INTF_SEL_SHIFT = 4, 919 RK1808_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 920 RK1808_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 921 922 RK1808_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 923 RK1808_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 924 RK1808_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 925 926 RK1808_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 927 RK1808_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 928 RK1808_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 929 }; 930 enum { 931 RK1808_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 932 RK1808_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 7), 933 934 RK1808_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 935 RK1808_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 936 }; 937 938 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 939 rk_clrsetreg(&grf->mac_con1, 940 RK1808_GMAC_PHY_INTF_SEL_MASK | 941 RK1808_RXCLK_DLY_ENA_GMAC_MASK | 942 RK1808_TXCLK_DLY_ENA_GMAC_MASK, 943 RK1808_GMAC_PHY_INTF_SEL_RGMII | 944 RK1808_RXCLK_DLY_ENA_GMAC_ENABLE | 945 RK1808_TXCLK_DLY_ENA_GMAC_ENABLE); 946 947 rk_clrsetreg(&grf->mac_con0, 948 RK1808_CLK_RX_DL_CFG_GMAC_MASK | 949 RK1808_CLK_TX_DL_CFG_GMAC_MASK, 950 (pdata->rx_delay << RK1808_CLK_RX_DL_CFG_GMAC_SHIFT) | 951 (pdata->tx_delay << RK1808_CLK_TX_DL_CFG_GMAC_SHIFT)); 952 } 953 954 static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 955 { 956 struct rk322x_grf *grf; 957 enum { 958 RK3228_RMII_MODE_SHIFT = 10, 959 RK3228_RMII_MODE_MASK = BIT(10), 960 961 RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4, 962 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 963 RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 964 965 RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 966 RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 967 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 968 969 RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 970 RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 971 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 972 }; 973 enum { 974 RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 975 RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 976 977 RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 978 RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 979 }; 980 981 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 982 rk_clrsetreg(&grf->mac_con[1], 983 RK3228_RMII_MODE_MASK | 984 RK3228_GMAC_PHY_INTF_SEL_MASK | 985 RK3228_RXCLK_DLY_ENA_GMAC_MASK | 986 RK3228_TXCLK_DLY_ENA_GMAC_MASK, 987 RK3228_GMAC_PHY_INTF_SEL_RGMII | 988 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE | 989 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE); 990 991 rk_clrsetreg(&grf->mac_con[0], 992 RK3228_CLK_RX_DL_CFG_GMAC_MASK | 993 RK3228_CLK_TX_DL_CFG_GMAC_MASK, 994 pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT | 995 pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT); 996 } 997 998 static void rk3228_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 999 { 1000 struct rk322x_grf *grf; 1001 enum { 1002 RK3228_GRF_CON_RMII_MODE_MASK = BIT(11), 1003 RK3228_GRF_CON_RMII_MODE_SEL = BIT(11), 1004 RK3228_RMII_MODE_MASK = BIT(10), 1005 RK3228_RMII_MODE_SEL = BIT(10), 1006 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1007 RK3228_GMAC_PHY_INTF_SEL_RMII = BIT(6), 1008 }; 1009 1010 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1011 rk_clrsetreg(&grf->mac_con[1], 1012 RK3228_GRF_CON_RMII_MODE_MASK | 1013 RK3228_RMII_MODE_MASK | 1014 RK3228_GMAC_PHY_INTF_SEL_MASK, 1015 RK3228_GRF_CON_RMII_MODE_SEL | 1016 RK3228_RMII_MODE_SEL | 1017 RK3228_GMAC_PHY_INTF_SEL_RMII); 1018 } 1019 1020 static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1021 { 1022 struct rk3288_grf *grf; 1023 1024 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1025 rk_clrsetreg(&grf->soc_con1, 1026 RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK, 1027 RK3288_GMAC_PHY_INTF_SEL_RGMII); 1028 1029 rk_clrsetreg(&grf->soc_con3, 1030 RK3288_RXCLK_DLY_ENA_GMAC_MASK | 1031 RK3288_TXCLK_DLY_ENA_GMAC_MASK | 1032 RK3288_CLK_RX_DL_CFG_GMAC_MASK | 1033 RK3288_CLK_TX_DL_CFG_GMAC_MASK, 1034 RK3288_RXCLK_DLY_ENA_GMAC_ENABLE | 1035 RK3288_TXCLK_DLY_ENA_GMAC_ENABLE | 1036 pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT | 1037 pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT); 1038 } 1039 1040 static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1041 { 1042 struct rk3308_grf *grf; 1043 enum { 1044 RK3308_GMAC_PHY_INTF_SEL_SHIFT = 2, 1045 RK3308_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 2), 1046 RK3308_GMAC_PHY_INTF_SEL_RMII = BIT(4), 1047 }; 1048 1049 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1050 1051 rk_clrsetreg(&grf->mac_con0, 1052 RK3308_GMAC_PHY_INTF_SEL_MASK, 1053 RK3308_GMAC_PHY_INTF_SEL_RMII); 1054 } 1055 1056 static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1057 { 1058 struct rk3328_grf_regs *grf; 1059 enum { 1060 RK3328_RMII_MODE_SHIFT = 9, 1061 RK3328_RMII_MODE_MASK = BIT(9), 1062 1063 RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4, 1064 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1065 RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 1066 1067 RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 1068 RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 1069 RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 1070 1071 RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 1072 RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 1073 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 1074 }; 1075 enum { 1076 RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 1077 RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 1078 1079 RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1080 RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 1081 }; 1082 1083 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1084 rk_clrsetreg(&grf->mac_con[1], 1085 RK3328_RMII_MODE_MASK | 1086 RK3328_GMAC_PHY_INTF_SEL_MASK | 1087 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 1088 RK3328_TXCLK_DLY_ENA_GMAC_MASK, 1089 RK3328_GMAC_PHY_INTF_SEL_RGMII | 1090 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 1091 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE); 1092 1093 rk_clrsetreg(&grf->mac_con[0], 1094 RK3328_CLK_RX_DL_CFG_GMAC_MASK | 1095 RK3328_CLK_TX_DL_CFG_GMAC_MASK, 1096 pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT | 1097 pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT); 1098 } 1099 1100 static void rk3328_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1101 { 1102 struct rk3328_grf_regs *grf; 1103 enum { 1104 RK3328_RMII_MODE_MASK = BIT(9), 1105 RK3328_RMII_MODE = BIT(9), 1106 1107 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1108 RK3328_GMAC_PHY_INTF_SEL_RMII = BIT(6), 1109 }; 1110 1111 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1112 rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1], 1113 RK3328_RMII_MODE_MASK | 1114 RK3328_GMAC_PHY_INTF_SEL_MASK, 1115 RK3328_GMAC_PHY_INTF_SEL_RMII | 1116 RK3328_RMII_MODE); 1117 } 1118 1119 static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1120 { 1121 struct rk3368_grf *grf; 1122 enum { 1123 RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9, 1124 RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9), 1125 RK3368_RMII_MODE_MASK = BIT(6), 1126 RK3368_RMII_MODE = BIT(6), 1127 }; 1128 enum { 1129 RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15), 1130 RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 1131 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15), 1132 RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7), 1133 RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 1134 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7), 1135 RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8, 1136 RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 1137 RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0, 1138 RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 1139 }; 1140 1141 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1142 rk_clrsetreg(&grf->soc_con15, 1143 RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK, 1144 RK3368_GMAC_PHY_INTF_SEL_RGMII); 1145 1146 rk_clrsetreg(&grf->soc_con16, 1147 RK3368_RXCLK_DLY_ENA_GMAC_MASK | 1148 RK3368_TXCLK_DLY_ENA_GMAC_MASK | 1149 RK3368_CLK_RX_DL_CFG_GMAC_MASK | 1150 RK3368_CLK_TX_DL_CFG_GMAC_MASK, 1151 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE | 1152 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE | 1153 (pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT) | 1154 (pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT)); 1155 } 1156 1157 static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1158 { 1159 struct rk3399_grf_regs *grf; 1160 1161 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1162 1163 rk_clrsetreg(&grf->soc_con5, 1164 RK3399_GMAC_PHY_INTF_SEL_MASK, 1165 RK3399_GMAC_PHY_INTF_SEL_RGMII); 1166 1167 rk_clrsetreg(&grf->soc_con6, 1168 RK3399_RXCLK_DLY_ENA_GMAC_MASK | 1169 RK3399_TXCLK_DLY_ENA_GMAC_MASK | 1170 RK3399_CLK_RX_DL_CFG_GMAC_MASK | 1171 RK3399_CLK_TX_DL_CFG_GMAC_MASK, 1172 RK3399_RXCLK_DLY_ENA_GMAC_ENABLE | 1173 RK3399_TXCLK_DLY_ENA_GMAC_ENABLE | 1174 (pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT) | 1175 (pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT)); 1176 } 1177 1178 static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1179 { 1180 struct rv1108_grf *grf; 1181 1182 enum { 1183 RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1184 RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4, 1185 }; 1186 1187 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1188 rk_clrsetreg(&grf->gmac_con0, 1189 RV1108_GMAC_PHY_INTF_SEL_MASK, 1190 RV1108_GMAC_PHY_INTF_SEL_RMII); 1191 } 1192 1193 static void rk3228_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 1194 { 1195 struct rk322x_grf *grf; 1196 enum { 1197 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK = BIT(15), 1198 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY = BIT(15), 1199 }; 1200 enum { 1201 RK3228_MACPHY_CFG_CLK_50M_MASK = BIT(14), 1202 RK3228_MACPHY_CFG_CLK_50M = BIT(14), 1203 1204 RK3228_MACPHY_RMII_MODE_MASK = GENMASK(7, 6), 1205 RK3228_MACPHY_RMII_MODE = BIT(6), 1206 1207 RK3228_MACPHY_ENABLE_MASK = BIT(0), 1208 RK3228_MACPHY_DISENABLE = 0, 1209 RK3228_MACPHY_ENABLE = BIT(0), 1210 }; 1211 enum { 1212 RK3228_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0), 1213 RK3228_RK_GRF_CON2_MACPHY_ID = 0x1234, 1214 }; 1215 enum { 1216 RK3228_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0), 1217 RK3228_RK_GRF_CON3_MACPHY_ID = 0x35, 1218 }; 1219 1220 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1221 rk_clrsetreg(&grf->con_iomux, 1222 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK, 1223 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY); 1224 1225 rk_clrsetreg(&grf->macphy_con[2], 1226 RK3228_RK_GRF_CON2_MACPHY_ID_MASK, 1227 RK3228_RK_GRF_CON2_MACPHY_ID); 1228 1229 rk_clrsetreg(&grf->macphy_con[3], 1230 RK3228_RK_GRF_CON3_MACPHY_ID_MASK, 1231 RK3228_RK_GRF_CON3_MACPHY_ID); 1232 1233 /* disabled before trying to reset it &*/ 1234 rk_clrsetreg(&grf->macphy_con[0], 1235 RK3228_MACPHY_CFG_CLK_50M_MASK | 1236 RK3228_MACPHY_RMII_MODE_MASK | 1237 RK3228_MACPHY_ENABLE_MASK, 1238 RK3228_MACPHY_CFG_CLK_50M | 1239 RK3228_MACPHY_RMII_MODE | 1240 RK3228_MACPHY_DISENABLE); 1241 1242 reset_assert(&pdata->phy_reset); 1243 udelay(10); 1244 reset_deassert(&pdata->phy_reset); 1245 udelay(10); 1246 1247 rk_clrsetreg(&grf->macphy_con[0], 1248 RK3228_MACPHY_ENABLE_MASK, 1249 RK3228_MACPHY_ENABLE); 1250 udelay(30 * 1000); 1251 } 1252 1253 static void rk3328_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 1254 { 1255 struct rk3328_grf_regs *grf; 1256 enum { 1257 RK3328_GRF_CON_RMII_MODE_MASK = BIT(9), 1258 RK3328_GRF_CON_RMII_MODE = BIT(9), 1259 }; 1260 enum { 1261 RK3328_MACPHY_CFG_CLK_50M_MASK = BIT(14), 1262 RK3328_MACPHY_CFG_CLK_50M = BIT(14), 1263 1264 RK3328_MACPHY_RMII_MODE_MASK = GENMASK(7, 6), 1265 RK3328_MACPHY_RMII_MODE = BIT(6), 1266 1267 RK3328_MACPHY_ENABLE_MASK = BIT(0), 1268 RK3328_MACPHY_DISENABLE = 0, 1269 RK3328_MACPHY_ENABLE = BIT(0), 1270 }; 1271 enum { 1272 RK3328_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0), 1273 RK3328_RK_GRF_CON2_MACPHY_ID = 0x1234, 1274 }; 1275 enum { 1276 RK3328_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0), 1277 RK3328_RK_GRF_CON3_MACPHY_ID = 0x35, 1278 }; 1279 1280 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1281 rk_clrsetreg(&grf->macphy_con[1], 1282 RK3328_GRF_CON_RMII_MODE_MASK, 1283 RK3328_GRF_CON_RMII_MODE); 1284 1285 rk_clrsetreg(&grf->macphy_con[2], 1286 RK3328_RK_GRF_CON2_MACPHY_ID_MASK, 1287 RK3328_RK_GRF_CON2_MACPHY_ID); 1288 1289 rk_clrsetreg(&grf->macphy_con[3], 1290 RK3328_RK_GRF_CON3_MACPHY_ID_MASK, 1291 RK3328_RK_GRF_CON3_MACPHY_ID); 1292 1293 /* disabled before trying to reset it &*/ 1294 rk_clrsetreg(&grf->macphy_con[0], 1295 RK3328_MACPHY_CFG_CLK_50M_MASK | 1296 RK3328_MACPHY_RMII_MODE_MASK | 1297 RK3328_MACPHY_ENABLE_MASK, 1298 RK3328_MACPHY_CFG_CLK_50M | 1299 RK3328_MACPHY_RMII_MODE | 1300 RK3328_MACPHY_DISENABLE); 1301 1302 reset_assert(&pdata->phy_reset); 1303 udelay(10); 1304 reset_deassert(&pdata->phy_reset); 1305 udelay(10); 1306 1307 rk_clrsetreg(&grf->macphy_con[0], 1308 RK3328_MACPHY_ENABLE_MASK, 1309 RK3328_MACPHY_ENABLE); 1310 udelay(30 * 1000); 1311 } 1312 1313 #else 1314 static void rk3506_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1315 { 1316 unsigned int clk_mode; 1317 struct rk3506_grf_reg *grf; 1318 1319 enum { 1320 RK3506_GMAC_CLK_RMII_MODE_SHIFT = 0x1, 1321 RK3506_GMAC_CLK_RMII_MODE_MASK = BIT(1), 1322 RK3506_GMAC_CLK_RMII_MODE = BIT(1), 1323 }; 1324 1325 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1326 clk_mode = RK3506_GMAC_CLK_RMII_MODE; 1327 1328 if (pdata->bus_id == 1) 1329 rk_clrsetreg(&grf->soc_con11, RK3506_GMAC_CLK_RMII_MODE_MASK, clk_mode); 1330 else 1331 rk_clrsetreg(&grf->soc_con8, RK3506_GMAC_CLK_RMII_MODE_MASK, clk_mode); 1332 } 1333 1334 static void rk3528_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 1335 { 1336 struct rk3528_grf *grf; 1337 unsigned char bgs[1] = {0}; 1338 1339 enum { 1340 RK3528_MACPHY_ENABLE_MASK = BIT(1), 1341 RK3528_MACPHY_DISENABLE = BIT(1), 1342 RK3528_MACPHY_ENABLE = 0, 1343 RK3528_MACPHY_XMII_SEL_MASK = GENMASK(6, 5), 1344 RK3528_MACPHY_XMII_SEL = BIT(6), 1345 RK3528_MACPHY_24M_CLK_SEL_MASK = GENMASK(9, 7), 1346 RK3528_MACPHY_24M_CLK_SEL_24M = (BIT(8) | BIT(9)), 1347 RK3528_MACPHY_PHY_ID_MASK = GENMASK(14, 10), 1348 RK3528_MACPHY_PHY_ID = BIT(11), 1349 }; 1350 1351 enum { 1352 RK3528_MACPHY_BGS_MASK = GENMASK(3, 0), 1353 }; 1354 1355 #if defined(CONFIG_ROCKCHIP_EFUSE) || defined(CONFIG_ROCKCHIP_OTP) 1356 struct udevice *dev; 1357 u32 regs[2] = {0}; 1358 ofnode node; 1359 int ret = 0; 1360 1361 /* retrieve the device */ 1362 if (IS_ENABLED(CONFIG_ROCKCHIP_EFUSE)) 1363 ret = uclass_get_device_by_driver(UCLASS_MISC, 1364 DM_GET_DRIVER(rockchip_efuse), 1365 &dev); 1366 else 1367 ret = uclass_get_device_by_driver(UCLASS_MISC, 1368 DM_GET_DRIVER(rockchip_otp), 1369 &dev); 1370 if (!ret) { 1371 node = dev_read_subnode(dev, "macphy-bgs"); 1372 if (ofnode_valid(node)) { 1373 if (!ofnode_read_u32_array(node, "reg", regs, 2)) { 1374 /* read the bgs from the efuses */ 1375 ret = misc_read(dev, regs[0], &bgs, 1); 1376 if (ret) { 1377 printf("read bgs from efuse/otp failed, ret=%d\n", 1378 ret); 1379 bgs[0] = 0; 1380 } 1381 } 1382 } 1383 } 1384 #endif 1385 1386 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1387 1388 reset_assert(&pdata->phy_reset); 1389 udelay(20); 1390 rk_clrsetreg(&grf->macphy_con0, 1391 RK3528_MACPHY_ENABLE_MASK | 1392 RK3528_MACPHY_XMII_SEL_MASK | 1393 RK3528_MACPHY_24M_CLK_SEL_MASK | 1394 RK3528_MACPHY_PHY_ID_MASK, 1395 RK3528_MACPHY_ENABLE | 1396 RK3528_MACPHY_XMII_SEL | 1397 RK3528_MACPHY_24M_CLK_SEL_24M | 1398 RK3528_MACPHY_PHY_ID); 1399 1400 rk_clrsetreg(&grf->macphy_con1, 1401 RK3528_MACPHY_BGS_MASK, 1402 bgs[0]); 1403 udelay(20); 1404 reset_deassert(&pdata->phy_reset); 1405 udelay(30 * 1000); 1406 } 1407 1408 static void rk3528_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1409 { 1410 unsigned int clk_mode; 1411 struct rk3528_grf *grf; 1412 1413 enum { 1414 RK3528_GMAC0_CLK_RMII_MODE_SHIFT = 0x1, 1415 RK3528_GMAC0_CLK_RMII_MODE_MASK = BIT(1), 1416 RK3528_GMAC0_CLK_RMII_MODE = 0x1, 1417 }; 1418 1419 enum { 1420 RK3528_GMAC1_CLK_RMII_MODE_SHIFT = 0x8, 1421 RK3528_GMAC1_CLK_RMII_MODE_MASK = BIT(8), 1422 RK3528_GMAC1_CLK_RMII_MODE = 0x1, 1423 }; 1424 1425 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1426 1427 if (pdata->bus_id == 1) { 1428 clk_mode = RK3528_GMAC1_CLK_RMII_MODE << RK3528_GMAC1_CLK_RMII_MODE_SHIFT; 1429 rk_clrsetreg(&grf->gmac1_con1, RK3528_GMAC1_CLK_RMII_MODE_MASK, clk_mode); 1430 } else { 1431 clk_mode = RK3528_GMAC0_CLK_RMII_MODE << RK3528_GMAC0_CLK_RMII_MODE_SHIFT; 1432 rk_clrsetreg(&grf->gmac0_con, RK3528_GMAC0_CLK_RMII_MODE_MASK, clk_mode); 1433 } 1434 } 1435 1436 static void rk3528_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1437 { 1438 unsigned int rx_enable; 1439 unsigned int rx_delay; 1440 struct rk3528_grf *grf; 1441 1442 enum { 1443 RK3528_GMAC1_RGMII_MODE_SHIFT = 0x8, 1444 RK3528_GMAC1_RGMII_MODE_MASK = BIT(8), 1445 RK3528_GMAC1_RGMII_MODE = 0x0, 1446 1447 RK3528_GMAC1_TXCLK_DLY_ENA_MASK = BIT(14), 1448 RK3528_GMAC1_TXCLK_DLY_ENA_DISABLE = 0, 1449 RK3528_GMAC1_TXCLK_DLY_ENA_ENABLE = BIT(14), 1450 1451 RK3528_GMAC1_RXCLK_DLY_ENA_MASK = BIT(15), 1452 RK3528_GMAC1_RXCLK_DLY_ENA_DISABLE = 0, 1453 RK3528_GMAC1_RXCLK_DLY_ENA_ENABLE = BIT(15), 1454 }; 1455 1456 enum { 1457 RK3528_GMAC1_RX_DL_CFG_SHIFT = 0x8, 1458 RK3528_GMAC1_RX_DL_CFG_MASK = GENMASK(15, 8), 1459 1460 RK3528_GMAC1_TX_DL_CFG_SHIFT = 0x0, 1461 RK3528_GMAC1_TX_DL_CFG_MASK = GENMASK(7, 0), 1462 }; 1463 1464 if (!pdata->bus_id) 1465 return; 1466 1467 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1468 1469 if (pdata->rx_delay < 0) { 1470 rx_enable = RK3528_GMAC1_RXCLK_DLY_ENA_DISABLE; 1471 rx_delay = 0; 1472 } else { 1473 rx_enable = RK3528_GMAC1_RXCLK_DLY_ENA_ENABLE; 1474 rx_delay = pdata->rx_delay << RK3528_GMAC1_RX_DL_CFG_SHIFT; 1475 } 1476 1477 rk_clrsetreg(&grf->gmac1_con0, 1478 RK3528_GMAC1_TXCLK_DLY_ENA_MASK | 1479 RK3528_GMAC1_RXCLK_DLY_ENA_MASK | 1480 RK3528_GMAC1_RGMII_MODE_MASK, 1481 rx_enable | RK3528_GMAC1_TXCLK_DLY_ENA_ENABLE | 1482 (RK3528_GMAC1_RGMII_MODE << RK3528_GMAC1_RGMII_MODE_SHIFT)); 1483 1484 rk_clrsetreg(&grf->gmac1_con1, 1485 RK3528_GMAC1_RX_DL_CFG_MASK | 1486 RK3528_GMAC1_TX_DL_CFG_MASK, 1487 (pdata->tx_delay << RK3528_GMAC1_TX_DL_CFG_SHIFT) | 1488 rx_delay); 1489 } 1490 1491 static void rk3562_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1492 { 1493 struct rk3562_grf *grf; 1494 unsigned int mode; 1495 1496 enum { 1497 RK3562_GMAC0_RMII_MODE_SHIFT = 0x5, 1498 RK3562_GMAC0_RMII_MODE_MASK = BIT(5), 1499 RK3562_GMAC0_RMII_MODE = 0x1, 1500 }; 1501 1502 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1503 1504 if (!pdata->bus_id) { 1505 mode = RK3562_GMAC0_RMII_MODE << RK3562_GMAC0_RMII_MODE_SHIFT; 1506 rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_RMII_MODE_MASK, mode); 1507 } 1508 } 1509 1510 static void rk3562_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1511 { 1512 struct rk3562_grf *grf; 1513 struct rk3562_ioc *ioc; 1514 unsigned int rx_enable; 1515 unsigned int rx_delay; 1516 1517 enum { 1518 RK3562_GMAC0_RGMII_MODE_SHIFT = 0x5, 1519 RK3562_GMAC0_RGMII_MODE_MASK = BIT(5), 1520 RK3562_GMAC0_RGMII_MODE = 0x0, 1521 1522 RK3562_GMAC0_TXCLK_DLY_ENA_MASK = BIT(0), 1523 RK3562_GMAC0_TXCLK_DLY_ENA_DISABLE = 0, 1524 RK3562_GMAC0_TXCLK_DLY_ENA_ENABLE = BIT(0), 1525 1526 RK3562_GMAC0_RXCLK_DLY_ENA_MASK = BIT(1), 1527 RK3562_GMAC0_RXCLK_DLY_ENA_DISABLE = 0, 1528 RK3562_GMAC0_RXCLK_DLY_ENA_ENABLE = BIT(1), 1529 }; 1530 1531 enum { 1532 RK3562_GMAC0_RX_DL_CFG_SHIFT = 0x8, 1533 RK3562_GMAC0_RX_DL_CFG_MASK = GENMASK(15, 8), 1534 1535 RK3562_GMAC0_TX_DL_CFG_SHIFT = 0x0, 1536 RK3562_GMAC0_TX_DL_CFG_MASK = GENMASK(7, 0), 1537 }; 1538 1539 if (pdata->bus_id) 1540 return; 1541 1542 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1543 ioc = syscon_get_first_range(ROCKCHIP_SYSCON_IOC); 1544 1545 rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_RGMII_MODE_MASK, 1546 RK3562_GMAC0_RGMII_MODE << RK3562_GMAC0_RGMII_MODE_SHIFT); 1547 1548 if (pdata->rx_delay < 0) { 1549 rx_enable = RK3562_GMAC0_RXCLK_DLY_ENA_DISABLE; 1550 rx_delay = 0; 1551 } else { 1552 rx_enable = RK3562_GMAC0_RXCLK_DLY_ENA_ENABLE; 1553 rx_delay = pdata->rx_delay << RK3562_GMAC0_RX_DL_CFG_SHIFT; 1554 } 1555 1556 rk_clrsetreg(&ioc->mac0_io_con1, 1557 RK3562_GMAC0_TXCLK_DLY_ENA_MASK | 1558 RK3562_GMAC0_RXCLK_DLY_ENA_MASK, 1559 rx_enable | RK3562_GMAC0_TXCLK_DLY_ENA_ENABLE); 1560 1561 rk_clrsetreg(&ioc->mac0_io_con0, 1562 RK3562_GMAC0_RX_DL_CFG_MASK | 1563 RK3562_GMAC0_TX_DL_CFG_MASK, 1564 (pdata->tx_delay << RK3562_GMAC0_TX_DL_CFG_SHIFT) | 1565 rx_delay); 1566 1567 rk_clrsetreg(&ioc->mac1_io_con1, 1568 RK3562_GMAC0_TXCLK_DLY_ENA_MASK | 1569 RK3562_GMAC0_RXCLK_DLY_ENA_MASK, 1570 rx_enable | RK3562_GMAC0_TXCLK_DLY_ENA_ENABLE); 1571 1572 rk_clrsetreg(&ioc->mac1_io_con0, 1573 RK3562_GMAC0_RX_DL_CFG_MASK | 1574 RK3562_GMAC0_TX_DL_CFG_MASK, 1575 (pdata->tx_delay << RK3562_GMAC0_TX_DL_CFG_SHIFT) | 1576 rx_delay); 1577 } 1578 1579 static void rk3568_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1580 { 1581 struct rk3568_grf *grf; 1582 void *con1; 1583 1584 enum { 1585 RK3568_GMAC_PHY_INTF_SEL_SHIFT = 4, 1586 RK3568_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1587 RK3568_GMAC_PHY_INTF_SEL_RMII = BIT(6), 1588 }; 1589 1590 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1591 1592 if (pdata->bus_id == 1) 1593 con1 = &grf->mac1_con1; 1594 else 1595 con1 = &grf->mac0_con1; 1596 1597 rk_clrsetreg(con1, 1598 RK3568_GMAC_PHY_INTF_SEL_MASK, 1599 RK3568_GMAC_PHY_INTF_SEL_RMII); 1600 } 1601 1602 static void rk3568_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1603 { 1604 struct rk3568_grf *grf; 1605 void *con0, *con1; 1606 1607 enum { 1608 RK3568_GMAC_PHY_INTF_SEL_SHIFT = 4, 1609 RK3568_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1610 RK3568_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 1611 1612 RK3568_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 1613 RK3568_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 1614 RK3568_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 1615 1616 RK3568_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 1617 RK3568_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 1618 RK3568_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 1619 }; 1620 1621 enum { 1622 RK3568_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1623 RK3568_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 8), 1624 1625 RK3568_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1626 RK3568_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 1627 }; 1628 1629 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1630 1631 if (pdata->bus_id == 1) { 1632 con0 = &grf->mac1_con0; 1633 con1 = &grf->mac1_con1; 1634 } else { 1635 con0 = &grf->mac0_con0; 1636 con1 = &grf->mac0_con1; 1637 } 1638 1639 rk_clrsetreg(con0, 1640 RK3568_CLK_RX_DL_CFG_GMAC_MASK | 1641 RK3568_CLK_TX_DL_CFG_GMAC_MASK, 1642 (pdata->rx_delay << RK3568_CLK_RX_DL_CFG_GMAC_SHIFT) | 1643 (pdata->tx_delay << RK3568_CLK_TX_DL_CFG_GMAC_SHIFT)); 1644 1645 rk_clrsetreg(con1, 1646 RK3568_TXCLK_DLY_ENA_GMAC_MASK | 1647 RK3568_RXCLK_DLY_ENA_GMAC_MASK | 1648 RK3568_GMAC_PHY_INTF_SEL_MASK, 1649 RK3568_TXCLK_DLY_ENA_GMAC_ENABLE | 1650 RK3568_RXCLK_DLY_ENA_GMAC_ENABLE | 1651 RK3568_GMAC_PHY_INTF_SEL_RGMII); 1652 } 1653 1654 static void rk3576_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1655 { 1656 unsigned int clk_mode, clk_mode_mask; 1657 struct rk3576_sdgmac_grf_reg *s_grf; 1658 1659 enum { 1660 RK3576_GMAC_RMII_MODE_MASK = BIT(3), 1661 RK3576_GMAC_RMII_MODE = 0x1, 1662 }; 1663 1664 s_grf = syscon_get_first_range(ROCKCHIP_SYSCON_SDGMAC_GRF); 1665 1666 clk_mode = RK3576_GMAC_RMII_MODE; 1667 clk_mode_mask = RK3576_GMAC_RMII_MODE_MASK; 1668 1669 if (pdata->bus_id == 1) 1670 rk_clrsetreg(&s_grf->gmac1_con, clk_mode_mask, clk_mode); 1671 else 1672 rk_clrsetreg(&s_grf->gmac0_con, clk_mode_mask, clk_mode); 1673 } 1674 1675 static void rk3576_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1676 { 1677 struct rk3576_sdgmac_grf_reg *s_grf; 1678 struct rk3576_vccio_ioc_reg *ioc; 1679 unsigned int clk_mode, clk_mode_mask; 1680 unsigned int rx_enable, tx_enable; 1681 void *offset_con; 1682 1683 enum { 1684 RK3576_GMAC_RXCLK_DLY_DISABLE = 0, 1685 RK3576_GMAC_RXCLK_DLY_ENABLE = BIT(15), 1686 1687 RK3576_GMAC_TXCLK_DLY_DISABLE = 0, 1688 RK3576_GMAC_TXCLK_DLY_ENABLE = BIT(7), 1689 }; 1690 1691 enum { 1692 RK3576_GMAC_CLK_RGMII_MODE_MASK = BIT(3), 1693 RK3576_GMAC_CLK_RGMII_MODE = 0x0, 1694 }; 1695 1696 ioc = syscon_get_first_range(ROCKCHIP_SYSCON_IOC); 1697 s_grf = syscon_get_first_range(ROCKCHIP_SYSCON_SDGMAC_GRF); 1698 1699 if (pdata->rx_delay < 0) 1700 rx_enable = RK3576_GMAC_RXCLK_DLY_DISABLE; 1701 else 1702 rx_enable = RK3576_GMAC_RXCLK_DLY_ENABLE; 1703 1704 clk_mode = RK3576_GMAC_CLK_RGMII_MODE; 1705 clk_mode_mask = RK3576_GMAC_CLK_RGMII_MODE_MASK; 1706 tx_enable = RK3576_GMAC_TXCLK_DLY_ENABLE; 1707 1708 if (pdata->bus_id == 1) { 1709 offset_con = &ioc->misc_con[4]; 1710 offset_con += 0x6000; 1711 rk_clrsetreg(&s_grf->gmac1_con, clk_mode_mask, clk_mode); 1712 1713 } else { 1714 offset_con = &ioc->misc_con[2]; 1715 offset_con += 0x6000; 1716 rk_clrsetreg(&s_grf->gmac0_con, clk_mode_mask, clk_mode); 1717 } 1718 1719 rk_setreg(offset_con, tx_enable | rx_enable); 1720 rk_setreg(offset_con + 0x4, tx_enable | rx_enable); 1721 rk_setreg(offset_con, DELAY_VALUE(RK3576, pdata->tx_delay, pdata->rx_delay)); 1722 rk_setreg(offset_con + 0X4, DELAY_VALUE(RK3576, pdata->tx_delay, pdata->rx_delay)); 1723 } 1724 1725 static void rk3588_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1726 { 1727 unsigned int intf_sel, intf_sel_mask; 1728 unsigned int clk_mode, clk_mode_mask; 1729 struct rk3588_php_grf *php_grf; 1730 1731 enum { 1732 RK3588_GMAC_PHY_INTF_SEL_SHIFT = 3, 1733 RK3588_GMAC_PHY_INTF_SEL_MASK = GENMASK(5, 3), 1734 RK3588_GMAC_PHY_INTF_SEL_RMII = BIT(5), 1735 }; 1736 1737 enum { 1738 RK3588_GMAC_CLK_RMII_MODE_SHIFT = 0x0, 1739 RK3588_GMAC_CLK_RMII_MODE_MASK = BIT(0), 1740 RK3588_GMAC_CLK_RMII_MODE = 0x1, 1741 }; 1742 1743 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 1744 1745 if (pdata->bus_id == 1) { 1746 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RMII << 6; 1747 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK << 6; 1748 clk_mode = RK3588_GMAC_CLK_RMII_MODE << 5; 1749 clk_mode_mask = RK3588_GMAC_CLK_RMII_MODE_MASK << 5; 1750 } else { 1751 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RMII; 1752 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK; 1753 clk_mode = RK3588_GMAC_CLK_RMII_MODE; 1754 clk_mode_mask = RK3588_GMAC_CLK_RMII_MODE_MASK; 1755 } 1756 1757 rk_clrsetreg(&php_grf->gmac_con0, intf_sel_mask, intf_sel); 1758 rk_clrsetreg(&php_grf->clk_con1, clk_mode_mask, clk_mode); 1759 } 1760 1761 static void rk3588_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1762 { 1763 unsigned int rx_enable, rx_enable_mask, tx_enable, tx_enable_mask; 1764 unsigned int intf_sel, intf_sel_mask; 1765 unsigned int clk_mode, clk_mode_mask; 1766 unsigned int rx_delay; 1767 struct rk3588_php_grf *php_grf; 1768 struct rk3588_sys_grf *grf; 1769 void *offset_con; 1770 1771 enum { 1772 RK3588_GMAC_PHY_INTF_SEL_SHIFT = 3, 1773 RK3588_GMAC_PHY_INTF_SEL_MASK = GENMASK(5, 3), 1774 RK3588_GMAC_PHY_INTF_SEL_RGMII = BIT(3), 1775 1776 RK3588_RXCLK_DLY_ENA_GMAC_MASK = BIT(3), 1777 RK3588_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 1778 RK3588_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(3), 1779 1780 RK3588_TXCLK_DLY_ENA_GMAC_MASK = BIT(2), 1781 RK3588_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 1782 RK3588_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(2), 1783 }; 1784 1785 enum { 1786 RK3588_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1787 RK3588_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 8), 1788 1789 RK3588_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1790 RK3588_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 1791 }; 1792 1793 enum { 1794 RK3588_GMAC_CLK_RGMII_MODE_SHIFT = 0x0, 1795 RK3588_GMAC_CLK_RGMII_MODE_MASK = BIT(0), 1796 RK3588_GMAC_CLK_RGMII_MODE = 0x0, 1797 }; 1798 1799 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1800 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 1801 1802 if (pdata->rx_delay < 0) { 1803 rx_enable = RK3588_RXCLK_DLY_ENA_GMAC_DISABLE; 1804 rx_delay = 0; 1805 } else { 1806 rx_enable = RK3588_RXCLK_DLY_ENA_GMAC_ENABLE; 1807 rx_delay = pdata->rx_delay << RK3588_CLK_RX_DL_CFG_GMAC_SHIFT; 1808 } 1809 1810 if (pdata->bus_id == 1) { 1811 offset_con = &grf->soc_con9; 1812 rx_enable = rx_delay << 2; 1813 rx_enable_mask = RK3588_RXCLK_DLY_ENA_GMAC_MASK << 2; 1814 tx_enable = RK3588_TXCLK_DLY_ENA_GMAC_ENABLE << 2; 1815 tx_enable_mask = RK3588_TXCLK_DLY_ENA_GMAC_MASK << 2; 1816 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RGMII << 6; 1817 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK << 6; 1818 clk_mode = RK3588_GMAC_CLK_RGMII_MODE << 5; 1819 clk_mode_mask = RK3588_GMAC_CLK_RGMII_MODE_MASK << 5; 1820 } else { 1821 offset_con = &grf->soc_con8; 1822 rx_enable_mask = RK3588_RXCLK_DLY_ENA_GMAC_MASK; 1823 tx_enable = RK3588_TXCLK_DLY_ENA_GMAC_ENABLE; 1824 tx_enable_mask = RK3588_TXCLK_DLY_ENA_GMAC_MASK; 1825 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RGMII; 1826 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK; 1827 clk_mode = RK3588_GMAC_CLK_RGMII_MODE; 1828 clk_mode_mask = RK3588_GMAC_CLK_RGMII_MODE_MASK; 1829 } 1830 1831 rk_clrsetreg(offset_con, 1832 RK3588_CLK_TX_DL_CFG_GMAC_MASK | 1833 RK3588_CLK_RX_DL_CFG_GMAC_MASK, 1834 (pdata->tx_delay << RK3588_CLK_TX_DL_CFG_GMAC_SHIFT) | 1835 rx_delay); 1836 1837 rk_clrsetreg(&grf->soc_con7, tx_enable_mask | rx_enable_mask, 1838 tx_enable | rx_enable); 1839 1840 rk_clrsetreg(&php_grf->gmac_con0, intf_sel_mask, intf_sel); 1841 rk_clrsetreg(&php_grf->clk_con1, clk_mode_mask, clk_mode); 1842 } 1843 1844 static void rv1103b_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1845 { 1846 struct rv1103b_grf *grf; 1847 enum { 1848 RV1103B_SYSGRF_GMAC_CLK_RMII_50M_MASK = BIT(2), 1849 RV1103B_SYSGRF_GMAC_CLK_RMII_50M = BIT(2), 1850 }; 1851 1852 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1853 rk_clrsetreg(&grf->gmac_clk_con, 1854 RV1103B_SYSGRF_GMAC_CLK_RMII_50M_MASK, 1855 RV1103B_SYSGRF_GMAC_CLK_RMII_50M); 1856 }; 1857 1858 static void rv1106_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 1859 { 1860 #ifdef CONFIG_ROCKCHIP_RV1103B 1861 struct rv1103b_grf *grf; 1862 #else 1863 struct rv1106_grf *grf; 1864 #endif 1865 unsigned char bgs[1] = {0}; 1866 1867 enum { 1868 RV1106_VOGRF_GMAC_CLK_RMII_MODE_MASK = BIT(0), 1869 RV1106_VOGRF_GMAC_CLK_RMII_MODE = BIT(0), 1870 }; 1871 1872 enum { 1873 RV1106_MACPHY_ENABLE_MASK = BIT(1), 1874 RV1106_MACPHY_DISENABLE = BIT(1), 1875 RV1106_MACPHY_ENABLE = 0, 1876 RV1106_MACPHY_XMII_SEL_MASK = GENMASK(6, 5), 1877 RV1106_MACPHY_XMII_SEL = BIT(6), 1878 RV1106_MACPHY_24M_CLK_SEL_MASK = GENMASK(9, 7), 1879 RV1106_MACPHY_24M_CLK_SEL_24M = (BIT(8) | BIT(9)), 1880 RV1106_MACPHY_PHY_ID_MASK = GENMASK(14, 10), 1881 RV1106_MACPHY_PHY_ID = BIT(11), 1882 }; 1883 1884 enum { 1885 RV1106_MACPHY_BGS_MASK = GENMASK(3, 0), 1886 RV1106_MACPHY_BGS = BIT(2), 1887 }; 1888 1889 #if defined(CONFIG_ROCKCHIP_EFUSE) || defined(CONFIG_ROCKCHIP_OTP) 1890 struct udevice *dev; 1891 u32 regs[2] = {0}; 1892 ofnode node; 1893 int ret = 0; 1894 1895 /* retrieve the device */ 1896 if (IS_ENABLED(CONFIG_ROCKCHIP_EFUSE)) 1897 ret = uclass_get_device_by_driver(UCLASS_MISC, 1898 DM_GET_DRIVER(rockchip_efuse), 1899 &dev); 1900 else 1901 ret = uclass_get_device_by_driver(UCLASS_MISC, 1902 DM_GET_DRIVER(rockchip_otp), 1903 &dev); 1904 if (!ret) { 1905 node = dev_read_subnode(dev, "macphy-bgs"); 1906 if (ofnode_valid(node)) { 1907 if (!ofnode_read_u32_array(node, "reg", regs, 2)) { 1908 /* read the bgs from the efuses */ 1909 ret = misc_read(dev, regs[0], &bgs, 1); 1910 if (ret) { 1911 printf("read bgs from efuse/otp failed, ret=%d\n", 1912 ret); 1913 bgs[0] = 0; 1914 } 1915 } 1916 } 1917 } 1918 #endif 1919 1920 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1921 1922 reset_assert(&pdata->phy_reset); 1923 udelay(20); 1924 rk_clrsetreg(&grf->macphy_con0, 1925 RV1106_MACPHY_ENABLE_MASK | 1926 RV1106_MACPHY_XMII_SEL_MASK | 1927 RV1106_MACPHY_24M_CLK_SEL_MASK | 1928 RV1106_MACPHY_PHY_ID_MASK, 1929 RV1106_MACPHY_ENABLE | 1930 RV1106_MACPHY_XMII_SEL | 1931 RV1106_MACPHY_24M_CLK_SEL_24M | 1932 RV1106_MACPHY_PHY_ID); 1933 1934 rk_clrsetreg(&grf->macphy_con1, 1935 RV1106_MACPHY_BGS_MASK, 1936 bgs[0]); 1937 udelay(20); 1938 reset_deassert(&pdata->phy_reset); 1939 udelay(30 * 1000); 1940 } 1941 1942 static void rv1106_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1943 { 1944 struct rv1106_grf *grf; 1945 enum { 1946 RV1106_VOGRF_GMAC_CLK_RMII_MODE_MASK = BIT(0), 1947 RV1106_VOGRF_GMAC_CLK_RMII_MODE = BIT(0), 1948 }; 1949 1950 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1951 rk_clrsetreg(&grf->gmac_clk_con, 1952 RV1106_VOGRF_GMAC_CLK_RMII_MODE_MASK, 1953 RV1106_VOGRF_GMAC_CLK_RMII_MODE); 1954 }; 1955 1956 static void rv1126_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1957 { 1958 struct rv1126_grf *grf; 1959 1960 enum { 1961 RV1126_GMAC_PHY_INTF_SEL_SHIFT = 4, 1962 RV1126_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1963 RV1126_GMAC_PHY_INTF_SEL_RMII = BIT(6), 1964 }; 1965 1966 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1967 1968 rk_clrsetreg(&grf->mac_con0, 1969 RV1126_GMAC_PHY_INTF_SEL_MASK, 1970 RV1126_GMAC_PHY_INTF_SEL_RMII); 1971 } 1972 1973 static void rv1126_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1974 { 1975 struct rv1126_grf *grf; 1976 1977 enum { 1978 RV1126_GMAC_PHY_INTF_SEL_SHIFT = 4, 1979 RV1126_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1980 RV1126_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 1981 1982 RV1126_RXCLK_M1_DLY_ENA_GMAC_MASK = BIT(3), 1983 RV1126_RXCLK_M1_DLY_ENA_GMAC_DISABLE = 0, 1984 RV1126_RXCLK_M1_DLY_ENA_GMAC_ENABLE = BIT(3), 1985 1986 RV1126_TXCLK_M1_DLY_ENA_GMAC_MASK = BIT(2), 1987 RV1126_TXCLK_M1_DLY_ENA_GMAC_DISABLE = 0, 1988 RV1126_TXCLK_M1_DLY_ENA_GMAC_ENABLE = BIT(2), 1989 1990 RV1126_RXCLK_M0_DLY_ENA_GMAC_MASK = BIT(1), 1991 RV1126_RXCLK_M0_DLY_ENA_GMAC_DISABLE = 0, 1992 RV1126_RXCLK_M0_DLY_ENA_GMAC_ENABLE = BIT(1), 1993 1994 RV1126_TXCLK_M0_DLY_ENA_GMAC_MASK = BIT(0), 1995 RV1126_TXCLK_M0_DLY_ENA_GMAC_DISABLE = 0, 1996 RV1126_TXCLK_M0_DLY_ENA_GMAC_ENABLE = BIT(0), 1997 }; 1998 enum { 1999 RV1126_M0_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 2000 RV1126_M0_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 2001 2002 RV1126_M0_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 2003 RV1126_M0_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 2004 }; 2005 enum { 2006 RV1126_M1_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 2007 RV1126_M1_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 2008 2009 RV1126_M1_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 2010 RV1126_M1_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 2011 }; 2012 2013 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 2014 2015 rk_clrsetreg(&grf->mac_con0, 2016 RV1126_TXCLK_M0_DLY_ENA_GMAC_MASK | 2017 RV1126_RXCLK_M0_DLY_ENA_GMAC_MASK | 2018 RV1126_TXCLK_M1_DLY_ENA_GMAC_MASK | 2019 RV1126_RXCLK_M1_DLY_ENA_GMAC_MASK | 2020 RV1126_GMAC_PHY_INTF_SEL_MASK, 2021 RV1126_TXCLK_M0_DLY_ENA_GMAC_ENABLE | 2022 RV1126_RXCLK_M0_DLY_ENA_GMAC_ENABLE | 2023 RV1126_TXCLK_M1_DLY_ENA_GMAC_ENABLE | 2024 RV1126_RXCLK_M1_DLY_ENA_GMAC_ENABLE | 2025 RV1126_GMAC_PHY_INTF_SEL_RGMII); 2026 2027 rk_clrsetreg(&grf->mac_con1, 2028 RV1126_M0_CLK_RX_DL_CFG_GMAC_MASK | 2029 RV1126_M0_CLK_TX_DL_CFG_GMAC_MASK, 2030 (pdata->rx_delay << RV1126_M0_CLK_RX_DL_CFG_GMAC_SHIFT) | 2031 (pdata->tx_delay << RV1126_M0_CLK_TX_DL_CFG_GMAC_SHIFT)); 2032 2033 rk_clrsetreg(&grf->mac_con2, 2034 RV1126_M1_CLK_RX_DL_CFG_GMAC_MASK | 2035 RV1126_M1_CLK_TX_DL_CFG_GMAC_MASK, 2036 (pdata->rx_delay << RV1126_M1_CLK_RX_DL_CFG_GMAC_SHIFT) | 2037 (pdata->tx_delay << RV1126_M1_CLK_TX_DL_CFG_GMAC_SHIFT)); 2038 } 2039 #endif 2040 2041 #ifdef CONFIG_DWC_ETH_QOS 2042 static void rk3506_set_clock_selection(struct gmac_rockchip_platdata *pdata) 2043 { 2044 struct rk3506_grf_reg *grf; 2045 unsigned int val; 2046 2047 enum { 2048 RK3506_GMAC_CLK_SELET_SHIFT = 5, 2049 RK3506_GMAC_CLK_SELET_MASK = BIT(5), 2050 RK3506_GMAC_CLK_SELET_CRU = 0, 2051 RK3506_GMAC_CLK_SELET_IO = BIT(5), 2052 }; 2053 2054 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 2055 2056 val = pdata->clock_input ? RK3506_GMAC_CLK_SELET_IO : 2057 RK3506_GMAC_CLK_SELET_CRU; 2058 2059 if (pdata->bus_id) 2060 rk_clrsetreg(&grf->soc_con11, RK3506_GMAC_CLK_SELET_MASK, val); 2061 else 2062 rk_clrsetreg(&grf->soc_con8, RK3506_GMAC_CLK_SELET_MASK, val); 2063 } 2064 2065 static void rk3528_set_clock_selection(struct gmac_rockchip_platdata *pdata) 2066 { 2067 struct rk3528_grf *grf; 2068 unsigned int val; 2069 2070 enum { 2071 RK3528_GMAC1_CLK_SELET_SHIFT = 0x12, 2072 RK3528_GMAC1_CLK_SELET_MASK = BIT(12), 2073 RK3528_GMAC1_CLK_SELET_CRU = 0, 2074 RK3528_GMAC1_CLK_SELET_IO = BIT(12), 2075 }; 2076 2077 if (!pdata->bus_id) 2078 return; 2079 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 2080 2081 val = pdata->clock_input ? RK3528_GMAC1_CLK_SELET_IO : 2082 RK3528_GMAC1_CLK_SELET_CRU; 2083 rk_clrsetreg(&grf->gmac1_con0, RK3528_GMAC1_CLK_SELET_MASK, val); 2084 } 2085 2086 static void rk3562_set_clock_selection(struct gmac_rockchip_platdata *pdata) 2087 { 2088 struct rk3562_grf *grf; 2089 struct rk3562_ioc *ioc; 2090 unsigned int val; 2091 2092 enum { 2093 RK3562_GMAC0_CLK_SELET_SHIFT = 0x9, 2094 RK3562_GMAC0_CLK_SELET_MASK = BIT(9), 2095 RK3562_GMAC0_CLK_SELET_CRU = 0, 2096 RK3562_GMAC0_CLK_SELET_IO = BIT(9), 2097 }; 2098 2099 enum { 2100 RK3562_GMAC1_CLK_SELET_SHIFT = 15, 2101 RK3562_GMAC1_CLK_SELET_MASK = BIT(15), 2102 RK3562_GMAC1_CLK_SELET_CRU = 0, 2103 RK3562_GMAC1_CLK_SELET_IO = BIT(15), 2104 }; 2105 2106 enum { 2107 RK3562_GMAC0_IO_EXTCLK_SELET_SHIFT = 0x2, 2108 RK3562_GMAC0_IO_EXTCLK_SELET_MASK = BIT(2), 2109 RK3562_GMAC0_IO_EXTCLK_SELET_CRU = 0, 2110 RK3562_GMAC0_IO_EXTCLK_SELET_IO = BIT(2), 2111 }; 2112 2113 enum { 2114 RK3562_GMAC1_IO_EXTCLK_SELET_SHIFT = 0x3, 2115 RK3562_GMAC1_IO_EXTCLK_SELET_MASK = BIT(3), 2116 RK3562_GMAC1_IO_EXTCLK_SELET_CRU = 0, 2117 RK3562_GMAC1_IO_EXTCLK_SELET_IO = BIT(3), 2118 }; 2119 2120 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 2121 ioc = syscon_get_first_range(ROCKCHIP_SYSCON_IOC); 2122 2123 if (!pdata->bus_id) { 2124 val = pdata->clock_input ? RK3562_GMAC0_CLK_SELET_IO : 2125 RK3562_GMAC0_CLK_SELET_CRU; 2126 rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_CLK_SELET_MASK, val); 2127 val = pdata->clock_input ? RK3562_GMAC0_IO_EXTCLK_SELET_IO : 2128 RK3562_GMAC0_IO_EXTCLK_SELET_CRU; 2129 rk_clrsetreg(&ioc->mac1_io_con1, 2130 RK3562_GMAC0_IO_EXTCLK_SELET_MASK, val); 2131 rk_clrsetreg(&ioc->mac0_io_con1, 2132 RK3562_GMAC0_IO_EXTCLK_SELET_MASK, val); 2133 2134 } else { 2135 val = pdata->clock_input ? RK3562_GMAC1_CLK_SELET_IO : 2136 RK3562_GMAC1_CLK_SELET_CRU; 2137 rk_clrsetreg(&grf->soc_con[1], RK3562_GMAC1_CLK_SELET_MASK, val); 2138 val = pdata->clock_input ? RK3562_GMAC1_IO_EXTCLK_SELET_IO : 2139 RK3562_GMAC1_IO_EXTCLK_SELET_CRU; 2140 rk_clrsetreg(&ioc->mac1_io_con1, 2141 RK3562_GMAC1_IO_EXTCLK_SELET_MASK, val); 2142 } 2143 } 2144 2145 static void rk3576_set_clock_selection(struct gmac_rockchip_platdata *pdata) 2146 { 2147 struct rk3576_sdgmac_grf_reg *s_grf; 2148 unsigned int val, mask; 2149 2150 enum { 2151 RK3576_GMAC_CLK_SELET_MASK = BIT(7), 2152 RK3576_GMAC_CLK_SELET_CRU = 0, 2153 RK3576_GMAC_CLK_SELET_IO = BIT(7), 2154 }; 2155 2156 s_grf = syscon_get_first_range(ROCKCHIP_SYSCON_SDGMAC_GRF); 2157 val = pdata->clock_input ? RK3576_GMAC_CLK_SELET_IO : 2158 RK3576_GMAC_CLK_SELET_CRU; 2159 2160 mask = RK3576_GMAC_CLK_SELET_MASK; 2161 2162 if (pdata->bus_id == 1) 2163 rk_clrsetreg(&s_grf->gmac1_con, mask, val); 2164 else 2165 rk_clrsetreg(&s_grf->gmac0_con, mask, val); 2166 } 2167 2168 static void rk3588_set_clock_selection(struct gmac_rockchip_platdata *pdata) 2169 { 2170 struct rk3588_php_grf *php_grf; 2171 unsigned int val, mask; 2172 2173 enum { 2174 RK3588_GMAC_CLK_SELET_SHIFT = 0x4, 2175 RK3588_GMAC_CLK_SELET_MASK = BIT(4), 2176 RK3588_GMAC_CLK_SELET_CRU = BIT(4), 2177 RK3588_GMAC_CLK_SELET_IO = 0, 2178 }; 2179 2180 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 2181 val = pdata->clock_input ? RK3588_GMAC_CLK_SELET_IO : 2182 RK3588_GMAC_CLK_SELET_CRU; 2183 mask = RK3588_GMAC_CLK_SELET_MASK; 2184 2185 if (pdata->bus_id == 1) { 2186 val <<= 5; 2187 mask <<= 5; 2188 } 2189 2190 rk_clrsetreg(&php_grf->clk_con1, mask, val); 2191 } 2192 #endif 2193 2194 static int gmac_rockchip_probe(struct udevice *dev) 2195 { 2196 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 2197 struct rk_gmac_ops *ops = 2198 (struct rk_gmac_ops *)dev_get_driver_data(dev); 2199 #ifdef CONFIG_DWC_ETH_QOS 2200 struct eqos_config *config; 2201 #else 2202 struct dw_eth_pdata *dw_pdata; 2203 #endif 2204 struct eth_pdata *eth_pdata; 2205 struct clk clk; 2206 ulong rate; 2207 int ret; 2208 2209 #ifdef CONFIG_DWC_ETH_QOS 2210 eth_pdata = &pdata->eth_pdata; 2211 config = (struct eqos_config *)&ops->config; 2212 memcpy(config, &eqos_rockchip_config, sizeof(struct eqos_config)); 2213 eth_pdata->phy_interface = config->ops->eqos_get_interface(dev); 2214 #else 2215 dw_pdata = &pdata->dw_eth_pdata; 2216 eth_pdata = &dw_pdata->eth_pdata; 2217 #endif 2218 pdata->bus_id = dev->seq; 2219 2220 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 2221 ret = clk_set_defaults(dev); 2222 if (ret) 2223 debug("%s clk_set_defaults failed %d\n", __func__, ret); 2224 2225 ret = clk_get_by_index(dev, 0, &clk); 2226 if (ret) 2227 debug("%s clk_get_by_index failed %d\n", __func__, ret); 2228 2229 pdata->phy_interface = eth_pdata->phy_interface; 2230 2231 if (ops->set_clock_selection) 2232 ops->set_clock_selection(pdata); 2233 2234 if (pdata->integrated_phy && ops->integrated_phy_powerup) 2235 ops->integrated_phy_powerup(pdata); 2236 2237 switch (eth_pdata->phy_interface) { 2238 case PHY_INTERFACE_MODE_RGMII: 2239 case PHY_INTERFACE_MODE_RGMII_RXID: 2240 /* 2241 * If the gmac clock is from internal pll, need to set and 2242 * check the return value for gmac clock at RGMII mode. If 2243 * the gmac clock is from external source, the clock rate 2244 * is not set, because of it is bypassed. 2245 */ 2246 if (!pdata->clock_input) { 2247 if (clk.id) { 2248 rate = clk_set_rate(&clk, 125000000); 2249 if (rate != 125000000) 2250 return -EINVAL; 2251 } 2252 } 2253 2254 if (eth_pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) 2255 pdata->rx_delay = -1; 2256 2257 /* Set to RGMII mode */ 2258 if (ops->set_to_rgmii) 2259 ops->set_to_rgmii(pdata); 2260 else 2261 return -EPERM; 2262 2263 break; 2264 case PHY_INTERFACE_MODE_RMII: 2265 /* The commet is the same as RGMII mode */ 2266 if (!pdata->clock_input) { 2267 if (clk.id) { 2268 rate = clk_set_rate(&clk, 50000000); 2269 if (rate != 50000000) 2270 return -EINVAL; 2271 } 2272 } 2273 2274 /* Set to RMII mode */ 2275 if (ops->set_to_rmii) 2276 ops->set_to_rmii(pdata); 2277 2278 break; 2279 default: 2280 debug("NO interface defined!\n"); 2281 return -ENXIO; 2282 } 2283 2284 #ifdef CONFIG_DWC_ETH_QOS 2285 return eqos_probe(dev); 2286 #else 2287 return designware_eth_probe(dev); 2288 #endif 2289 } 2290 2291 static int gmac_rockchip_eth_write_hwaddr(struct udevice *dev) 2292 { 2293 #if defined(CONFIG_DWC_ETH_QOS) 2294 return eqos_write_hwaddr(dev); 2295 #else 2296 return designware_eth_write_hwaddr(dev); 2297 #endif 2298 } 2299 2300 static int gmac_rockchip_eth_free_pkt(struct udevice *dev, uchar *packet, 2301 int length) 2302 { 2303 #ifdef CONFIG_DWC_ETH_QOS 2304 return eqos_free_pkt(dev, packet, length); 2305 #else 2306 return designware_eth_free_pkt(dev, packet, length); 2307 #endif 2308 } 2309 2310 static int gmac_rockchip_eth_send(struct udevice *dev, void *packet, 2311 int length) 2312 { 2313 #ifdef CONFIG_DWC_ETH_QOS 2314 return eqos_send(dev, packet, length); 2315 #else 2316 return designware_eth_send(dev, packet, length); 2317 #endif 2318 } 2319 2320 static int gmac_rockchip_eth_recv(struct udevice *dev, int flags, 2321 uchar **packetp) 2322 { 2323 #ifdef CONFIG_DWC_ETH_QOS 2324 return eqos_recv(dev, flags, packetp); 2325 #else 2326 return designware_eth_recv(dev, flags, packetp); 2327 #endif 2328 } 2329 2330 static int gmac_rockchip_eth_start(struct udevice *dev) 2331 { 2332 struct rockchip_eth_dev *priv = dev_get_priv(dev); 2333 struct rk_gmac_ops *ops = 2334 (struct rk_gmac_ops *)dev_get_driver_data(dev); 2335 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 2336 #ifndef CONFIG_DWC_ETH_QOS 2337 struct dw_eth_pdata *dw_pdata; 2338 struct eth_pdata *eth_pdata; 2339 #endif 2340 int ret; 2341 2342 #ifdef CONFIG_DWC_ETH_QOS 2343 ret = eqos_init(dev); 2344 #else 2345 dw_pdata = &pdata->dw_eth_pdata; 2346 eth_pdata = &dw_pdata->eth_pdata; 2347 ret = designware_eth_init((struct dw_eth_dev *)priv, 2348 eth_pdata->enetaddr); 2349 #endif 2350 if (ret) 2351 return ret; 2352 ret = ops->fix_mac_speed(pdata, priv); 2353 if (ret) 2354 return ret; 2355 2356 #ifdef CONFIG_DWC_ETH_QOS 2357 eqos_enable(dev); 2358 #else 2359 ret = designware_eth_enable((struct dw_eth_dev *)priv); 2360 if (ret) 2361 return ret; 2362 #endif 2363 2364 return 0; 2365 } 2366 2367 static void gmac_rockchip_eth_stop(struct udevice *dev) 2368 { 2369 #ifdef CONFIG_DWC_ETH_QOS 2370 eqos_stop(dev); 2371 #else 2372 designware_eth_stop(dev); 2373 #endif 2374 } 2375 2376 const struct eth_ops gmac_rockchip_eth_ops = { 2377 .start = gmac_rockchip_eth_start, 2378 .send = gmac_rockchip_eth_send, 2379 .recv = gmac_rockchip_eth_recv, 2380 .free_pkt = gmac_rockchip_eth_free_pkt, 2381 .stop = gmac_rockchip_eth_stop, 2382 .write_hwaddr = gmac_rockchip_eth_write_hwaddr, 2383 }; 2384 2385 #ifndef CONFIG_DWC_ETH_QOS 2386 const struct rk_gmac_ops px30_gmac_ops = { 2387 .fix_mac_speed = px30_gmac_fix_mac_speed, 2388 .set_to_rmii = px30_gmac_set_to_rmii, 2389 }; 2390 2391 const struct rk_gmac_ops rk1808_gmac_ops = { 2392 .fix_mac_speed = rk1808_gmac_fix_mac_speed, 2393 .set_to_rgmii = rk1808_gmac_set_to_rgmii, 2394 }; 2395 2396 const struct rk_gmac_ops rk3228_gmac_ops = { 2397 .fix_mac_speed = rk3228_gmac_fix_mac_speed, 2398 .set_to_rmii = rk3228_gmac_set_to_rmii, 2399 .set_to_rgmii = rk3228_gmac_set_to_rgmii, 2400 .integrated_phy_powerup = rk3228_gmac_integrated_phy_powerup, 2401 }; 2402 2403 const struct rk_gmac_ops rk3288_gmac_ops = { 2404 .fix_mac_speed = rk3288_gmac_fix_mac_speed, 2405 .set_to_rgmii = rk3288_gmac_set_to_rgmii, 2406 }; 2407 2408 const struct rk_gmac_ops rk3308_gmac_ops = { 2409 .fix_mac_speed = rk3308_gmac_fix_mac_speed, 2410 .set_to_rmii = rk3308_gmac_set_to_rmii, 2411 }; 2412 2413 const struct rk_gmac_ops rk3328_gmac_ops = { 2414 .fix_mac_speed = rk3328_gmac_fix_mac_speed, 2415 .set_to_rmii = rk3328_gmac_set_to_rmii, 2416 .set_to_rgmii = rk3328_gmac_set_to_rgmii, 2417 .integrated_phy_powerup = rk3328_gmac_integrated_phy_powerup, 2418 }; 2419 2420 const struct rk_gmac_ops rk3368_gmac_ops = { 2421 .fix_mac_speed = rk3368_gmac_fix_mac_speed, 2422 .set_to_rgmii = rk3368_gmac_set_to_rgmii, 2423 }; 2424 2425 const struct rk_gmac_ops rk3399_gmac_ops = { 2426 .fix_mac_speed = rk3399_gmac_fix_mac_speed, 2427 .set_to_rgmii = rk3399_gmac_set_to_rgmii, 2428 }; 2429 2430 const struct rk_gmac_ops rv1108_gmac_ops = { 2431 .fix_mac_speed = rv1108_set_rmii_speed, 2432 .set_to_rmii = rv1108_gmac_set_to_rmii, 2433 }; 2434 #else 2435 const struct rk_gmac_ops rk3506_gmac_ops = { 2436 .fix_mac_speed = rk3506_set_rmii_speed, 2437 .set_to_rmii = rk3506_set_to_rmii, 2438 .set_clock_selection = rk3506_set_clock_selection, 2439 }; 2440 2441 const struct rk_gmac_ops rk3528_gmac_ops = { 2442 .fix_mac_speed = rk3528_set_rgmii_speed, 2443 .set_to_rgmii = rk3528_set_to_rgmii, 2444 .set_to_rmii = rk3528_set_to_rmii, 2445 .set_clock_selection = rk3528_set_clock_selection, 2446 .integrated_phy_powerup = rk3528_gmac_integrated_phy_powerup, 2447 }; 2448 2449 const struct rk_gmac_ops rk3562_gmac_ops = { 2450 .fix_mac_speed = rk3562_set_gmac_speed, 2451 .set_to_rgmii = rk3562_set_to_rgmii, 2452 .set_to_rmii = rk3562_set_to_rmii, 2453 .set_clock_selection = rk3562_set_clock_selection, 2454 }; 2455 2456 const struct rk_gmac_ops rk3568_gmac_ops = { 2457 .fix_mac_speed = rv1126_set_rgmii_speed, 2458 .set_to_rgmii = rk3568_set_to_rgmii, 2459 .set_to_rmii = rk3568_set_to_rmii, 2460 }; 2461 2462 const struct rk_gmac_ops rk3576_gmac_ops = { 2463 .fix_mac_speed = rk3576_set_rgmii_speed, 2464 .set_to_rgmii = rk3576_set_to_rgmii, 2465 .set_to_rmii = rk3576_set_to_rmii, 2466 .set_clock_selection = rk3576_set_clock_selection, 2467 }; 2468 2469 const struct rk_gmac_ops rk3588_gmac_ops = { 2470 .fix_mac_speed = rk3588_set_rgmii_speed, 2471 .set_to_rgmii = rk3588_set_to_rgmii, 2472 .set_to_rmii = rk3588_set_to_rmii, 2473 .set_clock_selection = rk3588_set_clock_selection, 2474 }; 2475 2476 const struct rk_gmac_ops rv1103b_gmac_ops = { 2477 .fix_mac_speed = rv1106_set_rmii_speed, 2478 .set_to_rmii = rv1103b_set_to_rmii, 2479 .integrated_phy_powerup = rv1106_gmac_integrated_phy_powerup, 2480 }; 2481 2482 const struct rk_gmac_ops rv1106_gmac_ops = { 2483 .fix_mac_speed = rv1106_set_rmii_speed, 2484 .set_to_rmii = rv1106_set_to_rmii, 2485 .integrated_phy_powerup = rv1106_gmac_integrated_phy_powerup, 2486 }; 2487 2488 const struct rk_gmac_ops rv1126_gmac_ops = { 2489 .fix_mac_speed = rv1126_set_rgmii_speed, 2490 .set_to_rgmii = rv1126_set_to_rgmii, 2491 .set_to_rmii = rv1126_set_to_rmii, 2492 }; 2493 #endif 2494 2495 static const struct udevice_id rockchip_gmac_ids[] = { 2496 #ifndef CONFIG_DWC_ETH_QOS 2497 #ifdef CONFIG_ROCKCHIP_PX30 2498 { .compatible = "rockchip,px30-gmac", 2499 .data = (ulong)&px30_gmac_ops }, 2500 #endif 2501 2502 #ifdef CONFIG_ROCKCHIP_RK1808 2503 { .compatible = "rockchip,rk1808-gmac", 2504 .data = (ulong)&rk1808_gmac_ops }, 2505 #endif 2506 2507 #ifdef CONFIG_ROCKCHIP_RK3228 2508 { .compatible = "rockchip,rk3228-gmac", 2509 .data = (ulong)&rk3228_gmac_ops }, 2510 #endif 2511 2512 #ifdef CONFIG_ROCKCHIP_RK3288 2513 { .compatible = "rockchip,rk3288-gmac", 2514 .data = (ulong)&rk3288_gmac_ops }, 2515 #endif 2516 2517 #ifdef CONFIG_ROCKCHIP_RK3308 2518 { .compatible = "rockchip,rk3308-mac", 2519 .data = (ulong)&rk3308_gmac_ops }, 2520 #endif 2521 2522 #ifdef CONFIG_ROCKCHIP_RK3328 2523 { .compatible = "rockchip,rk3328-gmac", 2524 .data = (ulong)&rk3328_gmac_ops }, 2525 #endif 2526 2527 #ifdef CONFIG_ROCKCHIP_RK3368 2528 { .compatible = "rockchip,rk3368-gmac", 2529 .data = (ulong)&rk3368_gmac_ops }, 2530 #endif 2531 2532 #ifdef CONFIG_ROCKCHIP_RK3399 2533 { .compatible = "rockchip,rk3399-gmac", 2534 .data = (ulong)&rk3399_gmac_ops }, 2535 #endif 2536 2537 #ifdef CONFIG_ROCKCHIP_RV1108 2538 { .compatible = "rockchip,rv1108-gmac", 2539 .data = (ulong)&rv1108_gmac_ops }, 2540 #endif 2541 #else 2542 #ifdef CONFIG_ROCKCHIP_RK3506 2543 { .compatible = "rockchip,rk3506-gmac", 2544 .data = (ulong)&rk3506_gmac_ops }, 2545 #endif 2546 2547 #ifdef CONFIG_ROCKCHIP_RK3528 2548 { .compatible = "rockchip,rk3528-gmac", 2549 .data = (ulong)&rk3528_gmac_ops }, 2550 #endif 2551 2552 #ifdef CONFIG_ROCKCHIP_RK3562 2553 { .compatible = "rockchip,rk3562-gmac", 2554 .data = (ulong)&rk3562_gmac_ops }, 2555 #endif 2556 2557 #ifdef CONFIG_ROCKCHIP_RK3568 2558 { .compatible = "rockchip,rk3568-gmac", 2559 .data = (ulong)&rk3568_gmac_ops }, 2560 #endif 2561 2562 #ifdef CONFIG_ROCKCHIP_RK3576 2563 { .compatible = "rockchip,rk3576-gmac", 2564 .data = (ulong)&rk3576_gmac_ops }, 2565 #endif 2566 2567 #ifdef CONFIG_ROCKCHIP_RK3588 2568 { .compatible = "rockchip,rk3588-gmac", 2569 .data = (ulong)&rk3588_gmac_ops }, 2570 #endif 2571 2572 #ifdef CONFIG_ROCKCHIP_RV1103B 2573 { .compatible = "rockchip,rv1103b-gmac", 2574 .data = (ulong)&rv1103b_gmac_ops }, 2575 #endif 2576 2577 #ifdef CONFIG_ROCKCHIP_RV1106 2578 { .compatible = "rockchip,rv1106-gmac", 2579 .data = (ulong)&rv1106_gmac_ops }, 2580 #endif 2581 2582 #ifdef CONFIG_ROCKCHIP_RV1126 2583 { .compatible = "rockchip,rv1126-gmac", 2584 .data = (ulong)&rv1126_gmac_ops }, 2585 #endif 2586 #endif 2587 { } 2588 }; 2589 2590 U_BOOT_DRIVER(eth_gmac_rockchip) = { 2591 .name = "gmac_rockchip", 2592 .id = UCLASS_ETH, 2593 .of_match = rockchip_gmac_ids, 2594 .ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata, 2595 .probe = gmac_rockchip_probe, 2596 .ops = &gmac_rockchip_eth_ops, 2597 .priv_auto_alloc_size = sizeof(struct rockchip_eth_dev), 2598 .platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata), 2599 .flags = DM_FLAG_ALLOC_PRIV_DMA, 2600 }; 2601