1 /* 2 * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Rockchip GMAC ethernet IP driver for U-Boot 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <clk.h> 12 #include <phy.h> 13 #include <syscon.h> 14 #include <asm/io.h> 15 #include <asm/arch/periph.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/hardware.h> 18 #ifdef CONFIG_DWC_ETH_QOS 19 #include "dwc_eth_qos.h" 20 #else 21 #include <asm/arch/grf_px30.h> 22 #include <asm/arch/grf_rk1808.h> 23 #include <asm/arch/grf_rk322x.h> 24 #include <asm/arch/grf_rk3288.h> 25 #include <asm/arch/grf_rk3308.h> 26 #include <asm/arch/grf_rk3328.h> 27 #include <asm/arch/grf_rk3368.h> 28 #include <asm/arch/grf_rk3399.h> 29 #include <asm/arch/grf_rv1108.h> 30 #include "designware.h" 31 #include <dt-bindings/clock/rk3288-cru.h> 32 #endif 33 #include <dm/pinctrl.h> 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 struct rockchip_eth_dev { 38 #ifdef CONFIG_DWC_ETH_QOS 39 struct eqos_priv eqos; 40 #else 41 struct dw_eth_dev dw; 42 #endif 43 }; 44 45 /* 46 * Platform data for the gmac 47 * 48 * dw_eth_pdata: Required platform data for designware driver (must be first) 49 */ 50 struct gmac_rockchip_platdata { 51 #ifndef CONFIG_DWC_ETH_QOS 52 struct dw_eth_pdata dw_eth_pdata; 53 #else 54 struct eth_pdata eth_pdata; 55 #endif 56 bool clock_input; 57 int tx_delay; 58 int rx_delay; 59 }; 60 61 struct rk_gmac_ops { 62 #ifdef CONFIG_DWC_ETH_QOS 63 const struct eqos_config config; 64 #endif 65 int (*fix_mac_speed)(struct rockchip_eth_dev *dev); 66 void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata); 67 void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata); 68 }; 69 70 void gmac_set_rgmii(struct udevice *dev, u32 tx_delay, u32 rx_delay) 71 { 72 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 73 struct rk_gmac_ops *ops = 74 (struct rk_gmac_ops *)dev_get_driver_data(dev); 75 76 pdata->tx_delay = tx_delay; 77 pdata->rx_delay = rx_delay; 78 79 ops->set_to_rgmii(pdata); 80 } 81 82 static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) 83 { 84 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 85 const char *string; 86 87 string = dev_read_string(dev, "clock_in_out"); 88 if (!strcmp(string, "input")) 89 pdata->clock_input = true; 90 else 91 pdata->clock_input = false; 92 93 /* Check the new naming-style first... */ 94 pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT); 95 pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT); 96 97 /* ... and fall back to the old naming style or default, if necessary */ 98 if (pdata->tx_delay == -ENOENT) 99 pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30); 100 if (pdata->rx_delay == -ENOENT) 101 pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10); 102 103 #ifdef CONFIG_DWC_ETH_QOS 104 return 0; 105 #else 106 return designware_eth_ofdata_to_platdata(dev); 107 #endif 108 } 109 110 #ifndef CONFIG_DWC_ETH_QOS 111 static int px30_gmac_fix_mac_speed(struct rockchip_eth_dev *dev) 112 { 113 struct dw_eth_dev *priv = &dev->dw; 114 struct px30_grf *grf; 115 struct clk clk_speed; 116 int speed, ret; 117 enum { 118 PX30_GMAC_SPEED_SHIFT = 0x2, 119 PX30_GMAC_SPEED_MASK = BIT(2), 120 PX30_GMAC_SPEED_10M = 0, 121 PX30_GMAC_SPEED_100M = BIT(2), 122 }; 123 124 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 125 &clk_speed); 126 if (ret) 127 return ret; 128 129 switch (priv->phydev->speed) { 130 case 10: 131 speed = PX30_GMAC_SPEED_10M; 132 ret = clk_set_rate(&clk_speed, 2500000); 133 if (ret) 134 return ret; 135 break; 136 case 100: 137 speed = PX30_GMAC_SPEED_100M; 138 ret = clk_set_rate(&clk_speed, 25000000); 139 if (ret) 140 return ret; 141 break; 142 default: 143 debug("Unknown phy speed: %d\n", priv->phydev->speed); 144 return -EINVAL; 145 } 146 147 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 148 rk_clrsetreg(&grf->mac_con1, PX30_GMAC_SPEED_MASK, speed); 149 150 return 0; 151 } 152 153 static int rk1808_gmac_fix_mac_speed(struct rockchip_eth_dev *dev) 154 { 155 struct dw_eth_dev *priv = &dev->dw; 156 struct clk clk_speed; 157 int ret; 158 159 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 160 &clk_speed); 161 if (ret) 162 return ret; 163 164 switch (priv->phydev->speed) { 165 case 10: 166 ret = clk_set_rate(&clk_speed, 2500000); 167 if (ret) 168 return ret; 169 break; 170 case 100: 171 ret = clk_set_rate(&clk_speed, 25000000); 172 if (ret) 173 return ret; 174 break; 175 case 1000: 176 ret = clk_set_rate(&clk_speed, 125000000); 177 if (ret) 178 return ret; 179 break; 180 default: 181 debug("Unknown phy speed: %d\n", priv->phydev->speed); 182 return -EINVAL; 183 } 184 185 return 0; 186 } 187 188 static int rk3228_gmac_fix_mac_speed(struct rockchip_eth_dev *dev) 189 { 190 struct dw_eth_dev *priv = &dev->dw; 191 struct rk322x_grf *grf; 192 int clk; 193 enum { 194 RK3228_GMAC_CLK_SEL_SHIFT = 8, 195 RK3228_GMAC_CLK_SEL_MASK = GENMASK(9, 8), 196 RK3228_GMAC_CLK_SEL_125M = 0 << 8, 197 RK3228_GMAC_CLK_SEL_25M = 3 << 8, 198 RK3228_GMAC_CLK_SEL_2_5M = 2 << 8, 199 }; 200 201 switch (priv->phydev->speed) { 202 case 10: 203 clk = RK3228_GMAC_CLK_SEL_2_5M; 204 break; 205 case 100: 206 clk = RK3228_GMAC_CLK_SEL_25M; 207 break; 208 case 1000: 209 clk = RK3228_GMAC_CLK_SEL_125M; 210 break; 211 default: 212 debug("Unknown phy speed: %d\n", priv->phydev->speed); 213 return -EINVAL; 214 } 215 216 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 217 rk_clrsetreg(&grf->mac_con[1], RK3228_GMAC_CLK_SEL_MASK, clk); 218 219 return 0; 220 } 221 222 static int rk3288_gmac_fix_mac_speed(struct rockchip_eth_dev *dev) 223 { 224 struct dw_eth_dev *priv = &dev->dw; 225 struct rk3288_grf *grf; 226 int clk; 227 228 switch (priv->phydev->speed) { 229 case 10: 230 clk = RK3288_GMAC_CLK_SEL_2_5M; 231 break; 232 case 100: 233 clk = RK3288_GMAC_CLK_SEL_25M; 234 break; 235 case 1000: 236 clk = RK3288_GMAC_CLK_SEL_125M; 237 break; 238 default: 239 debug("Unknown phy speed: %d\n", priv->phydev->speed); 240 return -EINVAL; 241 } 242 243 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 244 rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk); 245 246 return 0; 247 } 248 249 static int rk3308_gmac_fix_mac_speed(struct rockchip_eth_dev *dev) 250 { 251 struct dw_eth_dev *priv = &dev->dw; 252 struct rk3308_grf *grf; 253 struct clk clk_speed; 254 int speed, ret; 255 enum { 256 RK3308_GMAC_SPEED_SHIFT = 0x0, 257 RK3308_GMAC_SPEED_MASK = BIT(0), 258 RK3308_GMAC_SPEED_10M = 0, 259 RK3308_GMAC_SPEED_100M = BIT(0), 260 }; 261 262 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 263 &clk_speed); 264 if (ret) 265 return ret; 266 267 switch (priv->phydev->speed) { 268 case 10: 269 speed = RK3308_GMAC_SPEED_10M; 270 ret = clk_set_rate(&clk_speed, 2500000); 271 if (ret) 272 return ret; 273 break; 274 case 100: 275 speed = RK3308_GMAC_SPEED_100M; 276 ret = clk_set_rate(&clk_speed, 25000000); 277 if (ret) 278 return ret; 279 break; 280 default: 281 debug("Unknown phy speed: %d\n", priv->phydev->speed); 282 return -EINVAL; 283 } 284 285 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 286 rk_clrsetreg(&grf->mac_con0, RK3308_GMAC_SPEED_MASK, speed); 287 288 return 0; 289 } 290 291 static int rk3328_gmac_fix_mac_speed(struct rockchip_eth_dev *dev) 292 { 293 struct dw_eth_dev *priv = &dev->dw; 294 struct rk3328_grf_regs *grf; 295 int clk; 296 enum { 297 RK3328_GMAC_CLK_SEL_SHIFT = 11, 298 RK3328_GMAC_CLK_SEL_MASK = GENMASK(12, 11), 299 RK3328_GMAC_CLK_SEL_125M = 0 << 11, 300 RK3328_GMAC_CLK_SEL_25M = 3 << 11, 301 RK3328_GMAC_CLK_SEL_2_5M = 2 << 11, 302 }; 303 304 switch (priv->phydev->speed) { 305 case 10: 306 clk = RK3328_GMAC_CLK_SEL_2_5M; 307 break; 308 case 100: 309 clk = RK3328_GMAC_CLK_SEL_25M; 310 break; 311 case 1000: 312 clk = RK3328_GMAC_CLK_SEL_125M; 313 break; 314 default: 315 debug("Unknown phy speed: %d\n", priv->phydev->speed); 316 return -EINVAL; 317 } 318 319 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 320 rk_clrsetreg(&grf->mac_con[1], RK3328_GMAC_CLK_SEL_MASK, clk); 321 322 return 0; 323 } 324 325 static int rk3368_gmac_fix_mac_speed(struct rockchip_eth_dev *dev) 326 { 327 struct dw_eth_dev *priv = &dev->dw; 328 struct rk3368_grf *grf; 329 int clk; 330 enum { 331 RK3368_GMAC_CLK_SEL_2_5M = 2 << 4, 332 RK3368_GMAC_CLK_SEL_25M = 3 << 4, 333 RK3368_GMAC_CLK_SEL_125M = 0 << 4, 334 RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4), 335 }; 336 337 switch (priv->phydev->speed) { 338 case 10: 339 clk = RK3368_GMAC_CLK_SEL_2_5M; 340 break; 341 case 100: 342 clk = RK3368_GMAC_CLK_SEL_25M; 343 break; 344 case 1000: 345 clk = RK3368_GMAC_CLK_SEL_125M; 346 break; 347 default: 348 debug("Unknown phy speed: %d\n", priv->phydev->speed); 349 return -EINVAL; 350 } 351 352 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 353 rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk); 354 355 return 0; 356 } 357 358 static int rk3399_gmac_fix_mac_speed(struct rockchip_eth_dev *dev) 359 { 360 struct dw_eth_dev *priv = &dev->dw; 361 struct rk3399_grf_regs *grf; 362 int clk; 363 364 switch (priv->phydev->speed) { 365 case 10: 366 clk = RK3399_GMAC_CLK_SEL_2_5M; 367 break; 368 case 100: 369 clk = RK3399_GMAC_CLK_SEL_25M; 370 break; 371 case 1000: 372 clk = RK3399_GMAC_CLK_SEL_125M; 373 break; 374 default: 375 debug("Unknown phy speed: %d\n", priv->phydev->speed); 376 return -EINVAL; 377 } 378 379 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 380 rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk); 381 382 return 0; 383 } 384 385 static int rv1108_set_rmii_speed(struct rockchip_eth_dev *dev) 386 { 387 struct dw_eth_dev *priv = &dev->dw; 388 struct rv1108_grf *grf; 389 int clk, speed; 390 enum { 391 RV1108_GMAC_SPEED_MASK = BIT(2), 392 RV1108_GMAC_SPEED_10M = 0 << 2, 393 RV1108_GMAC_SPEED_100M = 1 << 2, 394 RV1108_GMAC_CLK_SEL_MASK = BIT(7), 395 RV1108_GMAC_CLK_SEL_2_5M = 0 << 7, 396 RV1108_GMAC_CLK_SEL_25M = 1 << 7, 397 }; 398 399 switch (priv->phydev->speed) { 400 case 10: 401 clk = RV1108_GMAC_CLK_SEL_2_5M; 402 speed = RV1108_GMAC_SPEED_10M; 403 break; 404 case 100: 405 clk = RV1108_GMAC_CLK_SEL_25M; 406 speed = RV1108_GMAC_SPEED_100M; 407 break; 408 default: 409 debug("Unknown phy speed: %d\n", priv->phydev->speed); 410 return -EINVAL; 411 } 412 413 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 414 rk_clrsetreg(&grf->gmac_con0, 415 RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK, 416 clk | speed); 417 418 return 0; 419 } 420 #endif 421 422 #ifndef CONFIG_DWC_ETH_QOS 423 static void px30_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 424 { 425 struct px30_grf *grf; 426 enum { 427 px30_GMAC_PHY_INTF_SEL_SHIFT = 4, 428 px30_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 6), 429 px30_GMAC_PHY_INTF_SEL_RMII = BIT(6), 430 }; 431 432 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 433 434 rk_clrsetreg(&grf->mac_con1, 435 px30_GMAC_PHY_INTF_SEL_MASK, 436 px30_GMAC_PHY_INTF_SEL_RMII); 437 } 438 439 static void rk1808_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 440 { 441 struct rk1808_grf *grf; 442 enum { 443 RK1808_GMAC_PHY_INTF_SEL_SHIFT = 4, 444 RK1808_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 445 RK1808_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 446 447 RK1808_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 448 RK1808_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 449 RK1808_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 450 451 RK1808_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 452 RK1808_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 453 RK1808_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 454 }; 455 enum { 456 RK1808_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 457 RK1808_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 7), 458 459 RK1808_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 460 RK1808_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 461 }; 462 463 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 464 rk_clrsetreg(&grf->mac_con1, 465 RK1808_GMAC_PHY_INTF_SEL_MASK | 466 RK1808_RXCLK_DLY_ENA_GMAC_MASK | 467 RK1808_TXCLK_DLY_ENA_GMAC_MASK, 468 RK1808_GMAC_PHY_INTF_SEL_RGMII | 469 RK1808_RXCLK_DLY_ENA_GMAC_ENABLE | 470 RK1808_TXCLK_DLY_ENA_GMAC_ENABLE); 471 472 rk_clrsetreg(&grf->mac_con0, 473 RK1808_CLK_RX_DL_CFG_GMAC_MASK | 474 RK1808_CLK_TX_DL_CFG_GMAC_MASK, 475 pdata->rx_delay << RK1808_CLK_RX_DL_CFG_GMAC_SHIFT | 476 pdata->tx_delay << RK1808_CLK_TX_DL_CFG_GMAC_SHIFT); 477 } 478 479 static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 480 { 481 struct rk322x_grf *grf; 482 enum { 483 RK3228_RMII_MODE_SHIFT = 10, 484 RK3228_RMII_MODE_MASK = BIT(10), 485 486 RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4, 487 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 488 RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 489 490 RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 491 RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 492 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 493 494 RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 495 RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 496 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 497 }; 498 enum { 499 RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 500 RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 501 502 RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 503 RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 504 }; 505 506 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 507 rk_clrsetreg(&grf->mac_con[1], 508 RK3228_RMII_MODE_MASK | 509 RK3228_GMAC_PHY_INTF_SEL_MASK | 510 RK3228_RXCLK_DLY_ENA_GMAC_MASK | 511 RK3228_TXCLK_DLY_ENA_GMAC_MASK, 512 RK3228_GMAC_PHY_INTF_SEL_RGMII | 513 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE | 514 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE); 515 516 rk_clrsetreg(&grf->mac_con[0], 517 RK3228_CLK_RX_DL_CFG_GMAC_MASK | 518 RK3228_CLK_TX_DL_CFG_GMAC_MASK, 519 pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT | 520 pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT); 521 } 522 523 static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 524 { 525 struct rk3288_grf *grf; 526 527 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 528 rk_clrsetreg(&grf->soc_con1, 529 RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK, 530 RK3288_GMAC_PHY_INTF_SEL_RGMII); 531 532 rk_clrsetreg(&grf->soc_con3, 533 RK3288_RXCLK_DLY_ENA_GMAC_MASK | 534 RK3288_TXCLK_DLY_ENA_GMAC_MASK | 535 RK3288_CLK_RX_DL_CFG_GMAC_MASK | 536 RK3288_CLK_TX_DL_CFG_GMAC_MASK, 537 RK3288_RXCLK_DLY_ENA_GMAC_ENABLE | 538 RK3288_TXCLK_DLY_ENA_GMAC_ENABLE | 539 pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT | 540 pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT); 541 } 542 543 static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 544 { 545 struct rk3308_grf *grf; 546 enum { 547 RK3308_GMAC_PHY_INTF_SEL_SHIFT = 2, 548 RK3308_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 2), 549 RK3308_GMAC_PHY_INTF_SEL_RMII = BIT(4), 550 }; 551 552 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 553 554 rk_clrsetreg(&grf->mac_con0, 555 RK3308_GMAC_PHY_INTF_SEL_MASK, 556 RK3308_GMAC_PHY_INTF_SEL_RMII); 557 } 558 559 static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 560 { 561 struct rk3328_grf_regs *grf; 562 enum { 563 RK3328_RMII_MODE_SHIFT = 9, 564 RK3328_RMII_MODE_MASK = BIT(9), 565 566 RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4, 567 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 568 RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 569 570 RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 571 RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 572 RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 573 574 RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 575 RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 576 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 577 }; 578 enum { 579 RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 580 RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 581 582 RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 583 RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 584 }; 585 586 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 587 rk_clrsetreg(&grf->mac_con[1], 588 RK3328_RMII_MODE_MASK | 589 RK3328_GMAC_PHY_INTF_SEL_MASK | 590 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 591 RK3328_TXCLK_DLY_ENA_GMAC_MASK, 592 RK3328_GMAC_PHY_INTF_SEL_RGMII | 593 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 594 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE); 595 596 rk_clrsetreg(&grf->mac_con[0], 597 RK3328_CLK_RX_DL_CFG_GMAC_MASK | 598 RK3328_CLK_TX_DL_CFG_GMAC_MASK, 599 pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT | 600 pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT); 601 } 602 603 static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 604 { 605 struct rk3368_grf *grf; 606 enum { 607 RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9, 608 RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9), 609 RK3368_RMII_MODE_MASK = BIT(6), 610 RK3368_RMII_MODE = BIT(6), 611 }; 612 enum { 613 RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15), 614 RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 615 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15), 616 RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7), 617 RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 618 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7), 619 RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8, 620 RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 621 RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0, 622 RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 623 }; 624 625 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 626 rk_clrsetreg(&grf->soc_con15, 627 RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK, 628 RK3368_GMAC_PHY_INTF_SEL_RGMII); 629 630 rk_clrsetreg(&grf->soc_con16, 631 RK3368_RXCLK_DLY_ENA_GMAC_MASK | 632 RK3368_TXCLK_DLY_ENA_GMAC_MASK | 633 RK3368_CLK_RX_DL_CFG_GMAC_MASK | 634 RK3368_CLK_TX_DL_CFG_GMAC_MASK, 635 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE | 636 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE | 637 pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT | 638 pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT); 639 } 640 641 static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 642 { 643 struct rk3399_grf_regs *grf; 644 645 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 646 647 rk_clrsetreg(&grf->soc_con5, 648 RK3399_GMAC_PHY_INTF_SEL_MASK, 649 RK3399_GMAC_PHY_INTF_SEL_RGMII); 650 651 rk_clrsetreg(&grf->soc_con6, 652 RK3399_RXCLK_DLY_ENA_GMAC_MASK | 653 RK3399_TXCLK_DLY_ENA_GMAC_MASK | 654 RK3399_CLK_RX_DL_CFG_GMAC_MASK | 655 RK3399_CLK_TX_DL_CFG_GMAC_MASK, 656 RK3399_RXCLK_DLY_ENA_GMAC_ENABLE | 657 RK3399_TXCLK_DLY_ENA_GMAC_ENABLE | 658 pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT | 659 pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT); 660 } 661 662 static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 663 { 664 struct rv1108_grf *grf; 665 666 enum { 667 RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 668 RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4, 669 }; 670 671 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 672 rk_clrsetreg(&grf->gmac_con0, 673 RV1108_GMAC_PHY_INTF_SEL_MASK, 674 RV1108_GMAC_PHY_INTF_SEL_RMII); 675 } 676 #endif 677 678 static int gmac_rockchip_probe(struct udevice *dev) 679 { 680 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 681 struct rk_gmac_ops *ops = 682 (struct rk_gmac_ops *)dev_get_driver_data(dev); 683 #ifdef CONFIG_DWC_ETH_QOS 684 struct eqos_config *config; 685 #else 686 struct dw_eth_pdata *dw_pdata; 687 #endif 688 struct eth_pdata *eth_pdata; 689 struct clk clk; 690 ulong rate; 691 int ret; 692 693 #ifdef CONFIG_DWC_ETH_QOS 694 eth_pdata = &pdata->eth_pdata; 695 config = (struct eqos_config *)&ops->config; 696 eth_pdata->phy_interface = config->ops->eqos_get_interface(dev); 697 #else 698 dw_pdata = &pdata->dw_eth_pdata; 699 eth_pdata = &dw_pdata->eth_pdata; 700 #endif 701 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 702 ret = clk_set_defaults(dev); 703 if (ret) 704 debug("%s clk_set_defaults failed %d\n", __func__, ret); 705 706 ret = clk_get_by_index(dev, 0, &clk); 707 if (ret) 708 return ret; 709 710 switch (eth_pdata->phy_interface) { 711 case PHY_INTERFACE_MODE_RGMII: 712 /* 713 * If the gmac clock is from internal pll, need to set and 714 * check the return value for gmac clock at RGMII mode. If 715 * the gmac clock is from external source, the clock rate 716 * is not set, because of it is bypassed. 717 */ 718 if (!pdata->clock_input) { 719 rate = clk_set_rate(&clk, 125000000); 720 if (rate != 125000000) 721 return -EINVAL; 722 } 723 724 /* Set to RGMII mode */ 725 if (ops->set_to_rgmii) 726 ops->set_to_rgmii(pdata); 727 else 728 return -EPERM; 729 730 break; 731 case PHY_INTERFACE_MODE_RMII: 732 /* The commet is the same as RGMII mode */ 733 if (!pdata->clock_input) { 734 rate = clk_set_rate(&clk, 50000000); 735 if (rate != 50000000) 736 return -EINVAL; 737 } 738 739 /* Set to RMII mode */ 740 if (ops->set_to_rmii) 741 ops->set_to_rmii(pdata); 742 else 743 return -EPERM; 744 745 break; 746 default: 747 debug("NO interface defined!\n"); 748 return -ENXIO; 749 } 750 751 #ifdef CONFIG_DWC_ETH_QOS 752 return eqos_probe(dev); 753 #else 754 return designware_eth_probe(dev); 755 #endif 756 } 757 758 static int gmac_rockchip_eth_write_hwaddr(struct udevice *dev) 759 { 760 #if defined(CONFIG_DWC_ETH_QOS) 761 return eqos_write_hwaddr(dev); 762 #else 763 return designware_eth_write_hwaddr(dev); 764 #endif 765 } 766 767 static int gmac_rockchip_eth_free_pkt(struct udevice *dev, uchar *packet, 768 int length) 769 { 770 #ifdef CONFIG_DWC_ETH_QOS 771 return eqos_free_pkt(dev, packet, length); 772 #else 773 return designware_eth_free_pkt(dev, packet, length); 774 #endif 775 } 776 777 static int gmac_rockchip_eth_send(struct udevice *dev, void *packet, 778 int length) 779 { 780 #ifdef CONFIG_DWC_ETH_QOS 781 return eqos_send(dev, packet, length); 782 #else 783 return designware_eth_send(dev, packet, length); 784 #endif 785 } 786 787 static int gmac_rockchip_eth_recv(struct udevice *dev, int flags, 788 uchar **packetp) 789 { 790 #ifdef CONFIG_DWC_ETH_QOS 791 return eqos_recv(dev, flags, packetp); 792 #else 793 return designware_eth_recv(dev, flags, packetp); 794 #endif 795 } 796 797 static int gmac_rockchip_eth_start(struct udevice *dev) 798 { 799 struct rockchip_eth_dev *priv = dev_get_priv(dev); 800 struct rk_gmac_ops *ops = 801 (struct rk_gmac_ops *)dev_get_driver_data(dev); 802 #ifndef CONFIG_DWC_ETH_QOS 803 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 804 struct dw_eth_pdata *dw_pdata; 805 struct eth_pdata *eth_pdata; 806 #endif 807 int ret; 808 809 #ifdef CONFIG_DWC_ETH_QOS 810 ret = eqos_init(dev); 811 #else 812 dw_pdata = &pdata->dw_eth_pdata; 813 eth_pdata = &dw_pdata->eth_pdata; 814 ret = designware_eth_init((struct dw_eth_dev *)priv, 815 eth_pdata->enetaddr); 816 #endif 817 if (ret) 818 return ret; 819 ret = ops->fix_mac_speed(priv); 820 if (ret) 821 return ret; 822 823 #ifdef CONFIG_DWC_ETH_QOS 824 eqos_enable(dev); 825 #else 826 ret = designware_eth_enable((struct dw_eth_dev *)priv); 827 if (ret) 828 return ret; 829 #endif 830 831 return 0; 832 } 833 834 static void gmac_rockchip_eth_stop(struct udevice *dev) 835 { 836 #ifdef CONFIG_DWC_ETH_QOS 837 eqos_stop(dev); 838 #else 839 designware_eth_stop(dev); 840 #endif 841 } 842 843 const struct eth_ops gmac_rockchip_eth_ops = { 844 .start = gmac_rockchip_eth_start, 845 .send = gmac_rockchip_eth_send, 846 .recv = gmac_rockchip_eth_recv, 847 .free_pkt = gmac_rockchip_eth_free_pkt, 848 .stop = gmac_rockchip_eth_stop, 849 .write_hwaddr = gmac_rockchip_eth_write_hwaddr, 850 }; 851 852 #ifndef CONFIG_DWC_ETH_QOS 853 const struct rk_gmac_ops px30_gmac_ops = { 854 .fix_mac_speed = px30_gmac_fix_mac_speed, 855 .set_to_rmii = px30_gmac_set_to_rmii, 856 }; 857 858 const struct rk_gmac_ops rk1808_gmac_ops = { 859 .fix_mac_speed = rk1808_gmac_fix_mac_speed, 860 .set_to_rgmii = rk1808_gmac_set_to_rgmii, 861 }; 862 863 const struct rk_gmac_ops rk3228_gmac_ops = { 864 .fix_mac_speed = rk3228_gmac_fix_mac_speed, 865 .set_to_rgmii = rk3228_gmac_set_to_rgmii, 866 }; 867 868 const struct rk_gmac_ops rk3288_gmac_ops = { 869 .fix_mac_speed = rk3288_gmac_fix_mac_speed, 870 .set_to_rgmii = rk3288_gmac_set_to_rgmii, 871 }; 872 873 const struct rk_gmac_ops rk3308_gmac_ops = { 874 .fix_mac_speed = rk3308_gmac_fix_mac_speed, 875 .set_to_rmii = rk3308_gmac_set_to_rmii, 876 }; 877 878 const struct rk_gmac_ops rk3328_gmac_ops = { 879 .fix_mac_speed = rk3328_gmac_fix_mac_speed, 880 .set_to_rgmii = rk3328_gmac_set_to_rgmii, 881 }; 882 883 const struct rk_gmac_ops rk3368_gmac_ops = { 884 .fix_mac_speed = rk3368_gmac_fix_mac_speed, 885 .set_to_rgmii = rk3368_gmac_set_to_rgmii, 886 }; 887 888 const struct rk_gmac_ops rk3399_gmac_ops = { 889 .fix_mac_speed = rk3399_gmac_fix_mac_speed, 890 .set_to_rgmii = rk3399_gmac_set_to_rgmii, 891 }; 892 893 const struct rk_gmac_ops rv1108_gmac_ops = { 894 .fix_mac_speed = rv1108_set_rmii_speed, 895 .set_to_rmii = rv1108_gmac_set_to_rmii, 896 }; 897 #endif 898 899 static const struct udevice_id rockchip_gmac_ids[] = { 900 #ifndef CONFIG_DWC_ETH_QOS 901 { .compatible = "rockchip,px30-gmac", 902 .data = (ulong)&px30_gmac_ops }, 903 { .compatible = "rockchip,rk1808-gmac", 904 .data = (ulong)&rk1808_gmac_ops }, 905 { .compatible = "rockchip,rk3228-gmac", 906 .data = (ulong)&rk3228_gmac_ops }, 907 { .compatible = "rockchip,rk3288-gmac", 908 .data = (ulong)&rk3288_gmac_ops }, 909 { .compatible = "rockchip,rk3308-mac", 910 .data = (ulong)&rk3308_gmac_ops }, 911 { .compatible = "rockchip,rk3328-gmac", 912 .data = (ulong)&rk3328_gmac_ops }, 913 { .compatible = "rockchip,rk3368-gmac", 914 .data = (ulong)&rk3368_gmac_ops }, 915 { .compatible = "rockchip,rk3399-gmac", 916 .data = (ulong)&rk3399_gmac_ops }, 917 { .compatible = "rockchip,rv1108-gmac", 918 .data = (ulong)&rv1108_gmac_ops }, 919 #endif 920 { } 921 }; 922 923 U_BOOT_DRIVER(eth_gmac_rockchip) = { 924 .name = "gmac_rockchip", 925 .id = UCLASS_ETH, 926 .of_match = rockchip_gmac_ids, 927 .ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata, 928 .probe = gmac_rockchip_probe, 929 .ops = &gmac_rockchip_eth_ops, 930 .priv_auto_alloc_size = sizeof(struct rockchip_eth_dev), 931 .platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata), 932 .flags = DM_FLAG_ALLOC_PRIV_DMA, 933 }; 934