1 /* 2 * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Rockchip GMAC ethernet IP driver for U-Boot 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <clk.h> 12 #include <phy.h> 13 #include <syscon.h> 14 #include <asm/io.h> 15 #include <asm/arch/periph.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/hardware.h> 18 #include <asm/arch/grf_px30.h> 19 #include <asm/arch/grf_rk322x.h> 20 #include <asm/arch/grf_rk3288.h> 21 #include <asm/arch/grf_rk3308.h> 22 #include <asm/arch/grf_rk3328.h> 23 #include <asm/arch/grf_rk3368.h> 24 #include <asm/arch/grf_rk3399.h> 25 #include <asm/arch/grf_rv1108.h> 26 #include <dm/pinctrl.h> 27 #include <dt-bindings/clock/rk3288-cru.h> 28 #include "designware.h" 29 30 DECLARE_GLOBAL_DATA_PTR; 31 32 /* 33 * Platform data for the gmac 34 * 35 * dw_eth_pdata: Required platform data for designware driver (must be first) 36 */ 37 struct gmac_rockchip_platdata { 38 struct dw_eth_pdata dw_eth_pdata; 39 bool clock_input; 40 int tx_delay; 41 int rx_delay; 42 }; 43 44 struct rk_gmac_ops { 45 int (*fix_mac_speed)(struct dw_eth_dev *priv); 46 void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata); 47 void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata); 48 }; 49 50 void gmac_set_rgmii(struct udevice *dev, u32 tx_delay, u32 rx_delay) 51 { 52 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 53 struct rk_gmac_ops *ops = 54 (struct rk_gmac_ops *)dev_get_driver_data(dev); 55 56 pdata->tx_delay = tx_delay; 57 pdata->rx_delay = rx_delay; 58 59 ops->set_to_rgmii(pdata); 60 } 61 62 static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) 63 { 64 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 65 const char *string; 66 67 string = dev_read_string(dev, "clock_in_out"); 68 if (!strcmp(string, "input")) 69 pdata->clock_input = true; 70 else 71 pdata->clock_input = false; 72 73 /* Check the new naming-style first... */ 74 pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT); 75 pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT); 76 77 /* ... and fall back to the old naming style or default, if necessary */ 78 if (pdata->tx_delay == -ENOENT) 79 pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30); 80 if (pdata->rx_delay == -ENOENT) 81 pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10); 82 83 return designware_eth_ofdata_to_platdata(dev); 84 } 85 86 static int px30_gmac_fix_mac_speed(struct dw_eth_dev *priv) 87 { 88 struct px30_grf *grf; 89 struct clk clk_speed; 90 int speed, ret; 91 enum { 92 PX30_GMAC_SPEED_SHIFT = 0x2, 93 PX30_GMAC_SPEED_MASK = BIT(2), 94 PX30_GMAC_SPEED_10M = 0, 95 PX30_GMAC_SPEED_100M = BIT(2), 96 }; 97 98 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 99 &clk_speed); 100 if (ret) 101 return ret; 102 103 switch (priv->phydev->speed) { 104 case 10: 105 speed = PX30_GMAC_SPEED_10M; 106 ret = clk_set_rate(&clk_speed, 2500000); 107 if (ret) 108 return ret; 109 break; 110 case 100: 111 speed = PX30_GMAC_SPEED_100M; 112 ret = clk_set_rate(&clk_speed, 25000000); 113 if (ret) 114 return ret; 115 break; 116 default: 117 debug("Unknown phy speed: %d\n", priv->phydev->speed); 118 return -EINVAL; 119 } 120 121 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 122 rk_clrsetreg(&grf->mac_con1, PX30_GMAC_SPEED_MASK, speed); 123 124 return 0; 125 } 126 127 static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv) 128 { 129 struct rk322x_grf *grf; 130 int clk; 131 enum { 132 RK3228_GMAC_CLK_SEL_SHIFT = 8, 133 RK3228_GMAC_CLK_SEL_MASK = GENMASK(9, 8), 134 RK3228_GMAC_CLK_SEL_125M = 0 << 8, 135 RK3228_GMAC_CLK_SEL_25M = 3 << 8, 136 RK3228_GMAC_CLK_SEL_2_5M = 2 << 8, 137 }; 138 139 switch (priv->phydev->speed) { 140 case 10: 141 clk = RK3228_GMAC_CLK_SEL_2_5M; 142 break; 143 case 100: 144 clk = RK3228_GMAC_CLK_SEL_25M; 145 break; 146 case 1000: 147 clk = RK3228_GMAC_CLK_SEL_125M; 148 break; 149 default: 150 debug("Unknown phy speed: %d\n", priv->phydev->speed); 151 return -EINVAL; 152 } 153 154 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 155 rk_clrsetreg(&grf->mac_con[1], RK3228_GMAC_CLK_SEL_MASK, clk); 156 157 return 0; 158 } 159 160 static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv) 161 { 162 struct rk3288_grf *grf; 163 int clk; 164 165 switch (priv->phydev->speed) { 166 case 10: 167 clk = RK3288_GMAC_CLK_SEL_2_5M; 168 break; 169 case 100: 170 clk = RK3288_GMAC_CLK_SEL_25M; 171 break; 172 case 1000: 173 clk = RK3288_GMAC_CLK_SEL_125M; 174 break; 175 default: 176 debug("Unknown phy speed: %d\n", priv->phydev->speed); 177 return -EINVAL; 178 } 179 180 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 181 rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk); 182 183 return 0; 184 } 185 186 static int rk3308_gmac_fix_mac_speed(struct dw_eth_dev *priv) 187 { 188 struct rk3308_grf *grf; 189 struct clk clk_speed; 190 int speed, ret; 191 enum { 192 RK3308_GMAC_SPEED_SHIFT = 0x0, 193 RK3308_GMAC_SPEED_MASK = BIT(0), 194 RK3308_GMAC_SPEED_10M = 0, 195 RK3308_GMAC_SPEED_100M = BIT(0), 196 }; 197 198 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 199 &clk_speed); 200 if (ret) 201 return ret; 202 203 switch (priv->phydev->speed) { 204 case 10: 205 speed = RK3308_GMAC_SPEED_10M; 206 ret = clk_set_rate(&clk_speed, 2500000); 207 if (ret) 208 return ret; 209 break; 210 case 100: 211 speed = RK3308_GMAC_SPEED_100M; 212 ret = clk_set_rate(&clk_speed, 25000000); 213 if (ret) 214 return ret; 215 break; 216 default: 217 debug("Unknown phy speed: %d\n", priv->phydev->speed); 218 return -EINVAL; 219 } 220 221 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 222 rk_clrsetreg(&grf->mac_con0, RK3308_GMAC_SPEED_MASK, speed); 223 224 return 0; 225 } 226 227 static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv) 228 { 229 struct rk3328_grf_regs *grf; 230 int clk; 231 enum { 232 RK3328_GMAC_CLK_SEL_SHIFT = 11, 233 RK3328_GMAC_CLK_SEL_MASK = GENMASK(12, 11), 234 RK3328_GMAC_CLK_SEL_125M = 0 << 11, 235 RK3328_GMAC_CLK_SEL_25M = 3 << 11, 236 RK3328_GMAC_CLK_SEL_2_5M = 2 << 11, 237 }; 238 239 switch (priv->phydev->speed) { 240 case 10: 241 clk = RK3328_GMAC_CLK_SEL_2_5M; 242 break; 243 case 100: 244 clk = RK3328_GMAC_CLK_SEL_25M; 245 break; 246 case 1000: 247 clk = RK3328_GMAC_CLK_SEL_125M; 248 break; 249 default: 250 debug("Unknown phy speed: %d\n", priv->phydev->speed); 251 return -EINVAL; 252 } 253 254 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 255 rk_clrsetreg(&grf->mac_con[1], RK3328_GMAC_CLK_SEL_MASK, clk); 256 257 return 0; 258 } 259 260 static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv) 261 { 262 struct rk3368_grf *grf; 263 int clk; 264 enum { 265 RK3368_GMAC_CLK_SEL_2_5M = 2 << 4, 266 RK3368_GMAC_CLK_SEL_25M = 3 << 4, 267 RK3368_GMAC_CLK_SEL_125M = 0 << 4, 268 RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4), 269 }; 270 271 switch (priv->phydev->speed) { 272 case 10: 273 clk = RK3368_GMAC_CLK_SEL_2_5M; 274 break; 275 case 100: 276 clk = RK3368_GMAC_CLK_SEL_25M; 277 break; 278 case 1000: 279 clk = RK3368_GMAC_CLK_SEL_125M; 280 break; 281 default: 282 debug("Unknown phy speed: %d\n", priv->phydev->speed); 283 return -EINVAL; 284 } 285 286 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 287 rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk); 288 289 return 0; 290 } 291 292 static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv) 293 { 294 struct rk3399_grf_regs *grf; 295 int clk; 296 297 switch (priv->phydev->speed) { 298 case 10: 299 clk = RK3399_GMAC_CLK_SEL_2_5M; 300 break; 301 case 100: 302 clk = RK3399_GMAC_CLK_SEL_25M; 303 break; 304 case 1000: 305 clk = RK3399_GMAC_CLK_SEL_125M; 306 break; 307 default: 308 debug("Unknown phy speed: %d\n", priv->phydev->speed); 309 return -EINVAL; 310 } 311 312 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 313 rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk); 314 315 return 0; 316 } 317 318 static int rv1108_set_rmii_speed(struct dw_eth_dev *priv) 319 { 320 struct rv1108_grf *grf; 321 int clk, speed; 322 enum { 323 RV1108_GMAC_SPEED_MASK = BIT(2), 324 RV1108_GMAC_SPEED_10M = 0 << 2, 325 RV1108_GMAC_SPEED_100M = 1 << 2, 326 RV1108_GMAC_CLK_SEL_MASK = BIT(7), 327 RV1108_GMAC_CLK_SEL_2_5M = 0 << 7, 328 RV1108_GMAC_CLK_SEL_25M = 1 << 7, 329 }; 330 331 switch (priv->phydev->speed) { 332 case 10: 333 clk = RV1108_GMAC_CLK_SEL_2_5M; 334 speed = RV1108_GMAC_SPEED_10M; 335 break; 336 case 100: 337 clk = RV1108_GMAC_CLK_SEL_25M; 338 speed = RV1108_GMAC_SPEED_100M; 339 break; 340 default: 341 debug("Unknown phy speed: %d\n", priv->phydev->speed); 342 return -EINVAL; 343 } 344 345 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 346 rk_clrsetreg(&grf->gmac_con0, 347 RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK, 348 clk | speed); 349 350 return 0; 351 } 352 353 static void px30_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 354 { 355 struct px30_grf *grf; 356 enum { 357 px30_GMAC_PHY_INTF_SEL_SHIFT = 4, 358 px30_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 6), 359 px30_GMAC_PHY_INTF_SEL_RMII = BIT(6), 360 }; 361 362 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 363 364 rk_clrsetreg(&grf->mac_con1, 365 px30_GMAC_PHY_INTF_SEL_MASK, 366 px30_GMAC_PHY_INTF_SEL_RMII); 367 } 368 369 static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 370 { 371 struct rk322x_grf *grf; 372 enum { 373 RK3228_RMII_MODE_SHIFT = 10, 374 RK3228_RMII_MODE_MASK = BIT(10), 375 376 RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4, 377 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 378 RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 379 380 RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 381 RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 382 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 383 384 RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 385 RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 386 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 387 }; 388 enum { 389 RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 390 RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 391 392 RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 393 RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 394 }; 395 396 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 397 rk_clrsetreg(&grf->mac_con[1], 398 RK3228_RMII_MODE_MASK | 399 RK3228_GMAC_PHY_INTF_SEL_MASK | 400 RK3228_RXCLK_DLY_ENA_GMAC_MASK | 401 RK3228_TXCLK_DLY_ENA_GMAC_MASK, 402 RK3228_GMAC_PHY_INTF_SEL_RGMII | 403 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE | 404 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE); 405 406 rk_clrsetreg(&grf->mac_con[0], 407 RK3228_CLK_RX_DL_CFG_GMAC_MASK | 408 RK3228_CLK_TX_DL_CFG_GMAC_MASK, 409 pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT | 410 pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT); 411 } 412 413 static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 414 { 415 struct rk3288_grf *grf; 416 417 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 418 rk_clrsetreg(&grf->soc_con1, 419 RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK, 420 RK3288_GMAC_PHY_INTF_SEL_RGMII); 421 422 rk_clrsetreg(&grf->soc_con3, 423 RK3288_RXCLK_DLY_ENA_GMAC_MASK | 424 RK3288_TXCLK_DLY_ENA_GMAC_MASK | 425 RK3288_CLK_RX_DL_CFG_GMAC_MASK | 426 RK3288_CLK_TX_DL_CFG_GMAC_MASK, 427 RK3288_RXCLK_DLY_ENA_GMAC_ENABLE | 428 RK3288_TXCLK_DLY_ENA_GMAC_ENABLE | 429 pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT | 430 pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT); 431 } 432 433 static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 434 { 435 struct rk3308_grf *grf; 436 enum { 437 RK3308_GMAC_PHY_INTF_SEL_SHIFT = 2, 438 RK3308_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 2), 439 RK3308_GMAC_PHY_INTF_SEL_RMII = BIT(4), 440 }; 441 442 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 443 444 rk_clrsetreg(&grf->mac_con0, 445 RK3308_GMAC_PHY_INTF_SEL_MASK, 446 RK3308_GMAC_PHY_INTF_SEL_RMII); 447 } 448 449 static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 450 { 451 struct rk3328_grf_regs *grf; 452 enum { 453 RK3328_RMII_MODE_SHIFT = 9, 454 RK3328_RMII_MODE_MASK = BIT(9), 455 456 RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4, 457 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 458 RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 459 460 RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 461 RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 462 RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 463 464 RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 465 RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 466 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 467 }; 468 enum { 469 RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 470 RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 471 472 RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 473 RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 474 }; 475 476 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 477 rk_clrsetreg(&grf->mac_con[1], 478 RK3328_RMII_MODE_MASK | 479 RK3328_GMAC_PHY_INTF_SEL_MASK | 480 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 481 RK3328_TXCLK_DLY_ENA_GMAC_MASK, 482 RK3328_GMAC_PHY_INTF_SEL_RGMII | 483 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 484 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE); 485 486 rk_clrsetreg(&grf->mac_con[0], 487 RK3328_CLK_RX_DL_CFG_GMAC_MASK | 488 RK3328_CLK_TX_DL_CFG_GMAC_MASK, 489 pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT | 490 pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT); 491 } 492 493 static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 494 { 495 struct rk3368_grf *grf; 496 enum { 497 RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9, 498 RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9), 499 RK3368_RMII_MODE_MASK = BIT(6), 500 RK3368_RMII_MODE = BIT(6), 501 }; 502 enum { 503 RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15), 504 RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 505 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15), 506 RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7), 507 RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 508 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7), 509 RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8, 510 RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 511 RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0, 512 RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 513 }; 514 515 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 516 rk_clrsetreg(&grf->soc_con15, 517 RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK, 518 RK3368_GMAC_PHY_INTF_SEL_RGMII); 519 520 rk_clrsetreg(&grf->soc_con16, 521 RK3368_RXCLK_DLY_ENA_GMAC_MASK | 522 RK3368_TXCLK_DLY_ENA_GMAC_MASK | 523 RK3368_CLK_RX_DL_CFG_GMAC_MASK | 524 RK3368_CLK_TX_DL_CFG_GMAC_MASK, 525 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE | 526 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE | 527 pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT | 528 pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT); 529 } 530 531 static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 532 { 533 struct rk3399_grf_regs *grf; 534 535 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 536 537 rk_clrsetreg(&grf->soc_con5, 538 RK3399_GMAC_PHY_INTF_SEL_MASK, 539 RK3399_GMAC_PHY_INTF_SEL_RGMII); 540 541 rk_clrsetreg(&grf->soc_con6, 542 RK3399_RXCLK_DLY_ENA_GMAC_MASK | 543 RK3399_TXCLK_DLY_ENA_GMAC_MASK | 544 RK3399_CLK_RX_DL_CFG_GMAC_MASK | 545 RK3399_CLK_TX_DL_CFG_GMAC_MASK, 546 RK3399_RXCLK_DLY_ENA_GMAC_ENABLE | 547 RK3399_TXCLK_DLY_ENA_GMAC_ENABLE | 548 pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT | 549 pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT); 550 } 551 552 static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 553 { 554 struct rv1108_grf *grf; 555 556 enum { 557 RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 558 RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4, 559 }; 560 561 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 562 rk_clrsetreg(&grf->gmac_con0, 563 RV1108_GMAC_PHY_INTF_SEL_MASK, 564 RV1108_GMAC_PHY_INTF_SEL_RMII); 565 } 566 567 static int gmac_rockchip_probe(struct udevice *dev) 568 { 569 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 570 struct rk_gmac_ops *ops = 571 (struct rk_gmac_ops *)dev_get_driver_data(dev); 572 struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev); 573 struct eth_pdata *eth_pdata = &dw_pdata->eth_pdata; 574 struct clk clk; 575 ulong rate; 576 int ret; 577 578 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 579 ret = clk_set_defaults(dev); 580 if (ret) 581 debug("%s clk_set_defaults failed %d\n", __func__, ret); 582 583 ret = clk_get_by_index(dev, 0, &clk); 584 if (ret) 585 return ret; 586 587 switch (eth_pdata->phy_interface) { 588 case PHY_INTERFACE_MODE_RGMII: 589 /* 590 * If the gmac clock is from internal pll, need to set and 591 * check the return value for gmac clock at RGMII mode. If 592 * the gmac clock is from external source, the clock rate 593 * is not set, because of it is bypassed. 594 */ 595 if (!pdata->clock_input) { 596 rate = clk_set_rate(&clk, 125000000); 597 if (rate != 125000000) 598 return -EINVAL; 599 } 600 601 /* Set to RGMII mode */ 602 if (ops->set_to_rgmii) 603 ops->set_to_rgmii(pdata); 604 else 605 return -EPERM; 606 607 break; 608 case PHY_INTERFACE_MODE_RMII: 609 /* The commet is the same as RGMII mode */ 610 if (!pdata->clock_input) { 611 rate = clk_set_rate(&clk, 50000000); 612 if (rate != 50000000) 613 return -EINVAL; 614 } 615 616 /* Set to RMII mode */ 617 if (ops->set_to_rmii) 618 ops->set_to_rmii(pdata); 619 else 620 return -EPERM; 621 622 break; 623 default: 624 debug("NO interface defined!\n"); 625 return -ENXIO; 626 } 627 628 return designware_eth_probe(dev); 629 } 630 631 static int gmac_rockchip_eth_start(struct udevice *dev) 632 { 633 struct eth_pdata *pdata = dev_get_platdata(dev); 634 struct dw_eth_dev *priv = dev_get_priv(dev); 635 struct rk_gmac_ops *ops = 636 (struct rk_gmac_ops *)dev_get_driver_data(dev); 637 int ret; 638 639 ret = designware_eth_init(priv, pdata->enetaddr); 640 if (ret) 641 return ret; 642 ret = ops->fix_mac_speed(priv); 643 if (ret) 644 return ret; 645 ret = designware_eth_enable(priv); 646 if (ret) 647 return ret; 648 649 return 0; 650 } 651 652 const struct eth_ops gmac_rockchip_eth_ops = { 653 .start = gmac_rockchip_eth_start, 654 .send = designware_eth_send, 655 .recv = designware_eth_recv, 656 .free_pkt = designware_eth_free_pkt, 657 .stop = designware_eth_stop, 658 .write_hwaddr = designware_eth_write_hwaddr, 659 }; 660 661 const struct rk_gmac_ops px30_gmac_ops = { 662 .fix_mac_speed = px30_gmac_fix_mac_speed, 663 .set_to_rmii = px30_gmac_set_to_rmii, 664 }; 665 666 const struct rk_gmac_ops rk3228_gmac_ops = { 667 .fix_mac_speed = rk3228_gmac_fix_mac_speed, 668 .set_to_rgmii = rk3228_gmac_set_to_rgmii, 669 }; 670 671 const struct rk_gmac_ops rk3288_gmac_ops = { 672 .fix_mac_speed = rk3288_gmac_fix_mac_speed, 673 .set_to_rgmii = rk3288_gmac_set_to_rgmii, 674 }; 675 676 const struct rk_gmac_ops rk3308_gmac_ops = { 677 .fix_mac_speed = rk3308_gmac_fix_mac_speed, 678 .set_to_rmii = rk3308_gmac_set_to_rmii, 679 }; 680 681 const struct rk_gmac_ops rk3328_gmac_ops = { 682 .fix_mac_speed = rk3328_gmac_fix_mac_speed, 683 .set_to_rgmii = rk3328_gmac_set_to_rgmii, 684 }; 685 686 const struct rk_gmac_ops rk3368_gmac_ops = { 687 .fix_mac_speed = rk3368_gmac_fix_mac_speed, 688 .set_to_rgmii = rk3368_gmac_set_to_rgmii, 689 }; 690 691 const struct rk_gmac_ops rk3399_gmac_ops = { 692 .fix_mac_speed = rk3399_gmac_fix_mac_speed, 693 .set_to_rgmii = rk3399_gmac_set_to_rgmii, 694 }; 695 696 const struct rk_gmac_ops rv1108_gmac_ops = { 697 .fix_mac_speed = rv1108_set_rmii_speed, 698 .set_to_rmii = rv1108_gmac_set_to_rmii, 699 }; 700 701 static const struct udevice_id rockchip_gmac_ids[] = { 702 { .compatible = "rockchip,px30-gmac", 703 .data = (ulong)&px30_gmac_ops }, 704 { .compatible = "rockchip,rk3228-gmac", 705 .data = (ulong)&rk3228_gmac_ops }, 706 { .compatible = "rockchip,rk3288-gmac", 707 .data = (ulong)&rk3288_gmac_ops }, 708 { .compatible = "rockchip,rk3308-mac", 709 .data = (ulong)&rk3308_gmac_ops }, 710 { .compatible = "rockchip,rk3328-gmac", 711 .data = (ulong)&rk3328_gmac_ops }, 712 { .compatible = "rockchip,rk3368-gmac", 713 .data = (ulong)&rk3368_gmac_ops }, 714 { .compatible = "rockchip,rk3399-gmac", 715 .data = (ulong)&rk3399_gmac_ops }, 716 { .compatible = "rockchip,rv1108-gmac", 717 .data = (ulong)&rv1108_gmac_ops }, 718 { } 719 }; 720 721 U_BOOT_DRIVER(eth_gmac_rockchip) = { 722 .name = "gmac_rockchip", 723 .id = UCLASS_ETH, 724 .of_match = rockchip_gmac_ids, 725 .ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata, 726 .probe = gmac_rockchip_probe, 727 .ops = &gmac_rockchip_eth_ops, 728 .priv_auto_alloc_size = sizeof(struct dw_eth_dev), 729 .platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata), 730 .flags = DM_FLAG_ALLOC_PRIV_DMA, 731 }; 732