1 /* 2 * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Rockchip GMAC ethernet IP driver for U-Boot 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <clk.h> 12 #include <misc.h> 13 #include <phy.h> 14 #include <reset.h> 15 #include <syscon.h> 16 #include <asm/io.h> 17 #include <asm/arch/periph.h> 18 #include <asm/arch/clock.h> 19 #include <asm/arch/hardware.h> 20 #ifdef CONFIG_DWC_ETH_QOS 21 #include <asm/arch/grf_rk3528.h> 22 #include <asm/arch/grf_rk3568.h> 23 #include <asm/arch/grf_rk3588.h> 24 #include <asm/arch/grf_rv1106.h> 25 #include <asm/arch/grf_rv1126.h> 26 #include "dwc_eth_qos.h" 27 #else 28 #include <asm/arch/grf_px30.h> 29 #include <asm/arch/grf_rk1808.h> 30 #include <asm/arch/grf_rk322x.h> 31 #include <asm/arch/grf_rk3288.h> 32 #include <asm/arch/grf_rk3308.h> 33 #include <asm/arch/grf_rk3328.h> 34 #include <asm/arch/grf_rk3368.h> 35 #include <asm/arch/grf_rk3399.h> 36 #include <asm/arch/grf_rv1108.h> 37 #include "designware.h" 38 #include <dt-bindings/clock/rk3288-cru.h> 39 #endif 40 #include <dm/pinctrl.h> 41 #include <dm/of_access.h> 42 43 DECLARE_GLOBAL_DATA_PTR; 44 45 struct rockchip_eth_dev { 46 #ifdef CONFIG_DWC_ETH_QOS 47 struct eqos_priv eqos; 48 #else 49 struct dw_eth_dev dw; 50 #endif 51 int phy_interface; 52 }; 53 54 /* 55 * Platform data for the gmac 56 * 57 * dw_eth_pdata: Required platform data for designware driver (must be first) 58 */ 59 struct gmac_rockchip_platdata { 60 #ifndef CONFIG_DWC_ETH_QOS 61 struct dw_eth_pdata dw_eth_pdata; 62 #else 63 struct eth_pdata eth_pdata; 64 #endif 65 struct reset_ctl phy_reset; 66 bool integrated_phy; 67 bool clock_input; 68 int phy_interface; 69 int tx_delay; 70 int rx_delay; 71 int bus_id; 72 }; 73 74 struct rk_gmac_ops { 75 #ifdef CONFIG_DWC_ETH_QOS 76 const struct eqos_config config; 77 #endif 78 int (*fix_mac_speed)(struct gmac_rockchip_platdata *pdata, 79 struct rockchip_eth_dev *dev); 80 void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata); 81 void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata); 82 void (*set_clock_selection)(struct gmac_rockchip_platdata *pdata); 83 void (*integrated_phy_powerup)(struct gmac_rockchip_platdata *pdata); 84 }; 85 86 #ifdef CONFIG_DWC_ETH_QOS 87 static const struct eqos_config eqos_rockchip_config = { 88 .reg_access_always_ok = false, 89 .mdio_wait = 10000, 90 .swr_wait = 200, 91 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED, 92 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_100_150, 93 .ops = &eqos_rockchip_ops, 94 }; 95 #endif 96 97 void gmac_set_rgmii(struct udevice *dev, u32 tx_delay, u32 rx_delay) 98 { 99 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 100 struct rk_gmac_ops *ops = 101 (struct rk_gmac_ops *)dev_get_driver_data(dev); 102 103 pdata->tx_delay = tx_delay; 104 pdata->rx_delay = rx_delay; 105 106 ops->set_to_rgmii(pdata); 107 } 108 109 static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) 110 { 111 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 112 struct ofnode_phandle_args args; 113 struct udevice *phydev; 114 const char *string; 115 int ret; 116 117 string = dev_read_string(dev, "clock_in_out"); 118 if (!strcmp(string, "input")) 119 pdata->clock_input = true; 120 else 121 pdata->clock_input = false; 122 123 /* If phy-handle property is passed from DT, use it as the PHY */ 124 ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &args); 125 if (ret) { 126 debug("Cannot get phy phandle: ret=%d\n", ret); 127 pdata->integrated_phy = dev_read_bool(dev, "phy-is-integrated"); 128 } else { 129 debug("Found phy-handle subnode\n"); 130 pdata->integrated_phy = ofnode_read_bool(args.node, 131 "phy-is-integrated"); 132 } 133 134 if (pdata->integrated_phy) { 135 ret = reset_get_by_name(dev, "mac-phy", &pdata->phy_reset); 136 if (ret) { 137 ret = uclass_get_device_by_ofnode(UCLASS_ETH_PHY, args.node, &phydev); 138 if (ret) { 139 debug("Get phydev by ofnode failed: err=%d\n", ret); 140 return ret; 141 } 142 143 ret = reset_get_by_index(phydev, 0, &pdata->phy_reset); 144 if (ret) { 145 debug("No PHY reset control found: ret=%d\n", ret); 146 return ret; 147 } 148 } 149 } 150 151 /* Check the new naming-style first... */ 152 pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT); 153 pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT); 154 155 /* ... and fall back to the old naming style or default, if necessary */ 156 if (pdata->tx_delay == -ENOENT) 157 pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30); 158 if (pdata->rx_delay == -ENOENT) 159 pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10); 160 161 #ifdef CONFIG_DWC_ETH_QOS 162 return 0; 163 #else 164 return designware_eth_ofdata_to_platdata(dev); 165 #endif 166 } 167 168 #ifndef CONFIG_DWC_ETH_QOS 169 static int px30_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 170 struct rockchip_eth_dev *dev) 171 { 172 struct dw_eth_dev *priv = &dev->dw; 173 struct px30_grf *grf; 174 struct clk clk_speed; 175 int speed, ret; 176 enum { 177 PX30_GMAC_SPEED_SHIFT = 0x2, 178 PX30_GMAC_SPEED_MASK = BIT(2), 179 PX30_GMAC_SPEED_10M = 0, 180 PX30_GMAC_SPEED_100M = BIT(2), 181 }; 182 183 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 184 &clk_speed); 185 if (ret) 186 return ret; 187 188 switch (priv->phydev->speed) { 189 case 10: 190 speed = PX30_GMAC_SPEED_10M; 191 ret = clk_set_rate(&clk_speed, 2500000); 192 if (ret) 193 return ret; 194 break; 195 case 100: 196 speed = PX30_GMAC_SPEED_100M; 197 ret = clk_set_rate(&clk_speed, 25000000); 198 if (ret) 199 return ret; 200 break; 201 default: 202 debug("Unknown phy speed: %d\n", priv->phydev->speed); 203 return -EINVAL; 204 } 205 206 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 207 rk_clrsetreg(&grf->mac_con1, PX30_GMAC_SPEED_MASK, speed); 208 209 return 0; 210 } 211 212 static int rk1808_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 213 struct rockchip_eth_dev *dev) 214 { 215 struct dw_eth_dev *priv = &dev->dw; 216 struct clk clk_speed; 217 int ret; 218 219 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 220 &clk_speed); 221 if (ret) 222 return ret; 223 224 switch (priv->phydev->speed) { 225 case 10: 226 ret = clk_set_rate(&clk_speed, 2500000); 227 if (ret) 228 return ret; 229 break; 230 case 100: 231 ret = clk_set_rate(&clk_speed, 25000000); 232 if (ret) 233 return ret; 234 break; 235 case 1000: 236 ret = clk_set_rate(&clk_speed, 125000000); 237 if (ret) 238 return ret; 239 break; 240 default: 241 debug("Unknown phy speed: %d\n", priv->phydev->speed); 242 return -EINVAL; 243 } 244 245 return 0; 246 } 247 248 static int rk3228_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 249 struct rockchip_eth_dev *dev) 250 { 251 struct dw_eth_dev *priv = &dev->dw; 252 struct rk322x_grf *grf; 253 int clk; 254 enum { 255 RK3228_GMAC_CLK_SEL_SHIFT = 8, 256 RK3228_GMAC_CLK_SEL_MASK = GENMASK(9, 8), 257 RK3228_GMAC_CLK_SEL_125M = 0 << 8, 258 RK3228_GMAC_CLK_SEL_25M = 3 << 8, 259 RK3228_GMAC_CLK_SEL_2_5M = 2 << 8, 260 261 RK3228_GMAC_RMII_CLK_MASK = BIT(7), 262 RK3228_GMAC_RMII_CLK_2_5M = 0, 263 RK3228_GMAC_RMII_CLK_25M = BIT(7), 264 265 RK3228_GMAC_RMII_SPEED_MASK = BIT(2), 266 RK3228_GMAC_RMII_SPEED_10 = 0, 267 RK3228_GMAC_RMII_SPEED_100 = BIT(2), 268 }; 269 270 switch (priv->phydev->speed) { 271 case 10: 272 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 273 (RK3228_GMAC_RMII_CLK_2_5M | RK3228_GMAC_RMII_SPEED_10) : 274 RK3228_GMAC_CLK_SEL_2_5M; 275 break; 276 case 100: 277 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 278 (RK3228_GMAC_RMII_CLK_25M | RK3228_GMAC_RMII_SPEED_100) : 279 RK3228_GMAC_CLK_SEL_25M; 280 break; 281 case 1000: 282 clk = RK3228_GMAC_CLK_SEL_125M; 283 break; 284 default: 285 debug("Unknown phy speed: %d\n", priv->phydev->speed); 286 return -EINVAL; 287 } 288 289 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 290 rk_clrsetreg(&grf->mac_con[1], 291 RK3228_GMAC_CLK_SEL_MASK | 292 RK3228_GMAC_RMII_CLK_MASK | 293 RK3228_GMAC_RMII_SPEED_MASK, 294 clk); 295 296 return 0; 297 } 298 299 static int rk3288_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 300 struct rockchip_eth_dev *dev) 301 { 302 struct dw_eth_dev *priv = &dev->dw; 303 struct rk3288_grf *grf; 304 int clk; 305 306 switch (priv->phydev->speed) { 307 case 10: 308 clk = RK3288_GMAC_CLK_SEL_2_5M; 309 break; 310 case 100: 311 clk = RK3288_GMAC_CLK_SEL_25M; 312 break; 313 case 1000: 314 clk = RK3288_GMAC_CLK_SEL_125M; 315 break; 316 default: 317 debug("Unknown phy speed: %d\n", priv->phydev->speed); 318 return -EINVAL; 319 } 320 321 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 322 rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk); 323 324 return 0; 325 } 326 327 static int rk3308_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 328 struct rockchip_eth_dev *dev) 329 { 330 struct dw_eth_dev *priv = &dev->dw; 331 struct rk3308_grf *grf; 332 struct clk clk_speed; 333 int speed, ret; 334 enum { 335 RK3308_GMAC_SPEED_SHIFT = 0x0, 336 RK3308_GMAC_SPEED_MASK = BIT(0), 337 RK3308_GMAC_SPEED_10M = 0, 338 RK3308_GMAC_SPEED_100M = BIT(0), 339 }; 340 341 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 342 &clk_speed); 343 if (ret) 344 return ret; 345 346 switch (priv->phydev->speed) { 347 case 10: 348 speed = RK3308_GMAC_SPEED_10M; 349 ret = clk_set_rate(&clk_speed, 2500000); 350 if (ret) 351 return ret; 352 break; 353 case 100: 354 speed = RK3308_GMAC_SPEED_100M; 355 ret = clk_set_rate(&clk_speed, 25000000); 356 if (ret) 357 return ret; 358 break; 359 default: 360 debug("Unknown phy speed: %d\n", priv->phydev->speed); 361 return -EINVAL; 362 } 363 364 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 365 rk_clrsetreg(&grf->mac_con0, RK3308_GMAC_SPEED_MASK, speed); 366 367 return 0; 368 } 369 370 static int rk3328_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 371 struct rockchip_eth_dev *dev) 372 { 373 struct dw_eth_dev *priv = &dev->dw; 374 struct rk3328_grf_regs *grf; 375 int clk; 376 enum { 377 RK3328_GMAC_CLK_SEL_SHIFT = 11, 378 RK3328_GMAC_CLK_SEL_MASK = GENMASK(12, 11), 379 RK3328_GMAC_CLK_SEL_125M = 0 << 11, 380 RK3328_GMAC_CLK_SEL_25M = 3 << 11, 381 RK3328_GMAC_CLK_SEL_2_5M = 2 << 11, 382 383 RK3328_GMAC_RMII_CLK_MASK = BIT(7), 384 RK3328_GMAC_RMII_CLK_2_5M = 0, 385 RK3328_GMAC_RMII_CLK_25M = BIT(7), 386 387 RK3328_GMAC_RMII_SPEED_MASK = BIT(2), 388 RK3328_GMAC_RMII_SPEED_10 = 0, 389 RK3328_GMAC_RMII_SPEED_100 = BIT(2), 390 }; 391 392 switch (priv->phydev->speed) { 393 case 10: 394 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 395 (RK3328_GMAC_RMII_CLK_2_5M | RK3328_GMAC_RMII_SPEED_10) : 396 RK3328_GMAC_CLK_SEL_2_5M; 397 break; 398 case 100: 399 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 400 (RK3328_GMAC_RMII_CLK_25M | RK3328_GMAC_RMII_SPEED_100) : 401 RK3328_GMAC_CLK_SEL_25M; 402 break; 403 case 1000: 404 clk = RK3328_GMAC_CLK_SEL_125M; 405 break; 406 default: 407 debug("Unknown phy speed: %d\n", priv->phydev->speed); 408 return -EINVAL; 409 } 410 411 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 412 rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1], 413 RK3328_GMAC_CLK_SEL_MASK | 414 RK3328_GMAC_RMII_CLK_MASK | 415 RK3328_GMAC_RMII_SPEED_MASK, 416 clk); 417 418 return 0; 419 } 420 421 static int rk3368_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 422 struct rockchip_eth_dev *dev) 423 { 424 struct dw_eth_dev *priv = &dev->dw; 425 struct rk3368_grf *grf; 426 int clk; 427 enum { 428 RK3368_GMAC_CLK_SEL_2_5M = 2 << 4, 429 RK3368_GMAC_CLK_SEL_25M = 3 << 4, 430 RK3368_GMAC_CLK_SEL_125M = 0 << 4, 431 RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4), 432 }; 433 434 switch (priv->phydev->speed) { 435 case 10: 436 clk = RK3368_GMAC_CLK_SEL_2_5M; 437 break; 438 case 100: 439 clk = RK3368_GMAC_CLK_SEL_25M; 440 break; 441 case 1000: 442 clk = RK3368_GMAC_CLK_SEL_125M; 443 break; 444 default: 445 debug("Unknown phy speed: %d\n", priv->phydev->speed); 446 return -EINVAL; 447 } 448 449 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 450 rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk); 451 452 return 0; 453 } 454 455 static int rk3399_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 456 struct rockchip_eth_dev *dev) 457 { 458 struct dw_eth_dev *priv = &dev->dw; 459 struct rk3399_grf_regs *grf; 460 int clk; 461 462 switch (priv->phydev->speed) { 463 case 10: 464 clk = RK3399_GMAC_CLK_SEL_2_5M; 465 break; 466 case 100: 467 clk = RK3399_GMAC_CLK_SEL_25M; 468 break; 469 case 1000: 470 clk = RK3399_GMAC_CLK_SEL_125M; 471 break; 472 default: 473 debug("Unknown phy speed: %d\n", priv->phydev->speed); 474 return -EINVAL; 475 } 476 477 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 478 rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk); 479 480 return 0; 481 } 482 483 static int rv1108_set_rmii_speed(struct gmac_rockchip_platdata *pdata, 484 struct rockchip_eth_dev *dev) 485 { 486 struct dw_eth_dev *priv = &dev->dw; 487 struct rv1108_grf *grf; 488 int clk, speed; 489 enum { 490 RV1108_GMAC_SPEED_MASK = BIT(2), 491 RV1108_GMAC_SPEED_10M = 0 << 2, 492 RV1108_GMAC_SPEED_100M = 1 << 2, 493 RV1108_GMAC_CLK_SEL_MASK = BIT(7), 494 RV1108_GMAC_CLK_SEL_2_5M = 0 << 7, 495 RV1108_GMAC_CLK_SEL_25M = 1 << 7, 496 }; 497 498 switch (priv->phydev->speed) { 499 case 10: 500 clk = RV1108_GMAC_CLK_SEL_2_5M; 501 speed = RV1108_GMAC_SPEED_10M; 502 break; 503 case 100: 504 clk = RV1108_GMAC_CLK_SEL_25M; 505 speed = RV1108_GMAC_SPEED_100M; 506 break; 507 default: 508 debug("Unknown phy speed: %d\n", priv->phydev->speed); 509 return -EINVAL; 510 } 511 512 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 513 rk_clrsetreg(&grf->gmac_con0, 514 RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK, 515 clk | speed); 516 517 return 0; 518 } 519 #else 520 static int rk3528_set_rgmii_speed(struct gmac_rockchip_platdata *pdata, 521 struct rockchip_eth_dev *dev) 522 { 523 struct eqos_priv *priv = &dev->eqos; 524 struct rk3528_grf *grf; 525 unsigned int div; 526 527 enum { 528 RK3528_GMAC0_CLK_RMII_DIV_SHIFT = 3, 529 RK3528_GMAC0_CLK_RMII_DIV_MASK = GENMASK(4, 3), 530 RK3528_GMAC0_CLK_RMII_DIV2 = BIT(3), 531 RK3528_GMAC0_CLK_RMII_DIV20 = 0, 532 }; 533 534 enum { 535 RK3528_GMAC1_CLK_RGMII_DIV_SHIFT = 10, 536 RK3528_GMAC1_CLK_RGMII_DIV_MASK = GENMASK(11, 10), 537 RK3528_GMAC1_CLK_RGMII_DIV1 = 0, 538 RK3528_GMAC1_CLK_RGMII_DIV5 = GENMASK(11, 10), 539 RK3528_GMAC1_CLK_RGMII_DIV50 = BIT(11), 540 RK3528_GMAC1_CLK_RMII_DIV2 = BIT(11), 541 RK3528_GMAC1_CLK_RMII_DIV20 = 0, 542 }; 543 544 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 545 546 switch (priv->phy->speed) { 547 case 10: 548 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) 549 div = pdata->bus_id ? RK3528_GMAC1_CLK_RMII_DIV20 : 550 RK3528_GMAC0_CLK_RMII_DIV20; 551 else 552 div = RK3528_GMAC1_CLK_RGMII_DIV50; 553 break; 554 case 100: 555 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) 556 div = pdata->bus_id ? RK3528_GMAC1_CLK_RMII_DIV2 : 557 RK3528_GMAC0_CLK_RMII_DIV2; 558 else 559 div = RK3528_GMAC1_CLK_RGMII_DIV5; 560 break; 561 case 1000: 562 if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII) 563 div = RK3528_GMAC1_CLK_RGMII_DIV1; 564 else 565 return -EINVAL; 566 break; 567 default: 568 debug("Unknown phy speed: %d\n", priv->phy->speed); 569 return -EINVAL; 570 } 571 572 if (pdata->bus_id) 573 rk_clrsetreg(&grf->gmac1_con0, RK3528_GMAC1_CLK_RGMII_DIV_MASK, div); 574 else 575 rk_clrsetreg(&grf->gmac0_con, RK3528_GMAC0_CLK_RMII_DIV_MASK, div); 576 577 return 0; 578 } 579 580 static int rk3588_set_rgmii_speed(struct gmac_rockchip_platdata *pdata, 581 struct rockchip_eth_dev *dev) 582 { 583 struct eqos_priv *priv = &dev->eqos; 584 struct rk3588_php_grf *php_grf; 585 unsigned int div, div_mask; 586 587 enum { 588 RK3588_GMAC_CLK_RGMII_DIV_SHIFT = 2, 589 RK3588_GMAC_CLK_RGMII_DIV_MASK = GENMASK(3, 2), 590 RK3588_GMAC_CLK_RGMII_DIV1 = 0, 591 RK3588_GMAC_CLK_RGMII_DIV5 = GENMASK(3, 2), 592 RK3588_GMAC_CLK_RGMII_DIV50 = BIT(3), 593 RK3588_GMAC_CLK_RMII_DIV2 = BIT(2), 594 RK3588_GMAC_CLK_RMII_DIV20 = 0, 595 RK3588_GMAC1_ID_SHIFT = 5, 596 }; 597 598 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 599 600 switch (priv->phy->speed) { 601 case 10: 602 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) 603 div = RK3588_GMAC_CLK_RMII_DIV20; 604 else 605 div = RK3588_GMAC_CLK_RGMII_DIV50; 606 break; 607 case 100: 608 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) 609 div = RK3588_GMAC_CLK_RMII_DIV2; 610 else 611 div = RK3588_GMAC_CLK_RGMII_DIV5; 612 break; 613 case 1000: 614 if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII) 615 div = RK3588_GMAC_CLK_RGMII_DIV1; 616 else 617 return -EINVAL; 618 break; 619 default: 620 debug("Unknown phy speed: %d\n", priv->phy->speed); 621 return -EINVAL; 622 } 623 624 if (pdata->bus_id == 1) { 625 div <<= 5; 626 div_mask = RK3588_GMAC_CLK_RGMII_DIV_MASK << 5; 627 } 628 629 div <<= pdata->bus_id ? RK3588_GMAC1_ID_SHIFT : 0; 630 div_mask = pdata->bus_id ? (RK3588_GMAC_CLK_RGMII_DIV_MASK << 5) : 631 RK3588_GMAC_CLK_RGMII_DIV_MASK; 632 633 rk_clrsetreg(&php_grf->clk_con1, div_mask, div); 634 635 return 0; 636 } 637 638 static int rv1106_set_rmii_speed(struct gmac_rockchip_platdata *pdata, 639 struct rockchip_eth_dev *dev) 640 { 641 struct eqos_priv *priv = &dev->eqos; 642 struct rv1106_grf *grf; 643 unsigned int div; 644 645 enum { 646 RV1106_GMAC_CLK_RMII_DIV_SHIFT = 2, 647 RV1106_GMAC_CLK_RMII_DIV_MASK = GENMASK(3, 2), 648 RV1106_GMAC_CLK_RMII_DIV2 = BIT(2), 649 RV1106_GMAC_CLK_RMII_DIV20 = 0, 650 }; 651 652 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 653 654 switch (priv->phy->speed) { 655 case 10: 656 div = RV1106_GMAC_CLK_RMII_DIV20; 657 break; 658 case 100: 659 div = RV1106_GMAC_CLK_RMII_DIV2; 660 break; 661 default: 662 debug("Unknown phy speed: %d\n", priv->phy->speed); 663 return -EINVAL; 664 } 665 666 rk_clrsetreg(&grf->gmac_clk_con, RV1106_GMAC_CLK_RMII_DIV_MASK, div); 667 668 return 0; 669 } 670 671 static int rv1126_set_rgmii_speed(struct gmac_rockchip_platdata *pdata, 672 struct rockchip_eth_dev *dev) 673 { 674 struct eqos_priv *priv = &dev->eqos; 675 struct clk clk_speed; 676 int ret; 677 678 ret = clk_get_by_name(priv->phy->dev, "clk_mac_speed", 679 &clk_speed); 680 if (ret) { 681 printf("%s can't get clk_mac_speed clock (ret=%d):\n", 682 __func__, ret); 683 return ret; 684 } 685 686 switch ( priv->phy->speed) { 687 case 10: 688 ret = clk_set_rate(&clk_speed, 2500000); 689 if (ret) 690 return ret; 691 break; 692 case 100: 693 ret = clk_set_rate(&clk_speed, 25000000); 694 if (ret) 695 return ret; 696 break; 697 case 1000: 698 ret = clk_set_rate(&clk_speed, 125000000); 699 if (ret) 700 return ret; 701 break; 702 default: 703 debug("Unknown phy speed: %d\n", priv->phy->speed); 704 return -EINVAL; 705 } 706 707 return 0; 708 } 709 #endif 710 711 #ifndef CONFIG_DWC_ETH_QOS 712 static void px30_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 713 { 714 struct px30_grf *grf; 715 enum { 716 px30_GMAC_PHY_INTF_SEL_SHIFT = 4, 717 px30_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 6), 718 px30_GMAC_PHY_INTF_SEL_RMII = BIT(6), 719 }; 720 721 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 722 723 rk_clrsetreg(&grf->mac_con1, 724 px30_GMAC_PHY_INTF_SEL_MASK, 725 px30_GMAC_PHY_INTF_SEL_RMII); 726 } 727 728 static void rk1808_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 729 { 730 struct rk1808_grf *grf; 731 enum { 732 RK1808_GMAC_PHY_INTF_SEL_SHIFT = 4, 733 RK1808_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 734 RK1808_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 735 736 RK1808_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 737 RK1808_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 738 RK1808_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 739 740 RK1808_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 741 RK1808_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 742 RK1808_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 743 }; 744 enum { 745 RK1808_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 746 RK1808_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 7), 747 748 RK1808_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 749 RK1808_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 750 }; 751 752 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 753 rk_clrsetreg(&grf->mac_con1, 754 RK1808_GMAC_PHY_INTF_SEL_MASK | 755 RK1808_RXCLK_DLY_ENA_GMAC_MASK | 756 RK1808_TXCLK_DLY_ENA_GMAC_MASK, 757 RK1808_GMAC_PHY_INTF_SEL_RGMII | 758 RK1808_RXCLK_DLY_ENA_GMAC_ENABLE | 759 RK1808_TXCLK_DLY_ENA_GMAC_ENABLE); 760 761 rk_clrsetreg(&grf->mac_con0, 762 RK1808_CLK_RX_DL_CFG_GMAC_MASK | 763 RK1808_CLK_TX_DL_CFG_GMAC_MASK, 764 (pdata->rx_delay << RK1808_CLK_RX_DL_CFG_GMAC_SHIFT) | 765 (pdata->tx_delay << RK1808_CLK_TX_DL_CFG_GMAC_SHIFT)); 766 } 767 768 static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 769 { 770 struct rk322x_grf *grf; 771 enum { 772 RK3228_RMII_MODE_SHIFT = 10, 773 RK3228_RMII_MODE_MASK = BIT(10), 774 775 RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4, 776 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 777 RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 778 779 RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 780 RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 781 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 782 783 RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 784 RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 785 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 786 }; 787 enum { 788 RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 789 RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 790 791 RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 792 RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 793 }; 794 795 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 796 rk_clrsetreg(&grf->mac_con[1], 797 RK3228_RMII_MODE_MASK | 798 RK3228_GMAC_PHY_INTF_SEL_MASK | 799 RK3228_RXCLK_DLY_ENA_GMAC_MASK | 800 RK3228_TXCLK_DLY_ENA_GMAC_MASK, 801 RK3228_GMAC_PHY_INTF_SEL_RGMII | 802 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE | 803 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE); 804 805 rk_clrsetreg(&grf->mac_con[0], 806 RK3228_CLK_RX_DL_CFG_GMAC_MASK | 807 RK3228_CLK_TX_DL_CFG_GMAC_MASK, 808 pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT | 809 pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT); 810 } 811 812 static void rk3228_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 813 { 814 struct rk322x_grf *grf; 815 enum { 816 RK3228_GRF_CON_RMII_MODE_MASK = BIT(11), 817 RK3228_GRF_CON_RMII_MODE_SEL = BIT(11), 818 RK3228_RMII_MODE_MASK = BIT(10), 819 RK3228_RMII_MODE_SEL = BIT(10), 820 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 821 RK3228_GMAC_PHY_INTF_SEL_RMII = BIT(6), 822 }; 823 824 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 825 rk_clrsetreg(&grf->mac_con[1], 826 RK3228_GRF_CON_RMII_MODE_MASK | 827 RK3228_RMII_MODE_MASK | 828 RK3228_GMAC_PHY_INTF_SEL_MASK, 829 RK3228_GRF_CON_RMII_MODE_SEL | 830 RK3228_RMII_MODE_SEL | 831 RK3228_GMAC_PHY_INTF_SEL_RMII); 832 } 833 834 static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 835 { 836 struct rk3288_grf *grf; 837 838 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 839 rk_clrsetreg(&grf->soc_con1, 840 RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK, 841 RK3288_GMAC_PHY_INTF_SEL_RGMII); 842 843 rk_clrsetreg(&grf->soc_con3, 844 RK3288_RXCLK_DLY_ENA_GMAC_MASK | 845 RK3288_TXCLK_DLY_ENA_GMAC_MASK | 846 RK3288_CLK_RX_DL_CFG_GMAC_MASK | 847 RK3288_CLK_TX_DL_CFG_GMAC_MASK, 848 RK3288_RXCLK_DLY_ENA_GMAC_ENABLE | 849 RK3288_TXCLK_DLY_ENA_GMAC_ENABLE | 850 pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT | 851 pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT); 852 } 853 854 static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 855 { 856 struct rk3308_grf *grf; 857 enum { 858 RK3308_GMAC_PHY_INTF_SEL_SHIFT = 2, 859 RK3308_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 2), 860 RK3308_GMAC_PHY_INTF_SEL_RMII = BIT(4), 861 }; 862 863 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 864 865 rk_clrsetreg(&grf->mac_con0, 866 RK3308_GMAC_PHY_INTF_SEL_MASK, 867 RK3308_GMAC_PHY_INTF_SEL_RMII); 868 } 869 870 static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 871 { 872 struct rk3328_grf_regs *grf; 873 enum { 874 RK3328_RMII_MODE_SHIFT = 9, 875 RK3328_RMII_MODE_MASK = BIT(9), 876 877 RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4, 878 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 879 RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 880 881 RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 882 RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 883 RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 884 885 RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 886 RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 887 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 888 }; 889 enum { 890 RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 891 RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 892 893 RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 894 RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 895 }; 896 897 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 898 rk_clrsetreg(&grf->mac_con[1], 899 RK3328_RMII_MODE_MASK | 900 RK3328_GMAC_PHY_INTF_SEL_MASK | 901 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 902 RK3328_TXCLK_DLY_ENA_GMAC_MASK, 903 RK3328_GMAC_PHY_INTF_SEL_RGMII | 904 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 905 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE); 906 907 rk_clrsetreg(&grf->mac_con[0], 908 RK3328_CLK_RX_DL_CFG_GMAC_MASK | 909 RK3328_CLK_TX_DL_CFG_GMAC_MASK, 910 pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT | 911 pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT); 912 } 913 914 static void rk3328_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 915 { 916 struct rk3328_grf_regs *grf; 917 enum { 918 RK3328_RMII_MODE_MASK = BIT(9), 919 RK3328_RMII_MODE = BIT(9), 920 921 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 922 RK3328_GMAC_PHY_INTF_SEL_RMII = BIT(6), 923 }; 924 925 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 926 rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1], 927 RK3328_RMII_MODE_MASK | 928 RK3328_GMAC_PHY_INTF_SEL_MASK, 929 RK3328_GMAC_PHY_INTF_SEL_RMII | 930 RK3328_RMII_MODE); 931 } 932 933 static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 934 { 935 struct rk3368_grf *grf; 936 enum { 937 RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9, 938 RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9), 939 RK3368_RMII_MODE_MASK = BIT(6), 940 RK3368_RMII_MODE = BIT(6), 941 }; 942 enum { 943 RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15), 944 RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 945 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15), 946 RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7), 947 RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 948 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7), 949 RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8, 950 RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 951 RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0, 952 RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 953 }; 954 955 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 956 rk_clrsetreg(&grf->soc_con15, 957 RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK, 958 RK3368_GMAC_PHY_INTF_SEL_RGMII); 959 960 rk_clrsetreg(&grf->soc_con16, 961 RK3368_RXCLK_DLY_ENA_GMAC_MASK | 962 RK3368_TXCLK_DLY_ENA_GMAC_MASK | 963 RK3368_CLK_RX_DL_CFG_GMAC_MASK | 964 RK3368_CLK_TX_DL_CFG_GMAC_MASK, 965 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE | 966 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE | 967 (pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT) | 968 (pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT)); 969 } 970 971 static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 972 { 973 struct rk3399_grf_regs *grf; 974 975 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 976 977 rk_clrsetreg(&grf->soc_con5, 978 RK3399_GMAC_PHY_INTF_SEL_MASK, 979 RK3399_GMAC_PHY_INTF_SEL_RGMII); 980 981 rk_clrsetreg(&grf->soc_con6, 982 RK3399_RXCLK_DLY_ENA_GMAC_MASK | 983 RK3399_TXCLK_DLY_ENA_GMAC_MASK | 984 RK3399_CLK_RX_DL_CFG_GMAC_MASK | 985 RK3399_CLK_TX_DL_CFG_GMAC_MASK, 986 RK3399_RXCLK_DLY_ENA_GMAC_ENABLE | 987 RK3399_TXCLK_DLY_ENA_GMAC_ENABLE | 988 (pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT) | 989 (pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT)); 990 } 991 992 static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 993 { 994 struct rv1108_grf *grf; 995 996 enum { 997 RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 998 RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4, 999 }; 1000 1001 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1002 rk_clrsetreg(&grf->gmac_con0, 1003 RV1108_GMAC_PHY_INTF_SEL_MASK, 1004 RV1108_GMAC_PHY_INTF_SEL_RMII); 1005 } 1006 1007 static void rk3228_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 1008 { 1009 struct rk322x_grf *grf; 1010 enum { 1011 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK = BIT(15), 1012 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY = BIT(15), 1013 }; 1014 enum { 1015 RK3228_MACPHY_CFG_CLK_50M_MASK = BIT(14), 1016 RK3228_MACPHY_CFG_CLK_50M = BIT(14), 1017 1018 RK3228_MACPHY_RMII_MODE_MASK = GENMASK(7, 6), 1019 RK3228_MACPHY_RMII_MODE = BIT(6), 1020 1021 RK3228_MACPHY_ENABLE_MASK = BIT(0), 1022 RK3228_MACPHY_DISENABLE = 0, 1023 RK3228_MACPHY_ENABLE = BIT(0), 1024 }; 1025 enum { 1026 RK3228_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0), 1027 RK3228_RK_GRF_CON2_MACPHY_ID = 0x1234, 1028 }; 1029 enum { 1030 RK3228_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0), 1031 RK3228_RK_GRF_CON3_MACPHY_ID = 0x35, 1032 }; 1033 1034 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1035 rk_clrsetreg(&grf->con_iomux, 1036 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK, 1037 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY); 1038 1039 rk_clrsetreg(&grf->macphy_con[2], 1040 RK3228_RK_GRF_CON2_MACPHY_ID_MASK, 1041 RK3228_RK_GRF_CON2_MACPHY_ID); 1042 1043 rk_clrsetreg(&grf->macphy_con[3], 1044 RK3228_RK_GRF_CON3_MACPHY_ID_MASK, 1045 RK3228_RK_GRF_CON3_MACPHY_ID); 1046 1047 /* disabled before trying to reset it &*/ 1048 rk_clrsetreg(&grf->macphy_con[0], 1049 RK3228_MACPHY_CFG_CLK_50M_MASK | 1050 RK3228_MACPHY_RMII_MODE_MASK | 1051 RK3228_MACPHY_ENABLE_MASK, 1052 RK3228_MACPHY_CFG_CLK_50M | 1053 RK3228_MACPHY_RMII_MODE | 1054 RK3228_MACPHY_DISENABLE); 1055 1056 reset_assert(&pdata->phy_reset); 1057 udelay(10); 1058 reset_deassert(&pdata->phy_reset); 1059 udelay(10); 1060 1061 rk_clrsetreg(&grf->macphy_con[0], 1062 RK3228_MACPHY_ENABLE_MASK, 1063 RK3228_MACPHY_ENABLE); 1064 udelay(30 * 1000); 1065 } 1066 1067 static void rk3328_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 1068 { 1069 struct rk3328_grf_regs *grf; 1070 enum { 1071 RK3328_GRF_CON_RMII_MODE_MASK = BIT(9), 1072 RK3328_GRF_CON_RMII_MODE = BIT(9), 1073 }; 1074 enum { 1075 RK3328_MACPHY_CFG_CLK_50M_MASK = BIT(14), 1076 RK3328_MACPHY_CFG_CLK_50M = BIT(14), 1077 1078 RK3328_MACPHY_RMII_MODE_MASK = GENMASK(7, 6), 1079 RK3328_MACPHY_RMII_MODE = BIT(6), 1080 1081 RK3328_MACPHY_ENABLE_MASK = BIT(0), 1082 RK3328_MACPHY_DISENABLE = 0, 1083 RK3328_MACPHY_ENABLE = BIT(0), 1084 }; 1085 enum { 1086 RK3328_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0), 1087 RK3328_RK_GRF_CON2_MACPHY_ID = 0x1234, 1088 }; 1089 enum { 1090 RK3328_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0), 1091 RK3328_RK_GRF_CON3_MACPHY_ID = 0x35, 1092 }; 1093 1094 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1095 rk_clrsetreg(&grf->macphy_con[1], 1096 RK3328_GRF_CON_RMII_MODE_MASK, 1097 RK3328_GRF_CON_RMII_MODE); 1098 1099 rk_clrsetreg(&grf->macphy_con[2], 1100 RK3328_RK_GRF_CON2_MACPHY_ID_MASK, 1101 RK3328_RK_GRF_CON2_MACPHY_ID); 1102 1103 rk_clrsetreg(&grf->macphy_con[3], 1104 RK3328_RK_GRF_CON3_MACPHY_ID_MASK, 1105 RK3328_RK_GRF_CON3_MACPHY_ID); 1106 1107 /* disabled before trying to reset it &*/ 1108 rk_clrsetreg(&grf->macphy_con[0], 1109 RK3328_MACPHY_CFG_CLK_50M_MASK | 1110 RK3328_MACPHY_RMII_MODE_MASK | 1111 RK3328_MACPHY_ENABLE_MASK, 1112 RK3328_MACPHY_CFG_CLK_50M | 1113 RK3328_MACPHY_RMII_MODE | 1114 RK3328_MACPHY_DISENABLE); 1115 1116 reset_assert(&pdata->phy_reset); 1117 udelay(10); 1118 reset_deassert(&pdata->phy_reset); 1119 udelay(10); 1120 1121 rk_clrsetreg(&grf->macphy_con[0], 1122 RK3328_MACPHY_ENABLE_MASK, 1123 RK3328_MACPHY_ENABLE); 1124 udelay(30 * 1000); 1125 } 1126 1127 #else 1128 static void rk3528_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 1129 { 1130 struct rk3528_grf *grf; 1131 unsigned char bgs[1] = {0}; 1132 1133 enum { 1134 RK3528_MACPHY_ENABLE_MASK = BIT(1), 1135 RK3528_MACPHY_DISENABLE = BIT(1), 1136 RK3528_MACPHY_ENABLE = 0, 1137 RK3528_MACPHY_XMII_SEL_MASK = GENMASK(6, 5), 1138 RK3528_MACPHY_XMII_SEL = BIT(6), 1139 RK3528_MACPHY_24M_CLK_SEL_MASK = GENMASK(9, 7), 1140 RK3528_MACPHY_24M_CLK_SEL_24M = (BIT(8) | BIT(9)), 1141 RK3528_MACPHY_PHY_ID_MASK = GENMASK(14, 10), 1142 RK3528_MACPHY_PHY_ID = BIT(11), 1143 }; 1144 1145 enum { 1146 RK3528_MACPHY_BGS_MASK = GENMASK(3, 0), 1147 }; 1148 1149 #if defined(CONFIG_ROCKCHIP_EFUSE) || defined(CONFIG_ROCKCHIP_OTP) 1150 struct udevice *dev; 1151 u32 regs[2] = {0}; 1152 ofnode node; 1153 int ret = 0; 1154 1155 /* retrieve the device */ 1156 if (IS_ENABLED(CONFIG_ROCKCHIP_EFUSE)) 1157 ret = uclass_get_device_by_driver(UCLASS_MISC, 1158 DM_GET_DRIVER(rockchip_efuse), 1159 &dev); 1160 else 1161 ret = uclass_get_device_by_driver(UCLASS_MISC, 1162 DM_GET_DRIVER(rockchip_otp), 1163 &dev); 1164 if (!ret) { 1165 node = dev_read_subnode(dev, "macphy-bgs"); 1166 if (ofnode_valid(node)) { 1167 if (!ofnode_read_u32_array(node, "reg", regs, 2)) { 1168 /* read the bgs from the efuses */ 1169 ret = misc_read(dev, regs[0], &bgs, 1); 1170 if (ret) { 1171 printf("read bgs from efuse/otp failed, ret=%d\n", 1172 ret); 1173 bgs[0] = 0; 1174 } 1175 } 1176 } 1177 } 1178 #endif 1179 1180 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1181 1182 reset_assert(&pdata->phy_reset); 1183 udelay(20); 1184 rk_clrsetreg(&grf->macphy_con0, 1185 RK3528_MACPHY_ENABLE_MASK | 1186 RK3528_MACPHY_XMII_SEL_MASK | 1187 RK3528_MACPHY_24M_CLK_SEL_MASK | 1188 RK3528_MACPHY_PHY_ID_MASK, 1189 RK3528_MACPHY_ENABLE | 1190 RK3528_MACPHY_XMII_SEL | 1191 RK3528_MACPHY_24M_CLK_SEL_24M | 1192 RK3528_MACPHY_PHY_ID); 1193 1194 rk_clrsetreg(&grf->macphy_con1, 1195 RK3528_MACPHY_BGS_MASK, 1196 bgs[0]); 1197 udelay(20); 1198 reset_deassert(&pdata->phy_reset); 1199 udelay(30 * 1000); 1200 } 1201 1202 static void rk3528_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1203 { 1204 unsigned int clk_mode; 1205 struct rk3528_grf *grf; 1206 1207 enum { 1208 RK3528_GMAC0_CLK_RMII_MODE_SHIFT = 0x1, 1209 RK3528_GMAC0_CLK_RMII_MODE_MASK = BIT(1), 1210 RK3528_GMAC0_CLK_RMII_MODE = 0x1, 1211 }; 1212 1213 enum { 1214 RK3528_GMAC1_CLK_RMII_MODE_SHIFT = 0x8, 1215 RK3528_GMAC1_CLK_RMII_MODE_MASK = BIT(8), 1216 RK3528_GMAC1_CLK_RMII_MODE = 0x1, 1217 }; 1218 1219 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1220 1221 if (pdata->bus_id == 1) { 1222 clk_mode = RK3528_GMAC1_CLK_RMII_MODE << RK3528_GMAC1_CLK_RMII_MODE_SHIFT; 1223 rk_clrsetreg(&grf->gmac1_con1, RK3528_GMAC1_CLK_RMII_MODE_MASK, clk_mode); 1224 } else { 1225 clk_mode = RK3528_GMAC0_CLK_RMII_MODE << RK3528_GMAC0_CLK_RMII_MODE_SHIFT; 1226 rk_clrsetreg(&grf->gmac0_con, RK3528_GMAC0_CLK_RMII_MODE_MASK, clk_mode); 1227 } 1228 } 1229 1230 static void rk3528_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1231 { 1232 unsigned int rx_enable; 1233 unsigned int rx_delay; 1234 struct rk3528_grf *grf; 1235 1236 enum { 1237 RK3528_GMAC1_RGMII_MODE_SHIFT = 0x8, 1238 RK3528_GMAC1_RGMII_MODE_MASK = BIT(8), 1239 RK3528_GMAC1_RGMII_MODE = 0x0, 1240 1241 RK3528_GMAC1_TXCLK_DLY_ENA_MASK = BIT(14), 1242 RK3528_GMAC1_TXCLK_DLY_ENA_DISABLE = 0, 1243 RK3528_GMAC1_TXCLK_DLY_ENA_ENABLE = BIT(14), 1244 1245 RK3528_GMAC1_RXCLK_DLY_ENA_MASK = BIT(15), 1246 RK3528_GMAC1_RXCLK_DLY_ENA_DISABLE = 0, 1247 RK3528_GMAC1_RXCLK_DLY_ENA_ENABLE = BIT(15), 1248 }; 1249 1250 enum { 1251 RK3528_GMAC1_RX_DL_CFG_SHIFT = 0x8, 1252 RK3528_GMAC1_RX_DL_CFG_MASK = GENMASK(15, 8), 1253 1254 RK3528_GMAC1_TX_DL_CFG_SHIFT = 0x0, 1255 RK3528_GMAC1_TX_DL_CFG_MASK = GENMASK(7, 0), 1256 }; 1257 1258 if (!pdata->bus_id) 1259 return; 1260 1261 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1262 1263 if (pdata->rx_delay < 0) { 1264 rx_enable = RK3528_GMAC1_RXCLK_DLY_ENA_DISABLE; 1265 rx_delay = 0; 1266 } else { 1267 rx_enable = RK3528_GMAC1_RXCLK_DLY_ENA_ENABLE; 1268 rx_delay = pdata->rx_delay << RK3528_GMAC1_RX_DL_CFG_SHIFT; 1269 } 1270 1271 rk_clrsetreg(&grf->gmac1_con0, 1272 RK3528_GMAC1_TXCLK_DLY_ENA_MASK | 1273 RK3528_GMAC1_RXCLK_DLY_ENA_MASK | 1274 RK3528_GMAC1_RGMII_MODE_MASK, 1275 rx_enable | RK3528_GMAC1_TXCLK_DLY_ENA_ENABLE | 1276 (RK3528_GMAC1_RGMII_MODE << RK3528_GMAC1_RGMII_MODE_SHIFT)); 1277 1278 rk_clrsetreg(&grf->gmac1_con1, 1279 RK3528_GMAC1_RX_DL_CFG_MASK | 1280 RK3528_GMAC1_TX_DL_CFG_MASK, 1281 (pdata->tx_delay << RK3528_GMAC1_TX_DL_CFG_SHIFT) | 1282 rx_delay); 1283 } 1284 1285 static void rk3568_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1286 { 1287 struct rk3568_grf *grf; 1288 void *con1; 1289 1290 enum { 1291 RK3568_GMAC_PHY_INTF_SEL_SHIFT = 4, 1292 RK3568_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1293 RK3568_GMAC_PHY_INTF_SEL_RMII = BIT(6), 1294 }; 1295 1296 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1297 1298 if (pdata->bus_id == 1) 1299 con1 = &grf->mac1_con1; 1300 else 1301 con1 = &grf->mac0_con1; 1302 1303 rk_clrsetreg(con1, 1304 RK3568_GMAC_PHY_INTF_SEL_MASK, 1305 RK3568_GMAC_PHY_INTF_SEL_RMII); 1306 } 1307 1308 static void rk3568_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1309 { 1310 struct rk3568_grf *grf; 1311 void *con0, *con1; 1312 1313 enum { 1314 RK3568_GMAC_PHY_INTF_SEL_SHIFT = 4, 1315 RK3568_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1316 RK3568_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 1317 1318 RK3568_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 1319 RK3568_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 1320 RK3568_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 1321 1322 RK3568_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 1323 RK3568_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 1324 RK3568_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 1325 }; 1326 1327 enum { 1328 RK3568_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1329 RK3568_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 8), 1330 1331 RK3568_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1332 RK3568_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 1333 }; 1334 1335 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1336 1337 if (pdata->bus_id == 1) { 1338 con0 = &grf->mac1_con0; 1339 con1 = &grf->mac1_con1; 1340 } else { 1341 con0 = &grf->mac0_con0; 1342 con1 = &grf->mac0_con1; 1343 } 1344 1345 rk_clrsetreg(con0, 1346 RK3568_CLK_RX_DL_CFG_GMAC_MASK | 1347 RK3568_CLK_TX_DL_CFG_GMAC_MASK, 1348 (pdata->rx_delay << RK3568_CLK_RX_DL_CFG_GMAC_SHIFT) | 1349 (pdata->tx_delay << RK3568_CLK_TX_DL_CFG_GMAC_SHIFT)); 1350 1351 rk_clrsetreg(con1, 1352 RK3568_TXCLK_DLY_ENA_GMAC_MASK | 1353 RK3568_RXCLK_DLY_ENA_GMAC_MASK | 1354 RK3568_GMAC_PHY_INTF_SEL_MASK, 1355 RK3568_TXCLK_DLY_ENA_GMAC_ENABLE | 1356 RK3568_RXCLK_DLY_ENA_GMAC_ENABLE | 1357 RK3568_GMAC_PHY_INTF_SEL_RGMII); 1358 } 1359 1360 static void rk3588_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1361 { 1362 unsigned int intf_sel, intf_sel_mask; 1363 unsigned int clk_mode, clk_mode_mask; 1364 struct rk3588_php_grf *php_grf; 1365 1366 enum { 1367 RK3588_GMAC_PHY_INTF_SEL_SHIFT = 3, 1368 RK3588_GMAC_PHY_INTF_SEL_MASK = GENMASK(5, 3), 1369 RK3588_GMAC_PHY_INTF_SEL_RMII = BIT(5), 1370 }; 1371 1372 enum { 1373 RK3588_GMAC_CLK_RMII_MODE_SHIFT = 0x0, 1374 RK3588_GMAC_CLK_RMII_MODE_MASK = BIT(0), 1375 RK3588_GMAC_CLK_RMII_MODE = 0x1, 1376 }; 1377 1378 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 1379 1380 if (pdata->bus_id == 1) { 1381 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RMII << 6; 1382 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK << 6; 1383 clk_mode = RK3588_GMAC_CLK_RMII_MODE << 5; 1384 clk_mode_mask = RK3588_GMAC_CLK_RMII_MODE_MASK << 5; 1385 } else { 1386 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RMII; 1387 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK; 1388 clk_mode = RK3588_GMAC_CLK_RMII_MODE; 1389 clk_mode_mask = RK3588_GMAC_CLK_RMII_MODE_MASK; 1390 } 1391 1392 rk_clrsetreg(&php_grf->gmac_con0, intf_sel_mask, intf_sel); 1393 rk_clrsetreg(&php_grf->clk_con1, clk_mode_mask, clk_mode); 1394 } 1395 1396 static void rk3588_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1397 { 1398 unsigned int rx_enable, rx_enable_mask, tx_enable, tx_enable_mask; 1399 unsigned int intf_sel, intf_sel_mask; 1400 unsigned int clk_mode, clk_mode_mask; 1401 unsigned int rx_delay; 1402 struct rk3588_php_grf *php_grf; 1403 struct rk3588_sys_grf *grf; 1404 void *offset_con; 1405 1406 enum { 1407 RK3588_GMAC_PHY_INTF_SEL_SHIFT = 3, 1408 RK3588_GMAC_PHY_INTF_SEL_MASK = GENMASK(5, 3), 1409 RK3588_GMAC_PHY_INTF_SEL_RGMII = BIT(3), 1410 1411 RK3588_RXCLK_DLY_ENA_GMAC_MASK = BIT(3), 1412 RK3588_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 1413 RK3588_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(3), 1414 1415 RK3588_TXCLK_DLY_ENA_GMAC_MASK = BIT(2), 1416 RK3588_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 1417 RK3588_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(2), 1418 }; 1419 1420 enum { 1421 RK3588_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1422 RK3588_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 8), 1423 1424 RK3588_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1425 RK3588_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 1426 }; 1427 1428 enum { 1429 RK3588_GMAC_CLK_RGMII_MODE_SHIFT = 0x0, 1430 RK3588_GMAC_CLK_RGMII_MODE_MASK = BIT(0), 1431 RK3588_GMAC_CLK_RGMII_MODE = 0x0, 1432 }; 1433 1434 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1435 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 1436 1437 if (pdata->rx_delay < 0) { 1438 rx_enable = RK3588_RXCLK_DLY_ENA_GMAC_DISABLE; 1439 rx_delay = 0; 1440 } else { 1441 rx_enable = RK3588_RXCLK_DLY_ENA_GMAC_ENABLE; 1442 rx_delay = pdata->rx_delay << RK3588_CLK_RX_DL_CFG_GMAC_SHIFT; 1443 } 1444 1445 if (pdata->bus_id == 1) { 1446 offset_con = &grf->soc_con9; 1447 rx_enable = rx_delay << 2; 1448 rx_enable_mask = RK3588_RXCLK_DLY_ENA_GMAC_MASK << 2; 1449 tx_enable = RK3588_TXCLK_DLY_ENA_GMAC_ENABLE << 2; 1450 tx_enable_mask = RK3588_TXCLK_DLY_ENA_GMAC_MASK << 2; 1451 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RGMII << 6; 1452 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK << 6; 1453 clk_mode = RK3588_GMAC_CLK_RGMII_MODE << 5; 1454 clk_mode_mask = RK3588_GMAC_CLK_RGMII_MODE_MASK << 5; 1455 } else { 1456 offset_con = &grf->soc_con8; 1457 rx_enable_mask = RK3588_RXCLK_DLY_ENA_GMAC_MASK; 1458 tx_enable = RK3588_TXCLK_DLY_ENA_GMAC_ENABLE; 1459 tx_enable_mask = RK3588_TXCLK_DLY_ENA_GMAC_MASK; 1460 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RGMII; 1461 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK; 1462 clk_mode = RK3588_GMAC_CLK_RGMII_MODE; 1463 clk_mode_mask = RK3588_GMAC_CLK_RGMII_MODE_MASK; 1464 } 1465 1466 rk_clrsetreg(offset_con, 1467 RK3588_CLK_TX_DL_CFG_GMAC_MASK | 1468 RK3588_CLK_RX_DL_CFG_GMAC_MASK, 1469 (pdata->tx_delay << RK3588_CLK_TX_DL_CFG_GMAC_SHIFT) | 1470 rx_delay); 1471 1472 rk_clrsetreg(&grf->soc_con7, tx_enable_mask | rx_enable_mask, 1473 tx_enable | rx_enable); 1474 1475 rk_clrsetreg(&php_grf->gmac_con0, intf_sel_mask, intf_sel); 1476 rk_clrsetreg(&php_grf->clk_con1, clk_mode_mask, clk_mode); 1477 } 1478 1479 static void rv1106_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 1480 { 1481 struct rv1106_grf *grf; 1482 unsigned char bgs[1] = {0}; 1483 1484 enum { 1485 RV1106_VOGRF_GMAC_CLK_RMII_MODE_MASK = BIT(0), 1486 RV1106_VOGRF_GMAC_CLK_RMII_MODE = BIT(0), 1487 }; 1488 1489 enum { 1490 RV1106_MACPHY_ENABLE_MASK = BIT(1), 1491 RV1106_MACPHY_DISENABLE = BIT(1), 1492 RV1106_MACPHY_ENABLE = 0, 1493 RV1106_MACPHY_XMII_SEL_MASK = GENMASK(6, 5), 1494 RV1106_MACPHY_XMII_SEL = BIT(6), 1495 RV1106_MACPHY_24M_CLK_SEL_MASK = GENMASK(9, 7), 1496 RV1106_MACPHY_24M_CLK_SEL_24M = (BIT(8) | BIT(9)), 1497 RV1106_MACPHY_PHY_ID_MASK = GENMASK(14, 10), 1498 RV1106_MACPHY_PHY_ID = BIT(11), 1499 }; 1500 1501 enum { 1502 RV1106_MACPHY_BGS_MASK = GENMASK(3, 0), 1503 RV1106_MACPHY_BGS = BIT(2), 1504 }; 1505 1506 #if defined(CONFIG_ROCKCHIP_EFUSE) || defined(CONFIG_ROCKCHIP_OTP) 1507 struct udevice *dev; 1508 u32 regs[2] = {0}; 1509 ofnode node; 1510 int ret = 0; 1511 1512 /* retrieve the device */ 1513 if (IS_ENABLED(CONFIG_ROCKCHIP_EFUSE)) 1514 ret = uclass_get_device_by_driver(UCLASS_MISC, 1515 DM_GET_DRIVER(rockchip_efuse), 1516 &dev); 1517 else 1518 ret = uclass_get_device_by_driver(UCLASS_MISC, 1519 DM_GET_DRIVER(rockchip_otp), 1520 &dev); 1521 if (!ret) { 1522 node = dev_read_subnode(dev, "macphy-bgs"); 1523 if (ofnode_valid(node)) { 1524 if (!ofnode_read_u32_array(node, "reg", regs, 2)) { 1525 /* read the bgs from the efuses */ 1526 ret = misc_read(dev, regs[0], &bgs, 1); 1527 if (ret) { 1528 printf("read bgs from efuse/otp failed, ret=%d\n", 1529 ret); 1530 bgs[0] = 0; 1531 } 1532 } 1533 } 1534 } 1535 #endif 1536 1537 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1538 1539 reset_assert(&pdata->phy_reset); 1540 udelay(20); 1541 rk_clrsetreg(&grf->macphy_con0, 1542 RV1106_MACPHY_ENABLE_MASK | 1543 RV1106_MACPHY_XMII_SEL_MASK | 1544 RV1106_MACPHY_24M_CLK_SEL_MASK | 1545 RV1106_MACPHY_PHY_ID_MASK, 1546 RV1106_MACPHY_ENABLE | 1547 RV1106_MACPHY_XMII_SEL | 1548 RV1106_MACPHY_24M_CLK_SEL_24M | 1549 RV1106_MACPHY_PHY_ID); 1550 1551 rk_clrsetreg(&grf->macphy_con1, 1552 RV1106_MACPHY_BGS_MASK, 1553 bgs[0]); 1554 udelay(20); 1555 reset_deassert(&pdata->phy_reset); 1556 udelay(30 * 1000); 1557 } 1558 1559 static void rv1106_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1560 { 1561 struct rv1106_grf *grf; 1562 enum { 1563 RV1106_VOGRF_GMAC_CLK_RMII_MODE_MASK = BIT(0), 1564 RV1106_VOGRF_GMAC_CLK_RMII_MODE = BIT(0), 1565 }; 1566 1567 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1568 rk_clrsetreg(&grf->gmac_clk_con, 1569 RV1106_VOGRF_GMAC_CLK_RMII_MODE_MASK, 1570 RV1106_VOGRF_GMAC_CLK_RMII_MODE); 1571 }; 1572 1573 static void rv1126_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1574 { 1575 struct rv1126_grf *grf; 1576 1577 enum { 1578 RV1126_GMAC_PHY_INTF_SEL_SHIFT = 4, 1579 RV1126_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1580 RV1126_GMAC_PHY_INTF_SEL_RMII = BIT(6), 1581 }; 1582 1583 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1584 1585 rk_clrsetreg(&grf->mac_con0, 1586 RV1126_GMAC_PHY_INTF_SEL_MASK, 1587 RV1126_GMAC_PHY_INTF_SEL_RMII); 1588 } 1589 1590 static void rv1126_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1591 { 1592 struct rv1126_grf *grf; 1593 1594 enum { 1595 RV1126_GMAC_PHY_INTF_SEL_SHIFT = 4, 1596 RV1126_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1597 RV1126_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 1598 1599 RV1126_RXCLK_M1_DLY_ENA_GMAC_MASK = BIT(3), 1600 RV1126_RXCLK_M1_DLY_ENA_GMAC_DISABLE = 0, 1601 RV1126_RXCLK_M1_DLY_ENA_GMAC_ENABLE = BIT(3), 1602 1603 RV1126_TXCLK_M1_DLY_ENA_GMAC_MASK = BIT(2), 1604 RV1126_TXCLK_M1_DLY_ENA_GMAC_DISABLE = 0, 1605 RV1126_TXCLK_M1_DLY_ENA_GMAC_ENABLE = BIT(2), 1606 1607 RV1126_RXCLK_M0_DLY_ENA_GMAC_MASK = BIT(1), 1608 RV1126_RXCLK_M0_DLY_ENA_GMAC_DISABLE = 0, 1609 RV1126_RXCLK_M0_DLY_ENA_GMAC_ENABLE = BIT(1), 1610 1611 RV1126_TXCLK_M0_DLY_ENA_GMAC_MASK = BIT(0), 1612 RV1126_TXCLK_M0_DLY_ENA_GMAC_DISABLE = 0, 1613 RV1126_TXCLK_M0_DLY_ENA_GMAC_ENABLE = BIT(0), 1614 }; 1615 enum { 1616 RV1126_M0_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1617 RV1126_M0_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 1618 1619 RV1126_M0_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1620 RV1126_M0_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 1621 }; 1622 enum { 1623 RV1126_M1_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1624 RV1126_M1_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 1625 1626 RV1126_M1_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1627 RV1126_M1_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 1628 }; 1629 1630 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1631 1632 rk_clrsetreg(&grf->mac_con0, 1633 RV1126_TXCLK_M0_DLY_ENA_GMAC_MASK | 1634 RV1126_RXCLK_M0_DLY_ENA_GMAC_MASK | 1635 RV1126_TXCLK_M1_DLY_ENA_GMAC_MASK | 1636 RV1126_RXCLK_M1_DLY_ENA_GMAC_MASK | 1637 RV1126_GMAC_PHY_INTF_SEL_MASK, 1638 RV1126_TXCLK_M0_DLY_ENA_GMAC_ENABLE | 1639 RV1126_RXCLK_M0_DLY_ENA_GMAC_ENABLE | 1640 RV1126_TXCLK_M1_DLY_ENA_GMAC_ENABLE | 1641 RV1126_RXCLK_M1_DLY_ENA_GMAC_ENABLE | 1642 RV1126_GMAC_PHY_INTF_SEL_RGMII); 1643 1644 rk_clrsetreg(&grf->mac_con1, 1645 RV1126_M0_CLK_RX_DL_CFG_GMAC_MASK | 1646 RV1126_M0_CLK_TX_DL_CFG_GMAC_MASK, 1647 (pdata->rx_delay << RV1126_M0_CLK_RX_DL_CFG_GMAC_SHIFT) | 1648 (pdata->tx_delay << RV1126_M0_CLK_TX_DL_CFG_GMAC_SHIFT)); 1649 1650 rk_clrsetreg(&grf->mac_con2, 1651 RV1126_M1_CLK_RX_DL_CFG_GMAC_MASK | 1652 RV1126_M1_CLK_TX_DL_CFG_GMAC_MASK, 1653 (pdata->rx_delay << RV1126_M1_CLK_RX_DL_CFG_GMAC_SHIFT) | 1654 (pdata->tx_delay << RV1126_M1_CLK_TX_DL_CFG_GMAC_SHIFT)); 1655 } 1656 #endif 1657 1658 #ifdef CONFIG_DWC_ETH_QOS 1659 static void rk3528_set_clock_selection(struct gmac_rockchip_platdata *pdata) 1660 { 1661 struct rk3528_grf *grf; 1662 unsigned int val; 1663 1664 enum { 1665 RK3528_GMAC1_CLK_SELET_SHIFT = 0x12, 1666 RK3528_GMAC1_CLK_SELET_MASK = BIT(12), 1667 RK3528_GMAC1_CLK_SELET_CRU = 0, 1668 RK3528_GMAC1_CLK_SELET_IO = BIT(12), 1669 }; 1670 1671 if (!pdata->bus_id) 1672 return; 1673 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1674 1675 val = pdata->clock_input ? RK3528_GMAC1_CLK_SELET_IO : 1676 RK3528_GMAC1_CLK_SELET_CRU; 1677 rk_clrsetreg(&grf->gmac1_con0, RK3528_GMAC1_CLK_SELET_MASK, val); 1678 } 1679 1680 static void rk3588_set_clock_selection(struct gmac_rockchip_platdata *pdata) 1681 { 1682 struct rk3588_php_grf *php_grf; 1683 unsigned int val, mask; 1684 1685 enum { 1686 RK3588_GMAC_CLK_SELET_SHIFT = 0x4, 1687 RK3588_GMAC_CLK_SELET_MASK = BIT(4), 1688 RK3588_GMAC_CLK_SELET_CRU = BIT(4), 1689 RK3588_GMAC_CLK_SELET_IO = 0, 1690 }; 1691 1692 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 1693 val = pdata->clock_input ? RK3588_GMAC_CLK_SELET_IO : 1694 RK3588_GMAC_CLK_SELET_CRU; 1695 mask = RK3588_GMAC_CLK_SELET_MASK; 1696 1697 if (pdata->bus_id == 1) { 1698 val <<= 5; 1699 mask <<= 5; 1700 } 1701 1702 rk_clrsetreg(&php_grf->clk_con1, mask, val); 1703 } 1704 #endif 1705 1706 static int gmac_rockchip_probe(struct udevice *dev) 1707 { 1708 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 1709 struct rk_gmac_ops *ops = 1710 (struct rk_gmac_ops *)dev_get_driver_data(dev); 1711 #ifdef CONFIG_DWC_ETH_QOS 1712 struct eqos_config *config; 1713 #else 1714 struct dw_eth_pdata *dw_pdata; 1715 #endif 1716 struct eth_pdata *eth_pdata; 1717 struct clk clk; 1718 ulong rate; 1719 int ret; 1720 1721 #ifdef CONFIG_DWC_ETH_QOS 1722 eth_pdata = &pdata->eth_pdata; 1723 config = (struct eqos_config *)&ops->config; 1724 memcpy(config, &eqos_rockchip_config, sizeof(struct eqos_config)); 1725 eth_pdata->phy_interface = config->ops->eqos_get_interface(dev); 1726 #else 1727 dw_pdata = &pdata->dw_eth_pdata; 1728 eth_pdata = &dw_pdata->eth_pdata; 1729 #endif 1730 pdata->bus_id = dev->seq; 1731 1732 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 1733 ret = clk_set_defaults(dev); 1734 if (ret) 1735 debug("%s clk_set_defaults failed %d\n", __func__, ret); 1736 1737 ret = clk_get_by_index(dev, 0, &clk); 1738 if (ret) 1739 return ret; 1740 1741 pdata->phy_interface = eth_pdata->phy_interface; 1742 1743 if (ops->set_clock_selection) 1744 ops->set_clock_selection(pdata); 1745 1746 if (pdata->integrated_phy && ops->integrated_phy_powerup) 1747 ops->integrated_phy_powerup(pdata); 1748 1749 switch (eth_pdata->phy_interface) { 1750 case PHY_INTERFACE_MODE_RGMII: 1751 case PHY_INTERFACE_MODE_RGMII_RXID: 1752 /* 1753 * If the gmac clock is from internal pll, need to set and 1754 * check the return value for gmac clock at RGMII mode. If 1755 * the gmac clock is from external source, the clock rate 1756 * is not set, because of it is bypassed. 1757 */ 1758 if (!pdata->clock_input) { 1759 rate = clk_set_rate(&clk, 125000000); 1760 if (rate != 125000000) 1761 return -EINVAL; 1762 } 1763 1764 if (eth_pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) 1765 pdata->rx_delay = -1; 1766 1767 /* Set to RGMII mode */ 1768 if (ops->set_to_rgmii) 1769 ops->set_to_rgmii(pdata); 1770 else 1771 return -EPERM; 1772 1773 break; 1774 case PHY_INTERFACE_MODE_RMII: 1775 /* The commet is the same as RGMII mode */ 1776 if (!pdata->clock_input) { 1777 rate = clk_set_rate(&clk, 50000000); 1778 if (rate != 50000000) 1779 return -EINVAL; 1780 } 1781 1782 /* Set to RMII mode */ 1783 if (ops->set_to_rmii) 1784 ops->set_to_rmii(pdata); 1785 1786 break; 1787 default: 1788 debug("NO interface defined!\n"); 1789 return -ENXIO; 1790 } 1791 1792 #ifdef CONFIG_DWC_ETH_QOS 1793 return eqos_probe(dev); 1794 #else 1795 return designware_eth_probe(dev); 1796 #endif 1797 } 1798 1799 static int gmac_rockchip_eth_write_hwaddr(struct udevice *dev) 1800 { 1801 #if defined(CONFIG_DWC_ETH_QOS) 1802 return eqos_write_hwaddr(dev); 1803 #else 1804 return designware_eth_write_hwaddr(dev); 1805 #endif 1806 } 1807 1808 static int gmac_rockchip_eth_free_pkt(struct udevice *dev, uchar *packet, 1809 int length) 1810 { 1811 #ifdef CONFIG_DWC_ETH_QOS 1812 return eqos_free_pkt(dev, packet, length); 1813 #else 1814 return designware_eth_free_pkt(dev, packet, length); 1815 #endif 1816 } 1817 1818 static int gmac_rockchip_eth_send(struct udevice *dev, void *packet, 1819 int length) 1820 { 1821 #ifdef CONFIG_DWC_ETH_QOS 1822 return eqos_send(dev, packet, length); 1823 #else 1824 return designware_eth_send(dev, packet, length); 1825 #endif 1826 } 1827 1828 static int gmac_rockchip_eth_recv(struct udevice *dev, int flags, 1829 uchar **packetp) 1830 { 1831 #ifdef CONFIG_DWC_ETH_QOS 1832 return eqos_recv(dev, flags, packetp); 1833 #else 1834 return designware_eth_recv(dev, flags, packetp); 1835 #endif 1836 } 1837 1838 static int gmac_rockchip_eth_start(struct udevice *dev) 1839 { 1840 struct rockchip_eth_dev *priv = dev_get_priv(dev); 1841 struct rk_gmac_ops *ops = 1842 (struct rk_gmac_ops *)dev_get_driver_data(dev); 1843 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 1844 #ifndef CONFIG_DWC_ETH_QOS 1845 struct dw_eth_pdata *dw_pdata; 1846 struct eth_pdata *eth_pdata; 1847 #endif 1848 int ret; 1849 1850 #ifdef CONFIG_DWC_ETH_QOS 1851 ret = eqos_init(dev); 1852 #else 1853 dw_pdata = &pdata->dw_eth_pdata; 1854 eth_pdata = &dw_pdata->eth_pdata; 1855 ret = designware_eth_init((struct dw_eth_dev *)priv, 1856 eth_pdata->enetaddr); 1857 #endif 1858 if (ret) 1859 return ret; 1860 ret = ops->fix_mac_speed(pdata, priv); 1861 if (ret) 1862 return ret; 1863 1864 #ifdef CONFIG_DWC_ETH_QOS 1865 eqos_enable(dev); 1866 #else 1867 ret = designware_eth_enable((struct dw_eth_dev *)priv); 1868 if (ret) 1869 return ret; 1870 #endif 1871 1872 return 0; 1873 } 1874 1875 static void gmac_rockchip_eth_stop(struct udevice *dev) 1876 { 1877 #ifdef CONFIG_DWC_ETH_QOS 1878 eqos_stop(dev); 1879 #else 1880 designware_eth_stop(dev); 1881 #endif 1882 } 1883 1884 const struct eth_ops gmac_rockchip_eth_ops = { 1885 .start = gmac_rockchip_eth_start, 1886 .send = gmac_rockchip_eth_send, 1887 .recv = gmac_rockchip_eth_recv, 1888 .free_pkt = gmac_rockchip_eth_free_pkt, 1889 .stop = gmac_rockchip_eth_stop, 1890 .write_hwaddr = gmac_rockchip_eth_write_hwaddr, 1891 }; 1892 1893 #ifndef CONFIG_DWC_ETH_QOS 1894 const struct rk_gmac_ops px30_gmac_ops = { 1895 .fix_mac_speed = px30_gmac_fix_mac_speed, 1896 .set_to_rmii = px30_gmac_set_to_rmii, 1897 }; 1898 1899 const struct rk_gmac_ops rk1808_gmac_ops = { 1900 .fix_mac_speed = rk1808_gmac_fix_mac_speed, 1901 .set_to_rgmii = rk1808_gmac_set_to_rgmii, 1902 }; 1903 1904 const struct rk_gmac_ops rk3228_gmac_ops = { 1905 .fix_mac_speed = rk3228_gmac_fix_mac_speed, 1906 .set_to_rmii = rk3228_gmac_set_to_rmii, 1907 .set_to_rgmii = rk3228_gmac_set_to_rgmii, 1908 .integrated_phy_powerup = rk3228_gmac_integrated_phy_powerup, 1909 }; 1910 1911 const struct rk_gmac_ops rk3288_gmac_ops = { 1912 .fix_mac_speed = rk3288_gmac_fix_mac_speed, 1913 .set_to_rgmii = rk3288_gmac_set_to_rgmii, 1914 }; 1915 1916 const struct rk_gmac_ops rk3308_gmac_ops = { 1917 .fix_mac_speed = rk3308_gmac_fix_mac_speed, 1918 .set_to_rmii = rk3308_gmac_set_to_rmii, 1919 }; 1920 1921 const struct rk_gmac_ops rk3328_gmac_ops = { 1922 .fix_mac_speed = rk3328_gmac_fix_mac_speed, 1923 .set_to_rmii = rk3328_gmac_set_to_rmii, 1924 .set_to_rgmii = rk3328_gmac_set_to_rgmii, 1925 .integrated_phy_powerup = rk3328_gmac_integrated_phy_powerup, 1926 }; 1927 1928 const struct rk_gmac_ops rk3368_gmac_ops = { 1929 .fix_mac_speed = rk3368_gmac_fix_mac_speed, 1930 .set_to_rgmii = rk3368_gmac_set_to_rgmii, 1931 }; 1932 1933 const struct rk_gmac_ops rk3399_gmac_ops = { 1934 .fix_mac_speed = rk3399_gmac_fix_mac_speed, 1935 .set_to_rgmii = rk3399_gmac_set_to_rgmii, 1936 }; 1937 1938 const struct rk_gmac_ops rv1108_gmac_ops = { 1939 .fix_mac_speed = rv1108_set_rmii_speed, 1940 .set_to_rmii = rv1108_gmac_set_to_rmii, 1941 }; 1942 #else 1943 const struct rk_gmac_ops rk3528_gmac_ops = { 1944 .fix_mac_speed = rk3528_set_rgmii_speed, 1945 .set_to_rgmii = rk3528_set_to_rgmii, 1946 .set_to_rmii = rk3528_set_to_rmii, 1947 .set_clock_selection = rk3528_set_clock_selection, 1948 .integrated_phy_powerup = rk3528_gmac_integrated_phy_powerup, 1949 }; 1950 1951 const struct rk_gmac_ops rk3568_gmac_ops = { 1952 .fix_mac_speed = rv1126_set_rgmii_speed, 1953 .set_to_rgmii = rk3568_set_to_rgmii, 1954 .set_to_rmii = rk3568_set_to_rmii, 1955 }; 1956 1957 const struct rk_gmac_ops rk3588_gmac_ops = { 1958 .fix_mac_speed = rk3588_set_rgmii_speed, 1959 .set_to_rgmii = rk3588_set_to_rgmii, 1960 .set_to_rmii = rk3588_set_to_rmii, 1961 .set_clock_selection = rk3588_set_clock_selection, 1962 }; 1963 1964 const struct rk_gmac_ops rv1106_gmac_ops = { 1965 .fix_mac_speed = rv1106_set_rmii_speed, 1966 .set_to_rmii = rv1106_set_to_rmii, 1967 .integrated_phy_powerup = rv1106_gmac_integrated_phy_powerup, 1968 }; 1969 1970 const struct rk_gmac_ops rv1126_gmac_ops = { 1971 .fix_mac_speed = rv1126_set_rgmii_speed, 1972 .set_to_rgmii = rv1126_set_to_rgmii, 1973 .set_to_rmii = rv1126_set_to_rmii, 1974 }; 1975 #endif 1976 1977 static const struct udevice_id rockchip_gmac_ids[] = { 1978 #ifndef CONFIG_DWC_ETH_QOS 1979 #ifdef CONFIG_ROCKCHIP_PX30 1980 { .compatible = "rockchip,px30-gmac", 1981 .data = (ulong)&px30_gmac_ops }, 1982 #endif 1983 1984 #ifdef CONFIG_ROCKCHIP_RK1808 1985 { .compatible = "rockchip,rk1808-gmac", 1986 .data = (ulong)&rk1808_gmac_ops }, 1987 #endif 1988 1989 #ifdef CONFIG_ROCKCHIP_RK3228 1990 { .compatible = "rockchip,rk3228-gmac", 1991 .data = (ulong)&rk3228_gmac_ops }, 1992 #endif 1993 1994 #ifdef CONFIG_ROCKCHIP_RK3288 1995 { .compatible = "rockchip,rk3288-gmac", 1996 .data = (ulong)&rk3288_gmac_ops }, 1997 #endif 1998 1999 #ifdef CONFIG_ROCKCHIP_RK3308 2000 { .compatible = "rockchip,rk3308-mac", 2001 .data = (ulong)&rk3308_gmac_ops }, 2002 #endif 2003 2004 #ifdef CONFIG_ROCKCHIP_RK3328 2005 { .compatible = "rockchip,rk3328-gmac", 2006 .data = (ulong)&rk3328_gmac_ops }, 2007 #endif 2008 2009 #ifdef CONFIG_ROCKCHIP_RK3368 2010 { .compatible = "rockchip,rk3368-gmac", 2011 .data = (ulong)&rk3368_gmac_ops }, 2012 #endif 2013 2014 #ifdef CONFIG_ROCKCHIP_RK3399 2015 { .compatible = "rockchip,rk3399-gmac", 2016 .data = (ulong)&rk3399_gmac_ops }, 2017 #endif 2018 2019 #ifdef CONFIG_ROCKCHIP_RV1108 2020 { .compatible = "rockchip,rv1108-gmac", 2021 .data = (ulong)&rv1108_gmac_ops }, 2022 #endif 2023 #else 2024 #ifdef CONFIG_ROCKCHIP_RK3528 2025 { .compatible = "rockchip,rk3528-gmac", 2026 .data = (ulong)&rk3528_gmac_ops }, 2027 #endif 2028 2029 #ifdef CONFIG_ROCKCHIP_RK3568 2030 { .compatible = "rockchip,rk3568-gmac", 2031 .data = (ulong)&rk3568_gmac_ops }, 2032 #endif 2033 2034 #ifdef CONFIG_ROCKCHIP_RK3588 2035 { .compatible = "rockchip,rk3588-gmac", 2036 .data = (ulong)&rk3588_gmac_ops }, 2037 #endif 2038 2039 #ifdef CONFIG_ROCKCHIP_RV1106 2040 { .compatible = "rockchip,rv1106-gmac", 2041 .data = (ulong)&rv1106_gmac_ops }, 2042 #endif 2043 2044 #ifdef CONFIG_ROCKCHIP_RV1126 2045 { .compatible = "rockchip,rv1126-gmac", 2046 .data = (ulong)&rv1126_gmac_ops }, 2047 #endif 2048 #endif 2049 { } 2050 }; 2051 2052 U_BOOT_DRIVER(eth_gmac_rockchip) = { 2053 .name = "gmac_rockchip", 2054 .id = UCLASS_ETH, 2055 .of_match = rockchip_gmac_ids, 2056 .ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata, 2057 .probe = gmac_rockchip_probe, 2058 .ops = &gmac_rockchip_eth_ops, 2059 .priv_auto_alloc_size = sizeof(struct rockchip_eth_dev), 2060 .platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata), 2061 .flags = DM_FLAG_ALLOC_PRIV_DMA, 2062 }; 2063