1 /* 2 * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Rockchip GMAC ethernet IP driver for U-Boot 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <clk.h> 12 #include <phy.h> 13 #include <syscon.h> 14 #include <asm/io.h> 15 #include <asm/arch/periph.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/hardware.h> 18 #include <asm/arch/grf_px30.h> 19 #include <asm/arch/grf_rk1808.h> 20 #include <asm/arch/grf_rk322x.h> 21 #include <asm/arch/grf_rk3288.h> 22 #include <asm/arch/grf_rk3308.h> 23 #include <asm/arch/grf_rk3328.h> 24 #include <asm/arch/grf_rk3368.h> 25 #include <asm/arch/grf_rk3399.h> 26 #include <asm/arch/grf_rv1108.h> 27 #include <dm/pinctrl.h> 28 #include <dt-bindings/clock/rk3288-cru.h> 29 #include "designware.h" 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 /* 34 * Platform data for the gmac 35 * 36 * dw_eth_pdata: Required platform data for designware driver (must be first) 37 */ 38 struct gmac_rockchip_platdata { 39 struct dw_eth_pdata dw_eth_pdata; 40 bool clock_input; 41 int tx_delay; 42 int rx_delay; 43 }; 44 45 struct rk_gmac_ops { 46 int (*fix_mac_speed)(struct dw_eth_dev *priv); 47 void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata); 48 void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata); 49 }; 50 51 void gmac_set_rgmii(struct udevice *dev, u32 tx_delay, u32 rx_delay) 52 { 53 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 54 struct rk_gmac_ops *ops = 55 (struct rk_gmac_ops *)dev_get_driver_data(dev); 56 57 pdata->tx_delay = tx_delay; 58 pdata->rx_delay = rx_delay; 59 60 ops->set_to_rgmii(pdata); 61 } 62 63 static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) 64 { 65 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 66 const char *string; 67 68 string = dev_read_string(dev, "clock_in_out"); 69 if (!strcmp(string, "input")) 70 pdata->clock_input = true; 71 else 72 pdata->clock_input = false; 73 74 /* Check the new naming-style first... */ 75 pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT); 76 pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT); 77 78 /* ... and fall back to the old naming style or default, if necessary */ 79 if (pdata->tx_delay == -ENOENT) 80 pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30); 81 if (pdata->rx_delay == -ENOENT) 82 pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10); 83 84 return designware_eth_ofdata_to_platdata(dev); 85 } 86 87 static int px30_gmac_fix_mac_speed(struct dw_eth_dev *priv) 88 { 89 struct px30_grf *grf; 90 struct clk clk_speed; 91 int speed, ret; 92 enum { 93 PX30_GMAC_SPEED_SHIFT = 0x2, 94 PX30_GMAC_SPEED_MASK = BIT(2), 95 PX30_GMAC_SPEED_10M = 0, 96 PX30_GMAC_SPEED_100M = BIT(2), 97 }; 98 99 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 100 &clk_speed); 101 if (ret) 102 return ret; 103 104 switch (priv->phydev->speed) { 105 case 10: 106 speed = PX30_GMAC_SPEED_10M; 107 ret = clk_set_rate(&clk_speed, 2500000); 108 if (ret) 109 return ret; 110 break; 111 case 100: 112 speed = PX30_GMAC_SPEED_100M; 113 ret = clk_set_rate(&clk_speed, 25000000); 114 if (ret) 115 return ret; 116 break; 117 default: 118 debug("Unknown phy speed: %d\n", priv->phydev->speed); 119 return -EINVAL; 120 } 121 122 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 123 rk_clrsetreg(&grf->mac_con1, PX30_GMAC_SPEED_MASK, speed); 124 125 return 0; 126 } 127 128 static int rk1808_gmac_fix_mac_speed(struct dw_eth_dev *priv) 129 { 130 struct clk clk_speed; 131 int ret; 132 133 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 134 &clk_speed); 135 if (ret) 136 return ret; 137 138 switch (priv->phydev->speed) { 139 case 10: 140 ret = clk_set_rate(&clk_speed, 2500000); 141 if (ret) 142 return ret; 143 break; 144 case 100: 145 ret = clk_set_rate(&clk_speed, 25000000); 146 if (ret) 147 return ret; 148 break; 149 case 1000: 150 ret = clk_set_rate(&clk_speed, 125000000); 151 if (ret) 152 return ret; 153 break; 154 default: 155 debug("Unknown phy speed: %d\n", priv->phydev->speed); 156 return -EINVAL; 157 } 158 159 return 0; 160 } 161 162 static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv) 163 { 164 struct rk322x_grf *grf; 165 int clk; 166 enum { 167 RK3228_GMAC_CLK_SEL_SHIFT = 8, 168 RK3228_GMAC_CLK_SEL_MASK = GENMASK(9, 8), 169 RK3228_GMAC_CLK_SEL_125M = 0 << 8, 170 RK3228_GMAC_CLK_SEL_25M = 3 << 8, 171 RK3228_GMAC_CLK_SEL_2_5M = 2 << 8, 172 }; 173 174 switch (priv->phydev->speed) { 175 case 10: 176 clk = RK3228_GMAC_CLK_SEL_2_5M; 177 break; 178 case 100: 179 clk = RK3228_GMAC_CLK_SEL_25M; 180 break; 181 case 1000: 182 clk = RK3228_GMAC_CLK_SEL_125M; 183 break; 184 default: 185 debug("Unknown phy speed: %d\n", priv->phydev->speed); 186 return -EINVAL; 187 } 188 189 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 190 rk_clrsetreg(&grf->mac_con[1], RK3228_GMAC_CLK_SEL_MASK, clk); 191 192 return 0; 193 } 194 195 static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv) 196 { 197 struct rk3288_grf *grf; 198 int clk; 199 200 switch (priv->phydev->speed) { 201 case 10: 202 clk = RK3288_GMAC_CLK_SEL_2_5M; 203 break; 204 case 100: 205 clk = RK3288_GMAC_CLK_SEL_25M; 206 break; 207 case 1000: 208 clk = RK3288_GMAC_CLK_SEL_125M; 209 break; 210 default: 211 debug("Unknown phy speed: %d\n", priv->phydev->speed); 212 return -EINVAL; 213 } 214 215 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 216 rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk); 217 218 return 0; 219 } 220 221 static int rk3308_gmac_fix_mac_speed(struct dw_eth_dev *priv) 222 { 223 struct rk3308_grf *grf; 224 struct clk clk_speed; 225 int speed, ret; 226 enum { 227 RK3308_GMAC_SPEED_SHIFT = 0x0, 228 RK3308_GMAC_SPEED_MASK = BIT(0), 229 RK3308_GMAC_SPEED_10M = 0, 230 RK3308_GMAC_SPEED_100M = BIT(0), 231 }; 232 233 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 234 &clk_speed); 235 if (ret) 236 return ret; 237 238 switch (priv->phydev->speed) { 239 case 10: 240 speed = RK3308_GMAC_SPEED_10M; 241 ret = clk_set_rate(&clk_speed, 2500000); 242 if (ret) 243 return ret; 244 break; 245 case 100: 246 speed = RK3308_GMAC_SPEED_100M; 247 ret = clk_set_rate(&clk_speed, 25000000); 248 if (ret) 249 return ret; 250 break; 251 default: 252 debug("Unknown phy speed: %d\n", priv->phydev->speed); 253 return -EINVAL; 254 } 255 256 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 257 rk_clrsetreg(&grf->mac_con0, RK3308_GMAC_SPEED_MASK, speed); 258 259 return 0; 260 } 261 262 static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv) 263 { 264 struct rk3328_grf_regs *grf; 265 int clk; 266 enum { 267 RK3328_GMAC_CLK_SEL_SHIFT = 11, 268 RK3328_GMAC_CLK_SEL_MASK = GENMASK(12, 11), 269 RK3328_GMAC_CLK_SEL_125M = 0 << 11, 270 RK3328_GMAC_CLK_SEL_25M = 3 << 11, 271 RK3328_GMAC_CLK_SEL_2_5M = 2 << 11, 272 }; 273 274 switch (priv->phydev->speed) { 275 case 10: 276 clk = RK3328_GMAC_CLK_SEL_2_5M; 277 break; 278 case 100: 279 clk = RK3328_GMAC_CLK_SEL_25M; 280 break; 281 case 1000: 282 clk = RK3328_GMAC_CLK_SEL_125M; 283 break; 284 default: 285 debug("Unknown phy speed: %d\n", priv->phydev->speed); 286 return -EINVAL; 287 } 288 289 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 290 rk_clrsetreg(&grf->mac_con[1], RK3328_GMAC_CLK_SEL_MASK, clk); 291 292 return 0; 293 } 294 295 static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv) 296 { 297 struct rk3368_grf *grf; 298 int clk; 299 enum { 300 RK3368_GMAC_CLK_SEL_2_5M = 2 << 4, 301 RK3368_GMAC_CLK_SEL_25M = 3 << 4, 302 RK3368_GMAC_CLK_SEL_125M = 0 << 4, 303 RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4), 304 }; 305 306 switch (priv->phydev->speed) { 307 case 10: 308 clk = RK3368_GMAC_CLK_SEL_2_5M; 309 break; 310 case 100: 311 clk = RK3368_GMAC_CLK_SEL_25M; 312 break; 313 case 1000: 314 clk = RK3368_GMAC_CLK_SEL_125M; 315 break; 316 default: 317 debug("Unknown phy speed: %d\n", priv->phydev->speed); 318 return -EINVAL; 319 } 320 321 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 322 rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk); 323 324 return 0; 325 } 326 327 static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv) 328 { 329 struct rk3399_grf_regs *grf; 330 int clk; 331 332 switch (priv->phydev->speed) { 333 case 10: 334 clk = RK3399_GMAC_CLK_SEL_2_5M; 335 break; 336 case 100: 337 clk = RK3399_GMAC_CLK_SEL_25M; 338 break; 339 case 1000: 340 clk = RK3399_GMAC_CLK_SEL_125M; 341 break; 342 default: 343 debug("Unknown phy speed: %d\n", priv->phydev->speed); 344 return -EINVAL; 345 } 346 347 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 348 rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk); 349 350 return 0; 351 } 352 353 static int rv1108_set_rmii_speed(struct dw_eth_dev *priv) 354 { 355 struct rv1108_grf *grf; 356 int clk, speed; 357 enum { 358 RV1108_GMAC_SPEED_MASK = BIT(2), 359 RV1108_GMAC_SPEED_10M = 0 << 2, 360 RV1108_GMAC_SPEED_100M = 1 << 2, 361 RV1108_GMAC_CLK_SEL_MASK = BIT(7), 362 RV1108_GMAC_CLK_SEL_2_5M = 0 << 7, 363 RV1108_GMAC_CLK_SEL_25M = 1 << 7, 364 }; 365 366 switch (priv->phydev->speed) { 367 case 10: 368 clk = RV1108_GMAC_CLK_SEL_2_5M; 369 speed = RV1108_GMAC_SPEED_10M; 370 break; 371 case 100: 372 clk = RV1108_GMAC_CLK_SEL_25M; 373 speed = RV1108_GMAC_SPEED_100M; 374 break; 375 default: 376 debug("Unknown phy speed: %d\n", priv->phydev->speed); 377 return -EINVAL; 378 } 379 380 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 381 rk_clrsetreg(&grf->gmac_con0, 382 RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK, 383 clk | speed); 384 385 return 0; 386 } 387 388 static void px30_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 389 { 390 struct px30_grf *grf; 391 enum { 392 px30_GMAC_PHY_INTF_SEL_SHIFT = 4, 393 px30_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 6), 394 px30_GMAC_PHY_INTF_SEL_RMII = BIT(6), 395 }; 396 397 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 398 399 rk_clrsetreg(&grf->mac_con1, 400 px30_GMAC_PHY_INTF_SEL_MASK, 401 px30_GMAC_PHY_INTF_SEL_RMII); 402 } 403 404 static void rk1808_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 405 { 406 struct rk1808_grf *grf; 407 enum { 408 RK1808_GMAC_PHY_INTF_SEL_SHIFT = 4, 409 RK1808_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 410 RK1808_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 411 412 RK1808_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 413 RK1808_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 414 RK1808_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 415 416 RK1808_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 417 RK1808_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 418 RK1808_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 419 }; 420 enum { 421 RK1808_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 422 RK1808_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 7), 423 424 RK1808_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 425 RK1808_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 426 }; 427 428 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 429 rk_clrsetreg(&grf->mac_con1, 430 RK1808_GMAC_PHY_INTF_SEL_MASK | 431 RK1808_RXCLK_DLY_ENA_GMAC_MASK | 432 RK1808_TXCLK_DLY_ENA_GMAC_MASK, 433 RK1808_GMAC_PHY_INTF_SEL_RGMII | 434 RK1808_RXCLK_DLY_ENA_GMAC_ENABLE | 435 RK1808_TXCLK_DLY_ENA_GMAC_ENABLE); 436 437 rk_clrsetreg(&grf->mac_con0, 438 RK1808_CLK_RX_DL_CFG_GMAC_MASK | 439 RK1808_CLK_TX_DL_CFG_GMAC_MASK, 440 pdata->rx_delay << RK1808_CLK_RX_DL_CFG_GMAC_SHIFT | 441 pdata->tx_delay << RK1808_CLK_TX_DL_CFG_GMAC_SHIFT); 442 } 443 444 static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 445 { 446 struct rk322x_grf *grf; 447 enum { 448 RK3228_RMII_MODE_SHIFT = 10, 449 RK3228_RMII_MODE_MASK = BIT(10), 450 451 RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4, 452 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 453 RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 454 455 RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 456 RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 457 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 458 459 RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 460 RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 461 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 462 }; 463 enum { 464 RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 465 RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 466 467 RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 468 RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 469 }; 470 471 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 472 rk_clrsetreg(&grf->mac_con[1], 473 RK3228_RMII_MODE_MASK | 474 RK3228_GMAC_PHY_INTF_SEL_MASK | 475 RK3228_RXCLK_DLY_ENA_GMAC_MASK | 476 RK3228_TXCLK_DLY_ENA_GMAC_MASK, 477 RK3228_GMAC_PHY_INTF_SEL_RGMII | 478 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE | 479 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE); 480 481 rk_clrsetreg(&grf->mac_con[0], 482 RK3228_CLK_RX_DL_CFG_GMAC_MASK | 483 RK3228_CLK_TX_DL_CFG_GMAC_MASK, 484 pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT | 485 pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT); 486 } 487 488 static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 489 { 490 struct rk3288_grf *grf; 491 492 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 493 rk_clrsetreg(&grf->soc_con1, 494 RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK, 495 RK3288_GMAC_PHY_INTF_SEL_RGMII); 496 497 rk_clrsetreg(&grf->soc_con3, 498 RK3288_RXCLK_DLY_ENA_GMAC_MASK | 499 RK3288_TXCLK_DLY_ENA_GMAC_MASK | 500 RK3288_CLK_RX_DL_CFG_GMAC_MASK | 501 RK3288_CLK_TX_DL_CFG_GMAC_MASK, 502 RK3288_RXCLK_DLY_ENA_GMAC_ENABLE | 503 RK3288_TXCLK_DLY_ENA_GMAC_ENABLE | 504 pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT | 505 pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT); 506 } 507 508 static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 509 { 510 struct rk3308_grf *grf; 511 enum { 512 RK3308_GMAC_PHY_INTF_SEL_SHIFT = 2, 513 RK3308_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 2), 514 RK3308_GMAC_PHY_INTF_SEL_RMII = BIT(4), 515 }; 516 517 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 518 519 rk_clrsetreg(&grf->mac_con0, 520 RK3308_GMAC_PHY_INTF_SEL_MASK, 521 RK3308_GMAC_PHY_INTF_SEL_RMII); 522 } 523 524 static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 525 { 526 struct rk3328_grf_regs *grf; 527 enum { 528 RK3328_RMII_MODE_SHIFT = 9, 529 RK3328_RMII_MODE_MASK = BIT(9), 530 531 RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4, 532 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 533 RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 534 535 RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 536 RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 537 RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 538 539 RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 540 RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 541 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 542 }; 543 enum { 544 RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 545 RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 546 547 RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 548 RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 549 }; 550 551 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 552 rk_clrsetreg(&grf->mac_con[1], 553 RK3328_RMII_MODE_MASK | 554 RK3328_GMAC_PHY_INTF_SEL_MASK | 555 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 556 RK3328_TXCLK_DLY_ENA_GMAC_MASK, 557 RK3328_GMAC_PHY_INTF_SEL_RGMII | 558 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 559 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE); 560 561 rk_clrsetreg(&grf->mac_con[0], 562 RK3328_CLK_RX_DL_CFG_GMAC_MASK | 563 RK3328_CLK_TX_DL_CFG_GMAC_MASK, 564 pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT | 565 pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT); 566 } 567 568 static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 569 { 570 struct rk3368_grf *grf; 571 enum { 572 RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9, 573 RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9), 574 RK3368_RMII_MODE_MASK = BIT(6), 575 RK3368_RMII_MODE = BIT(6), 576 }; 577 enum { 578 RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15), 579 RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 580 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15), 581 RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7), 582 RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 583 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7), 584 RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8, 585 RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 586 RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0, 587 RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 588 }; 589 590 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 591 rk_clrsetreg(&grf->soc_con15, 592 RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK, 593 RK3368_GMAC_PHY_INTF_SEL_RGMII); 594 595 rk_clrsetreg(&grf->soc_con16, 596 RK3368_RXCLK_DLY_ENA_GMAC_MASK | 597 RK3368_TXCLK_DLY_ENA_GMAC_MASK | 598 RK3368_CLK_RX_DL_CFG_GMAC_MASK | 599 RK3368_CLK_TX_DL_CFG_GMAC_MASK, 600 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE | 601 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE | 602 pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT | 603 pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT); 604 } 605 606 static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 607 { 608 struct rk3399_grf_regs *grf; 609 610 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 611 612 rk_clrsetreg(&grf->soc_con5, 613 RK3399_GMAC_PHY_INTF_SEL_MASK, 614 RK3399_GMAC_PHY_INTF_SEL_RGMII); 615 616 rk_clrsetreg(&grf->soc_con6, 617 RK3399_RXCLK_DLY_ENA_GMAC_MASK | 618 RK3399_TXCLK_DLY_ENA_GMAC_MASK | 619 RK3399_CLK_RX_DL_CFG_GMAC_MASK | 620 RK3399_CLK_TX_DL_CFG_GMAC_MASK, 621 RK3399_RXCLK_DLY_ENA_GMAC_ENABLE | 622 RK3399_TXCLK_DLY_ENA_GMAC_ENABLE | 623 pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT | 624 pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT); 625 } 626 627 static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 628 { 629 struct rv1108_grf *grf; 630 631 enum { 632 RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 633 RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4, 634 }; 635 636 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 637 rk_clrsetreg(&grf->gmac_con0, 638 RV1108_GMAC_PHY_INTF_SEL_MASK, 639 RV1108_GMAC_PHY_INTF_SEL_RMII); 640 } 641 642 static int gmac_rockchip_probe(struct udevice *dev) 643 { 644 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 645 struct rk_gmac_ops *ops = 646 (struct rk_gmac_ops *)dev_get_driver_data(dev); 647 struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev); 648 struct eth_pdata *eth_pdata = &dw_pdata->eth_pdata; 649 struct clk clk; 650 ulong rate; 651 int ret; 652 653 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 654 ret = clk_set_defaults(dev); 655 if (ret) 656 debug("%s clk_set_defaults failed %d\n", __func__, ret); 657 658 ret = clk_get_by_index(dev, 0, &clk); 659 if (ret) 660 return ret; 661 662 switch (eth_pdata->phy_interface) { 663 case PHY_INTERFACE_MODE_RGMII: 664 /* 665 * If the gmac clock is from internal pll, need to set and 666 * check the return value for gmac clock at RGMII mode. If 667 * the gmac clock is from external source, the clock rate 668 * is not set, because of it is bypassed. 669 */ 670 if (!pdata->clock_input) { 671 rate = clk_set_rate(&clk, 125000000); 672 if (rate != 125000000) 673 return -EINVAL; 674 } 675 676 /* Set to RGMII mode */ 677 if (ops->set_to_rgmii) 678 ops->set_to_rgmii(pdata); 679 else 680 return -EPERM; 681 682 break; 683 case PHY_INTERFACE_MODE_RMII: 684 /* The commet is the same as RGMII mode */ 685 if (!pdata->clock_input) { 686 rate = clk_set_rate(&clk, 50000000); 687 if (rate != 50000000) 688 return -EINVAL; 689 } 690 691 /* Set to RMII mode */ 692 if (ops->set_to_rmii) 693 ops->set_to_rmii(pdata); 694 else 695 return -EPERM; 696 697 break; 698 default: 699 debug("NO interface defined!\n"); 700 return -ENXIO; 701 } 702 703 return designware_eth_probe(dev); 704 } 705 706 static int gmac_rockchip_eth_start(struct udevice *dev) 707 { 708 struct eth_pdata *pdata = dev_get_platdata(dev); 709 struct dw_eth_dev *priv = dev_get_priv(dev); 710 struct rk_gmac_ops *ops = 711 (struct rk_gmac_ops *)dev_get_driver_data(dev); 712 int ret; 713 714 ret = designware_eth_init(priv, pdata->enetaddr); 715 if (ret) 716 return ret; 717 ret = ops->fix_mac_speed(priv); 718 if (ret) 719 return ret; 720 ret = designware_eth_enable(priv); 721 if (ret) 722 return ret; 723 724 return 0; 725 } 726 727 const struct eth_ops gmac_rockchip_eth_ops = { 728 .start = gmac_rockchip_eth_start, 729 .send = designware_eth_send, 730 .recv = designware_eth_recv, 731 .free_pkt = designware_eth_free_pkt, 732 .stop = designware_eth_stop, 733 .write_hwaddr = designware_eth_write_hwaddr, 734 }; 735 736 const struct rk_gmac_ops px30_gmac_ops = { 737 .fix_mac_speed = px30_gmac_fix_mac_speed, 738 .set_to_rmii = px30_gmac_set_to_rmii, 739 }; 740 741 const struct rk_gmac_ops rk1808_gmac_ops = { 742 .fix_mac_speed = rk1808_gmac_fix_mac_speed, 743 .set_to_rgmii = rk1808_gmac_set_to_rgmii, 744 }; 745 746 const struct rk_gmac_ops rk3228_gmac_ops = { 747 .fix_mac_speed = rk3228_gmac_fix_mac_speed, 748 .set_to_rgmii = rk3228_gmac_set_to_rgmii, 749 }; 750 751 const struct rk_gmac_ops rk3288_gmac_ops = { 752 .fix_mac_speed = rk3288_gmac_fix_mac_speed, 753 .set_to_rgmii = rk3288_gmac_set_to_rgmii, 754 }; 755 756 const struct rk_gmac_ops rk3308_gmac_ops = { 757 .fix_mac_speed = rk3308_gmac_fix_mac_speed, 758 .set_to_rmii = rk3308_gmac_set_to_rmii, 759 }; 760 761 const struct rk_gmac_ops rk3328_gmac_ops = { 762 .fix_mac_speed = rk3328_gmac_fix_mac_speed, 763 .set_to_rgmii = rk3328_gmac_set_to_rgmii, 764 }; 765 766 const struct rk_gmac_ops rk3368_gmac_ops = { 767 .fix_mac_speed = rk3368_gmac_fix_mac_speed, 768 .set_to_rgmii = rk3368_gmac_set_to_rgmii, 769 }; 770 771 const struct rk_gmac_ops rk3399_gmac_ops = { 772 .fix_mac_speed = rk3399_gmac_fix_mac_speed, 773 .set_to_rgmii = rk3399_gmac_set_to_rgmii, 774 }; 775 776 const struct rk_gmac_ops rv1108_gmac_ops = { 777 .fix_mac_speed = rv1108_set_rmii_speed, 778 .set_to_rmii = rv1108_gmac_set_to_rmii, 779 }; 780 781 static const struct udevice_id rockchip_gmac_ids[] = { 782 { .compatible = "rockchip,px30-gmac", 783 .data = (ulong)&px30_gmac_ops }, 784 { .compatible = "rockchip,rk1808-gmac", 785 .data = (ulong)&rk1808_gmac_ops }, 786 { .compatible = "rockchip,rk3228-gmac", 787 .data = (ulong)&rk3228_gmac_ops }, 788 { .compatible = "rockchip,rk3288-gmac", 789 .data = (ulong)&rk3288_gmac_ops }, 790 { .compatible = "rockchip,rk3308-mac", 791 .data = (ulong)&rk3308_gmac_ops }, 792 { .compatible = "rockchip,rk3328-gmac", 793 .data = (ulong)&rk3328_gmac_ops }, 794 { .compatible = "rockchip,rk3368-gmac", 795 .data = (ulong)&rk3368_gmac_ops }, 796 { .compatible = "rockchip,rk3399-gmac", 797 .data = (ulong)&rk3399_gmac_ops }, 798 { .compatible = "rockchip,rv1108-gmac", 799 .data = (ulong)&rv1108_gmac_ops }, 800 { } 801 }; 802 803 U_BOOT_DRIVER(eth_gmac_rockchip) = { 804 .name = "gmac_rockchip", 805 .id = UCLASS_ETH, 806 .of_match = rockchip_gmac_ids, 807 .ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata, 808 .probe = gmac_rockchip_probe, 809 .ops = &gmac_rockchip_eth_ops, 810 .priv_auto_alloc_size = sizeof(struct dw_eth_dev), 811 .platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata), 812 .flags = DM_FLAG_ALLOC_PRIV_DMA, 813 }; 814