1 /* 2 * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Rockchip GMAC ethernet IP driver for U-Boot 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <clk.h> 12 #include <phy.h> 13 #include <syscon.h> 14 #include <asm/io.h> 15 #include <asm/arch/periph.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/hardware.h> 18 #include <asm/arch/grf_rk322x.h> 19 #include <asm/arch/grf_rk3288.h> 20 #include <asm/arch/grf_rk3308.h> 21 #include <asm/arch/grf_rk3328.h> 22 #include <asm/arch/grf_rk3368.h> 23 #include <asm/arch/grf_rk3399.h> 24 #include <asm/arch/grf_rv1108.h> 25 #include <dm/pinctrl.h> 26 #include <dt-bindings/clock/rk3288-cru.h> 27 #include "designware.h" 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 /* 32 * Platform data for the gmac 33 * 34 * dw_eth_pdata: Required platform data for designware driver (must be first) 35 */ 36 struct gmac_rockchip_platdata { 37 struct dw_eth_pdata dw_eth_pdata; 38 bool clock_input; 39 int tx_delay; 40 int rx_delay; 41 }; 42 43 struct rk_gmac_ops { 44 int (*fix_mac_speed)(struct dw_eth_dev *priv); 45 void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata); 46 void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata); 47 }; 48 49 void gmac_set_rgmii(struct udevice *dev, u32 tx_delay, u32 rx_delay) 50 { 51 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 52 struct rk_gmac_ops *ops = 53 (struct rk_gmac_ops *)dev_get_driver_data(dev); 54 55 pdata->tx_delay = tx_delay; 56 pdata->rx_delay = rx_delay; 57 58 ops->set_to_rgmii(pdata); 59 } 60 61 static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) 62 { 63 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 64 const char *string; 65 66 string = dev_read_string(dev, "clock_in_out"); 67 if (!strcmp(string, "input")) 68 pdata->clock_input = true; 69 else 70 pdata->clock_input = false; 71 72 /* Check the new naming-style first... */ 73 pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT); 74 pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT); 75 76 /* ... and fall back to the old naming style or default, if necessary */ 77 if (pdata->tx_delay == -ENOENT) 78 pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30); 79 if (pdata->rx_delay == -ENOENT) 80 pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10); 81 82 return designware_eth_ofdata_to_platdata(dev); 83 } 84 85 static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv) 86 { 87 struct rk322x_grf *grf; 88 int clk; 89 enum { 90 RK3228_GMAC_CLK_SEL_SHIFT = 8, 91 RK3228_GMAC_CLK_SEL_MASK = GENMASK(9, 8), 92 RK3228_GMAC_CLK_SEL_125M = 0 << 8, 93 RK3228_GMAC_CLK_SEL_25M = 3 << 8, 94 RK3228_GMAC_CLK_SEL_2_5M = 2 << 8, 95 }; 96 97 switch (priv->phydev->speed) { 98 case 10: 99 clk = RK3228_GMAC_CLK_SEL_2_5M; 100 break; 101 case 100: 102 clk = RK3228_GMAC_CLK_SEL_25M; 103 break; 104 case 1000: 105 clk = RK3228_GMAC_CLK_SEL_125M; 106 break; 107 default: 108 debug("Unknown phy speed: %d\n", priv->phydev->speed); 109 return -EINVAL; 110 } 111 112 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 113 rk_clrsetreg(&grf->mac_con[1], RK3228_GMAC_CLK_SEL_MASK, clk); 114 115 return 0; 116 } 117 118 static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv) 119 { 120 struct rk3288_grf *grf; 121 int clk; 122 123 switch (priv->phydev->speed) { 124 case 10: 125 clk = RK3288_GMAC_CLK_SEL_2_5M; 126 break; 127 case 100: 128 clk = RK3288_GMAC_CLK_SEL_25M; 129 break; 130 case 1000: 131 clk = RK3288_GMAC_CLK_SEL_125M; 132 break; 133 default: 134 debug("Unknown phy speed: %d\n", priv->phydev->speed); 135 return -EINVAL; 136 } 137 138 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 139 rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk); 140 141 return 0; 142 } 143 144 static int rk3308_gmac_fix_mac_speed(struct dw_eth_dev *priv) 145 { 146 struct rk3308_grf *grf; 147 struct clk clk_speed; 148 int speed, ret; 149 enum { 150 RK3308_GMAC_SPEED_SHIFT = 0x0, 151 RK3308_GMAC_SPEED_MASK = BIT(0), 152 RK3308_GMAC_SPEED_10M = 0, 153 RK3308_GMAC_SPEED_100M = BIT(0), 154 }; 155 156 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 157 &clk_speed); 158 if (ret) 159 return ret; 160 161 switch (priv->phydev->speed) { 162 case 10: 163 speed = RK3308_GMAC_SPEED_10M; 164 ret = clk_set_rate(&clk_speed, 2500000); 165 if (ret) 166 return ret; 167 break; 168 case 100: 169 speed = RK3308_GMAC_SPEED_100M; 170 ret = clk_set_rate(&clk_speed, 25000000); 171 if (ret) 172 return ret; 173 break; 174 default: 175 debug("Unknown phy speed: %d\n", priv->phydev->speed); 176 return -EINVAL; 177 } 178 179 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 180 rk_clrsetreg(&grf->mac_con0, RK3308_GMAC_SPEED_MASK, speed); 181 182 return 0; 183 } 184 185 static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv) 186 { 187 struct rk3328_grf_regs *grf; 188 int clk; 189 enum { 190 RK3328_GMAC_CLK_SEL_SHIFT = 11, 191 RK3328_GMAC_CLK_SEL_MASK = GENMASK(12, 11), 192 RK3328_GMAC_CLK_SEL_125M = 0 << 11, 193 RK3328_GMAC_CLK_SEL_25M = 3 << 11, 194 RK3328_GMAC_CLK_SEL_2_5M = 2 << 11, 195 }; 196 197 switch (priv->phydev->speed) { 198 case 10: 199 clk = RK3328_GMAC_CLK_SEL_2_5M; 200 break; 201 case 100: 202 clk = RK3328_GMAC_CLK_SEL_25M; 203 break; 204 case 1000: 205 clk = RK3328_GMAC_CLK_SEL_125M; 206 break; 207 default: 208 debug("Unknown phy speed: %d\n", priv->phydev->speed); 209 return -EINVAL; 210 } 211 212 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 213 rk_clrsetreg(&grf->mac_con[1], RK3328_GMAC_CLK_SEL_MASK, clk); 214 215 return 0; 216 } 217 218 static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv) 219 { 220 struct rk3368_grf *grf; 221 int clk; 222 enum { 223 RK3368_GMAC_CLK_SEL_2_5M = 2 << 4, 224 RK3368_GMAC_CLK_SEL_25M = 3 << 4, 225 RK3368_GMAC_CLK_SEL_125M = 0 << 4, 226 RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4), 227 }; 228 229 switch (priv->phydev->speed) { 230 case 10: 231 clk = RK3368_GMAC_CLK_SEL_2_5M; 232 break; 233 case 100: 234 clk = RK3368_GMAC_CLK_SEL_25M; 235 break; 236 case 1000: 237 clk = RK3368_GMAC_CLK_SEL_125M; 238 break; 239 default: 240 debug("Unknown phy speed: %d\n", priv->phydev->speed); 241 return -EINVAL; 242 } 243 244 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 245 rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk); 246 247 return 0; 248 } 249 250 static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv) 251 { 252 struct rk3399_grf_regs *grf; 253 int clk; 254 255 switch (priv->phydev->speed) { 256 case 10: 257 clk = RK3399_GMAC_CLK_SEL_2_5M; 258 break; 259 case 100: 260 clk = RK3399_GMAC_CLK_SEL_25M; 261 break; 262 case 1000: 263 clk = RK3399_GMAC_CLK_SEL_125M; 264 break; 265 default: 266 debug("Unknown phy speed: %d\n", priv->phydev->speed); 267 return -EINVAL; 268 } 269 270 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 271 rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk); 272 273 return 0; 274 } 275 276 static int rv1108_set_rmii_speed(struct dw_eth_dev *priv) 277 { 278 struct rv1108_grf *grf; 279 int clk, speed; 280 enum { 281 RV1108_GMAC_SPEED_MASK = BIT(2), 282 RV1108_GMAC_SPEED_10M = 0 << 2, 283 RV1108_GMAC_SPEED_100M = 1 << 2, 284 RV1108_GMAC_CLK_SEL_MASK = BIT(7), 285 RV1108_GMAC_CLK_SEL_2_5M = 0 << 7, 286 RV1108_GMAC_CLK_SEL_25M = 1 << 7, 287 }; 288 289 switch (priv->phydev->speed) { 290 case 10: 291 clk = RV1108_GMAC_CLK_SEL_2_5M; 292 speed = RV1108_GMAC_SPEED_10M; 293 break; 294 case 100: 295 clk = RV1108_GMAC_CLK_SEL_25M; 296 speed = RV1108_GMAC_SPEED_100M; 297 break; 298 default: 299 debug("Unknown phy speed: %d\n", priv->phydev->speed); 300 return -EINVAL; 301 } 302 303 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 304 rk_clrsetreg(&grf->gmac_con0, 305 RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK, 306 clk | speed); 307 308 return 0; 309 } 310 311 static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 312 { 313 struct rk322x_grf *grf; 314 enum { 315 RK3228_RMII_MODE_SHIFT = 10, 316 RK3228_RMII_MODE_MASK = BIT(10), 317 318 RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4, 319 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 320 RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 321 322 RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 323 RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 324 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 325 326 RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 327 RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 328 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 329 }; 330 enum { 331 RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 332 RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 333 334 RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 335 RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 336 }; 337 338 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 339 rk_clrsetreg(&grf->mac_con[1], 340 RK3228_RMII_MODE_MASK | 341 RK3228_GMAC_PHY_INTF_SEL_MASK | 342 RK3228_RXCLK_DLY_ENA_GMAC_MASK | 343 RK3228_TXCLK_DLY_ENA_GMAC_MASK, 344 RK3228_GMAC_PHY_INTF_SEL_RGMII | 345 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE | 346 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE); 347 348 rk_clrsetreg(&grf->mac_con[0], 349 RK3228_CLK_RX_DL_CFG_GMAC_MASK | 350 RK3228_CLK_TX_DL_CFG_GMAC_MASK, 351 pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT | 352 pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT); 353 } 354 355 static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 356 { 357 struct rk3288_grf *grf; 358 359 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 360 rk_clrsetreg(&grf->soc_con1, 361 RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK, 362 RK3288_GMAC_PHY_INTF_SEL_RGMII); 363 364 rk_clrsetreg(&grf->soc_con3, 365 RK3288_RXCLK_DLY_ENA_GMAC_MASK | 366 RK3288_TXCLK_DLY_ENA_GMAC_MASK | 367 RK3288_CLK_RX_DL_CFG_GMAC_MASK | 368 RK3288_CLK_TX_DL_CFG_GMAC_MASK, 369 RK3288_RXCLK_DLY_ENA_GMAC_ENABLE | 370 RK3288_TXCLK_DLY_ENA_GMAC_ENABLE | 371 pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT | 372 pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT); 373 } 374 375 static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 376 { 377 struct rk3308_grf *grf; 378 enum { 379 RK3308_GMAC_PHY_INTF_SEL_SHIFT = 2, 380 RK3308_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 2), 381 RK3308_GMAC_PHY_INTF_SEL_RMII = BIT(4), 382 }; 383 384 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 385 386 rk_clrsetreg(&grf->mac_con0, 387 RK3308_GMAC_PHY_INTF_SEL_MASK, 388 RK3308_GMAC_PHY_INTF_SEL_RMII); 389 } 390 391 static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 392 { 393 struct rk3328_grf_regs *grf; 394 enum { 395 RK3328_RMII_MODE_SHIFT = 9, 396 RK3328_RMII_MODE_MASK = BIT(9), 397 398 RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4, 399 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 400 RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 401 402 RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 403 RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 404 RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 405 406 RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 407 RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 408 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 409 }; 410 enum { 411 RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 412 RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 413 414 RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 415 RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 416 }; 417 418 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 419 rk_clrsetreg(&grf->mac_con[1], 420 RK3328_RMII_MODE_MASK | 421 RK3328_GMAC_PHY_INTF_SEL_MASK | 422 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 423 RK3328_TXCLK_DLY_ENA_GMAC_MASK, 424 RK3328_GMAC_PHY_INTF_SEL_RGMII | 425 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 426 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE); 427 428 rk_clrsetreg(&grf->mac_con[0], 429 RK3328_CLK_RX_DL_CFG_GMAC_MASK | 430 RK3328_CLK_TX_DL_CFG_GMAC_MASK, 431 pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT | 432 pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT); 433 } 434 435 static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 436 { 437 struct rk3368_grf *grf; 438 enum { 439 RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9, 440 RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9), 441 RK3368_RMII_MODE_MASK = BIT(6), 442 RK3368_RMII_MODE = BIT(6), 443 }; 444 enum { 445 RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15), 446 RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 447 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15), 448 RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7), 449 RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 450 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7), 451 RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8, 452 RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 453 RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0, 454 RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 455 }; 456 457 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 458 rk_clrsetreg(&grf->soc_con15, 459 RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK, 460 RK3368_GMAC_PHY_INTF_SEL_RGMII); 461 462 rk_clrsetreg(&grf->soc_con16, 463 RK3368_RXCLK_DLY_ENA_GMAC_MASK | 464 RK3368_TXCLK_DLY_ENA_GMAC_MASK | 465 RK3368_CLK_RX_DL_CFG_GMAC_MASK | 466 RK3368_CLK_TX_DL_CFG_GMAC_MASK, 467 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE | 468 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE | 469 pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT | 470 pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT); 471 } 472 473 static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 474 { 475 struct rk3399_grf_regs *grf; 476 477 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 478 479 rk_clrsetreg(&grf->soc_con5, 480 RK3399_GMAC_PHY_INTF_SEL_MASK, 481 RK3399_GMAC_PHY_INTF_SEL_RGMII); 482 483 rk_clrsetreg(&grf->soc_con6, 484 RK3399_RXCLK_DLY_ENA_GMAC_MASK | 485 RK3399_TXCLK_DLY_ENA_GMAC_MASK | 486 RK3399_CLK_RX_DL_CFG_GMAC_MASK | 487 RK3399_CLK_TX_DL_CFG_GMAC_MASK, 488 RK3399_RXCLK_DLY_ENA_GMAC_ENABLE | 489 RK3399_TXCLK_DLY_ENA_GMAC_ENABLE | 490 pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT | 491 pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT); 492 } 493 494 static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 495 { 496 struct rv1108_grf *grf; 497 498 enum { 499 RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 500 RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4, 501 }; 502 503 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 504 rk_clrsetreg(&grf->gmac_con0, 505 RV1108_GMAC_PHY_INTF_SEL_MASK, 506 RV1108_GMAC_PHY_INTF_SEL_RMII); 507 } 508 509 static int gmac_rockchip_probe(struct udevice *dev) 510 { 511 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 512 struct rk_gmac_ops *ops = 513 (struct rk_gmac_ops *)dev_get_driver_data(dev); 514 struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev); 515 struct eth_pdata *eth_pdata = &dw_pdata->eth_pdata; 516 struct clk clk; 517 ulong rate; 518 int ret; 519 520 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 521 ret = clk_set_defaults(dev); 522 if (ret) 523 debug("%s clk_set_defaults failed %d\n", __func__, ret); 524 525 ret = clk_get_by_index(dev, 0, &clk); 526 if (ret) 527 return ret; 528 529 switch (eth_pdata->phy_interface) { 530 case PHY_INTERFACE_MODE_RGMII: 531 /* 532 * If the gmac clock is from internal pll, need to set and 533 * check the return value for gmac clock at RGMII mode. If 534 * the gmac clock is from external source, the clock rate 535 * is not set, because of it is bypassed. 536 */ 537 if (!pdata->clock_input) { 538 rate = clk_set_rate(&clk, 125000000); 539 if (rate != 125000000) 540 return -EINVAL; 541 } 542 543 /* Set to RGMII mode */ 544 if (ops->set_to_rgmii) 545 ops->set_to_rgmii(pdata); 546 else 547 return -EPERM; 548 549 break; 550 case PHY_INTERFACE_MODE_RMII: 551 /* The commet is the same as RGMII mode */ 552 if (!pdata->clock_input) { 553 rate = clk_set_rate(&clk, 50000000); 554 if (rate != 50000000) 555 return -EINVAL; 556 } 557 558 /* Set to RMII mode */ 559 if (ops->set_to_rmii) 560 ops->set_to_rmii(pdata); 561 else 562 return -EPERM; 563 564 break; 565 default: 566 debug("NO interface defined!\n"); 567 return -ENXIO; 568 } 569 570 return designware_eth_probe(dev); 571 } 572 573 static int gmac_rockchip_eth_start(struct udevice *dev) 574 { 575 struct eth_pdata *pdata = dev_get_platdata(dev); 576 struct dw_eth_dev *priv = dev_get_priv(dev); 577 struct rk_gmac_ops *ops = 578 (struct rk_gmac_ops *)dev_get_driver_data(dev); 579 int ret; 580 581 ret = designware_eth_init(priv, pdata->enetaddr); 582 if (ret) 583 return ret; 584 ret = ops->fix_mac_speed(priv); 585 if (ret) 586 return ret; 587 ret = designware_eth_enable(priv); 588 if (ret) 589 return ret; 590 591 return 0; 592 } 593 594 const struct eth_ops gmac_rockchip_eth_ops = { 595 .start = gmac_rockchip_eth_start, 596 .send = designware_eth_send, 597 .recv = designware_eth_recv, 598 .free_pkt = designware_eth_free_pkt, 599 .stop = designware_eth_stop, 600 .write_hwaddr = designware_eth_write_hwaddr, 601 }; 602 603 const struct rk_gmac_ops rk3228_gmac_ops = { 604 .fix_mac_speed = rk3228_gmac_fix_mac_speed, 605 .set_to_rgmii = rk3228_gmac_set_to_rgmii, 606 }; 607 608 const struct rk_gmac_ops rk3288_gmac_ops = { 609 .fix_mac_speed = rk3288_gmac_fix_mac_speed, 610 .set_to_rgmii = rk3288_gmac_set_to_rgmii, 611 }; 612 613 const struct rk_gmac_ops rk3308_gmac_ops = { 614 .fix_mac_speed = rk3308_gmac_fix_mac_speed, 615 .set_to_rmii = rk3308_gmac_set_to_rmii, 616 }; 617 618 const struct rk_gmac_ops rk3328_gmac_ops = { 619 .fix_mac_speed = rk3328_gmac_fix_mac_speed, 620 .set_to_rgmii = rk3328_gmac_set_to_rgmii, 621 }; 622 623 const struct rk_gmac_ops rk3368_gmac_ops = { 624 .fix_mac_speed = rk3368_gmac_fix_mac_speed, 625 .set_to_rgmii = rk3368_gmac_set_to_rgmii, 626 }; 627 628 const struct rk_gmac_ops rk3399_gmac_ops = { 629 .fix_mac_speed = rk3399_gmac_fix_mac_speed, 630 .set_to_rgmii = rk3399_gmac_set_to_rgmii, 631 }; 632 633 const struct rk_gmac_ops rv1108_gmac_ops = { 634 .fix_mac_speed = rv1108_set_rmii_speed, 635 .set_to_rmii = rv1108_gmac_set_to_rmii, 636 }; 637 638 static const struct udevice_id rockchip_gmac_ids[] = { 639 { .compatible = "rockchip,rk3228-gmac", 640 .data = (ulong)&rk3228_gmac_ops }, 641 { .compatible = "rockchip,rk3288-gmac", 642 .data = (ulong)&rk3288_gmac_ops }, 643 { .compatible = "rockchip,rk3308-mac", 644 .data = (ulong)&rk3308_gmac_ops }, 645 { .compatible = "rockchip,rk3328-gmac", 646 .data = (ulong)&rk3328_gmac_ops }, 647 { .compatible = "rockchip,rk3368-gmac", 648 .data = (ulong)&rk3368_gmac_ops }, 649 { .compatible = "rockchip,rk3399-gmac", 650 .data = (ulong)&rk3399_gmac_ops }, 651 { .compatible = "rockchip,rv1108-gmac", 652 .data = (ulong)&rv1108_gmac_ops }, 653 { } 654 }; 655 656 U_BOOT_DRIVER(eth_gmac_rockchip) = { 657 .name = "gmac_rockchip", 658 .id = UCLASS_ETH, 659 .of_match = rockchip_gmac_ids, 660 .ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata, 661 .probe = gmac_rockchip_probe, 662 .ops = &gmac_rockchip_eth_ops, 663 .priv_auto_alloc_size = sizeof(struct dw_eth_dev), 664 .platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata), 665 .flags = DM_FLAG_ALLOC_PRIV_DMA, 666 }; 667