1 /* 2 * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Rockchip GMAC ethernet IP driver for U-Boot 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <clk.h> 12 #include <misc.h> 13 #include <phy.h> 14 #include <reset.h> 15 #include <syscon.h> 16 #include <asm/io.h> 17 #include <asm/arch/periph.h> 18 #include <asm/arch/clock.h> 19 #include <asm/arch/hardware.h> 20 #ifdef CONFIG_DWC_ETH_QOS 21 #include <asm/arch/grf_rk3568.h> 22 #include <asm/arch/grf_rk3588.h> 23 #include <asm/arch/grf_rv1106.h> 24 #include <asm/arch/grf_rv1126.h> 25 #include "dwc_eth_qos.h" 26 #else 27 #include <asm/arch/grf_px30.h> 28 #include <asm/arch/grf_rk1808.h> 29 #include <asm/arch/grf_rk322x.h> 30 #include <asm/arch/grf_rk3288.h> 31 #include <asm/arch/grf_rk3308.h> 32 #include <asm/arch/grf_rk3328.h> 33 #include <asm/arch/grf_rk3368.h> 34 #include <asm/arch/grf_rk3399.h> 35 #include <asm/arch/grf_rv1108.h> 36 #include "designware.h" 37 #include <dt-bindings/clock/rk3288-cru.h> 38 #endif 39 #include <dm/pinctrl.h> 40 #include <dm/of_access.h> 41 42 DECLARE_GLOBAL_DATA_PTR; 43 44 struct rockchip_eth_dev { 45 #ifdef CONFIG_DWC_ETH_QOS 46 struct eqos_priv eqos; 47 #else 48 struct dw_eth_dev dw; 49 #endif 50 int phy_interface; 51 }; 52 53 /* 54 * Platform data for the gmac 55 * 56 * dw_eth_pdata: Required platform data for designware driver (must be first) 57 */ 58 struct gmac_rockchip_platdata { 59 #ifndef CONFIG_DWC_ETH_QOS 60 struct dw_eth_pdata dw_eth_pdata; 61 #else 62 struct eth_pdata eth_pdata; 63 #endif 64 struct reset_ctl phy_reset; 65 bool integrated_phy; 66 bool clock_input; 67 int phy_interface; 68 int tx_delay; 69 int rx_delay; 70 int bus_id; 71 }; 72 73 struct rk_gmac_ops { 74 #ifdef CONFIG_DWC_ETH_QOS 75 const struct eqos_config config; 76 #endif 77 int (*fix_mac_speed)(struct gmac_rockchip_platdata *pdata, 78 struct rockchip_eth_dev *dev); 79 void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata); 80 void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata); 81 void (*set_clock_selection)(struct gmac_rockchip_platdata *pdata); 82 void (*integrated_phy_powerup)(struct gmac_rockchip_platdata *pdata); 83 }; 84 85 #ifdef CONFIG_DWC_ETH_QOS 86 static const struct eqos_config eqos_rockchip_config = { 87 .reg_access_always_ok = false, 88 .mdio_wait = 10000, 89 .swr_wait = 200, 90 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED, 91 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_100_150, 92 .ops = &eqos_rockchip_ops, 93 }; 94 #endif 95 96 void gmac_set_rgmii(struct udevice *dev, u32 tx_delay, u32 rx_delay) 97 { 98 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 99 struct rk_gmac_ops *ops = 100 (struct rk_gmac_ops *)dev_get_driver_data(dev); 101 102 pdata->tx_delay = tx_delay; 103 pdata->rx_delay = rx_delay; 104 105 ops->set_to_rgmii(pdata); 106 } 107 108 static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) 109 { 110 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 111 struct ofnode_phandle_args args; 112 struct udevice *phydev; 113 const char *string; 114 int ret; 115 116 string = dev_read_string(dev, "clock_in_out"); 117 if (!strcmp(string, "input")) 118 pdata->clock_input = true; 119 else 120 pdata->clock_input = false; 121 122 /* If phy-handle property is passed from DT, use it as the PHY */ 123 ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &args); 124 if (ret) { 125 debug("Cannot get phy phandle: ret=%d\n", ret); 126 pdata->integrated_phy = dev_read_bool(dev, "phy-is-integrated"); 127 } else { 128 debug("Found phy-handle subnode\n"); 129 pdata->integrated_phy = ofnode_read_bool(args.node, 130 "phy-is-integrated"); 131 } 132 133 if (pdata->integrated_phy) { 134 ret = reset_get_by_name(dev, "mac-phy", &pdata->phy_reset); 135 if (ret) { 136 ret = uclass_get_device_by_ofnode(UCLASS_ETH_PHY, args.node, &phydev); 137 if (ret) { 138 debug("Get phydev by ofnode failed: err=%d\n", ret); 139 return ret; 140 } 141 142 ret = reset_get_by_index(phydev, 0, &pdata->phy_reset); 143 if (ret) { 144 debug("No PHY reset control found: ret=%d\n", ret); 145 return ret; 146 } 147 } 148 } 149 150 /* Check the new naming-style first... */ 151 pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT); 152 pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT); 153 154 /* ... and fall back to the old naming style or default, if necessary */ 155 if (pdata->tx_delay == -ENOENT) 156 pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30); 157 if (pdata->rx_delay == -ENOENT) 158 pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10); 159 160 #ifdef CONFIG_DWC_ETH_QOS 161 return 0; 162 #else 163 return designware_eth_ofdata_to_platdata(dev); 164 #endif 165 } 166 167 #ifndef CONFIG_DWC_ETH_QOS 168 static int px30_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 169 struct rockchip_eth_dev *dev) 170 { 171 struct dw_eth_dev *priv = &dev->dw; 172 struct px30_grf *grf; 173 struct clk clk_speed; 174 int speed, ret; 175 enum { 176 PX30_GMAC_SPEED_SHIFT = 0x2, 177 PX30_GMAC_SPEED_MASK = BIT(2), 178 PX30_GMAC_SPEED_10M = 0, 179 PX30_GMAC_SPEED_100M = BIT(2), 180 }; 181 182 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 183 &clk_speed); 184 if (ret) 185 return ret; 186 187 switch (priv->phydev->speed) { 188 case 10: 189 speed = PX30_GMAC_SPEED_10M; 190 ret = clk_set_rate(&clk_speed, 2500000); 191 if (ret) 192 return ret; 193 break; 194 case 100: 195 speed = PX30_GMAC_SPEED_100M; 196 ret = clk_set_rate(&clk_speed, 25000000); 197 if (ret) 198 return ret; 199 break; 200 default: 201 debug("Unknown phy speed: %d\n", priv->phydev->speed); 202 return -EINVAL; 203 } 204 205 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 206 rk_clrsetreg(&grf->mac_con1, PX30_GMAC_SPEED_MASK, speed); 207 208 return 0; 209 } 210 211 static int rk1808_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 212 struct rockchip_eth_dev *dev) 213 { 214 struct dw_eth_dev *priv = &dev->dw; 215 struct clk clk_speed; 216 int ret; 217 218 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 219 &clk_speed); 220 if (ret) 221 return ret; 222 223 switch (priv->phydev->speed) { 224 case 10: 225 ret = clk_set_rate(&clk_speed, 2500000); 226 if (ret) 227 return ret; 228 break; 229 case 100: 230 ret = clk_set_rate(&clk_speed, 25000000); 231 if (ret) 232 return ret; 233 break; 234 case 1000: 235 ret = clk_set_rate(&clk_speed, 125000000); 236 if (ret) 237 return ret; 238 break; 239 default: 240 debug("Unknown phy speed: %d\n", priv->phydev->speed); 241 return -EINVAL; 242 } 243 244 return 0; 245 } 246 247 static int rk3228_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 248 struct rockchip_eth_dev *dev) 249 { 250 struct dw_eth_dev *priv = &dev->dw; 251 struct rk322x_grf *grf; 252 int clk; 253 enum { 254 RK3228_GMAC_CLK_SEL_SHIFT = 8, 255 RK3228_GMAC_CLK_SEL_MASK = GENMASK(9, 8), 256 RK3228_GMAC_CLK_SEL_125M = 0 << 8, 257 RK3228_GMAC_CLK_SEL_25M = 3 << 8, 258 RK3228_GMAC_CLK_SEL_2_5M = 2 << 8, 259 260 RK3228_GMAC_RMII_CLK_MASK = BIT(7), 261 RK3228_GMAC_RMII_CLK_2_5M = 0, 262 RK3228_GMAC_RMII_CLK_25M = BIT(7), 263 264 RK3228_GMAC_RMII_SPEED_MASK = BIT(2), 265 RK3228_GMAC_RMII_SPEED_10 = 0, 266 RK3228_GMAC_RMII_SPEED_100 = BIT(2), 267 }; 268 269 switch (priv->phydev->speed) { 270 case 10: 271 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 272 (RK3228_GMAC_RMII_CLK_2_5M | RK3228_GMAC_RMII_SPEED_10) : 273 RK3228_GMAC_CLK_SEL_2_5M; 274 break; 275 case 100: 276 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 277 (RK3228_GMAC_RMII_CLK_25M | RK3228_GMAC_RMII_SPEED_100) : 278 RK3228_GMAC_CLK_SEL_25M; 279 break; 280 case 1000: 281 clk = RK3228_GMAC_CLK_SEL_125M; 282 break; 283 default: 284 debug("Unknown phy speed: %d\n", priv->phydev->speed); 285 return -EINVAL; 286 } 287 288 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 289 rk_clrsetreg(&grf->mac_con[1], 290 RK3228_GMAC_CLK_SEL_MASK | 291 RK3228_GMAC_RMII_CLK_MASK | 292 RK3228_GMAC_RMII_SPEED_MASK, 293 clk); 294 295 return 0; 296 } 297 298 static int rk3288_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 299 struct rockchip_eth_dev *dev) 300 { 301 struct dw_eth_dev *priv = &dev->dw; 302 struct rk3288_grf *grf; 303 int clk; 304 305 switch (priv->phydev->speed) { 306 case 10: 307 clk = RK3288_GMAC_CLK_SEL_2_5M; 308 break; 309 case 100: 310 clk = RK3288_GMAC_CLK_SEL_25M; 311 break; 312 case 1000: 313 clk = RK3288_GMAC_CLK_SEL_125M; 314 break; 315 default: 316 debug("Unknown phy speed: %d\n", priv->phydev->speed); 317 return -EINVAL; 318 } 319 320 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 321 rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk); 322 323 return 0; 324 } 325 326 static int rk3308_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 327 struct rockchip_eth_dev *dev) 328 { 329 struct dw_eth_dev *priv = &dev->dw; 330 struct rk3308_grf *grf; 331 struct clk clk_speed; 332 int speed, ret; 333 enum { 334 RK3308_GMAC_SPEED_SHIFT = 0x0, 335 RK3308_GMAC_SPEED_MASK = BIT(0), 336 RK3308_GMAC_SPEED_10M = 0, 337 RK3308_GMAC_SPEED_100M = BIT(0), 338 }; 339 340 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 341 &clk_speed); 342 if (ret) 343 return ret; 344 345 switch (priv->phydev->speed) { 346 case 10: 347 speed = RK3308_GMAC_SPEED_10M; 348 ret = clk_set_rate(&clk_speed, 2500000); 349 if (ret) 350 return ret; 351 break; 352 case 100: 353 speed = RK3308_GMAC_SPEED_100M; 354 ret = clk_set_rate(&clk_speed, 25000000); 355 if (ret) 356 return ret; 357 break; 358 default: 359 debug("Unknown phy speed: %d\n", priv->phydev->speed); 360 return -EINVAL; 361 } 362 363 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 364 rk_clrsetreg(&grf->mac_con0, RK3308_GMAC_SPEED_MASK, speed); 365 366 return 0; 367 } 368 369 static int rk3328_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 370 struct rockchip_eth_dev *dev) 371 { 372 struct dw_eth_dev *priv = &dev->dw; 373 struct rk3328_grf_regs *grf; 374 int clk; 375 enum { 376 RK3328_GMAC_CLK_SEL_SHIFT = 11, 377 RK3328_GMAC_CLK_SEL_MASK = GENMASK(12, 11), 378 RK3328_GMAC_CLK_SEL_125M = 0 << 11, 379 RK3328_GMAC_CLK_SEL_25M = 3 << 11, 380 RK3328_GMAC_CLK_SEL_2_5M = 2 << 11, 381 382 RK3328_GMAC_RMII_CLK_MASK = BIT(7), 383 RK3328_GMAC_RMII_CLK_2_5M = 0, 384 RK3328_GMAC_RMII_CLK_25M = BIT(7), 385 386 RK3328_GMAC_RMII_SPEED_MASK = BIT(2), 387 RK3328_GMAC_RMII_SPEED_10 = 0, 388 RK3328_GMAC_RMII_SPEED_100 = BIT(2), 389 }; 390 391 switch (priv->phydev->speed) { 392 case 10: 393 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 394 (RK3328_GMAC_RMII_CLK_2_5M | RK3328_GMAC_RMII_SPEED_10) : 395 RK3328_GMAC_CLK_SEL_2_5M; 396 break; 397 case 100: 398 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 399 (RK3328_GMAC_RMII_CLK_25M | RK3328_GMAC_RMII_SPEED_100) : 400 RK3328_GMAC_CLK_SEL_25M; 401 break; 402 case 1000: 403 clk = RK3328_GMAC_CLK_SEL_125M; 404 break; 405 default: 406 debug("Unknown phy speed: %d\n", priv->phydev->speed); 407 return -EINVAL; 408 } 409 410 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 411 rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1], 412 RK3328_GMAC_CLK_SEL_MASK | 413 RK3328_GMAC_RMII_CLK_MASK | 414 RK3328_GMAC_RMII_SPEED_MASK, 415 clk); 416 417 return 0; 418 } 419 420 static int rk3368_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 421 struct rockchip_eth_dev *dev) 422 { 423 struct dw_eth_dev *priv = &dev->dw; 424 struct rk3368_grf *grf; 425 int clk; 426 enum { 427 RK3368_GMAC_CLK_SEL_2_5M = 2 << 4, 428 RK3368_GMAC_CLK_SEL_25M = 3 << 4, 429 RK3368_GMAC_CLK_SEL_125M = 0 << 4, 430 RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4), 431 }; 432 433 switch (priv->phydev->speed) { 434 case 10: 435 clk = RK3368_GMAC_CLK_SEL_2_5M; 436 break; 437 case 100: 438 clk = RK3368_GMAC_CLK_SEL_25M; 439 break; 440 case 1000: 441 clk = RK3368_GMAC_CLK_SEL_125M; 442 break; 443 default: 444 debug("Unknown phy speed: %d\n", priv->phydev->speed); 445 return -EINVAL; 446 } 447 448 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 449 rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk); 450 451 return 0; 452 } 453 454 static int rk3399_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 455 struct rockchip_eth_dev *dev) 456 { 457 struct dw_eth_dev *priv = &dev->dw; 458 struct rk3399_grf_regs *grf; 459 int clk; 460 461 switch (priv->phydev->speed) { 462 case 10: 463 clk = RK3399_GMAC_CLK_SEL_2_5M; 464 break; 465 case 100: 466 clk = RK3399_GMAC_CLK_SEL_25M; 467 break; 468 case 1000: 469 clk = RK3399_GMAC_CLK_SEL_125M; 470 break; 471 default: 472 debug("Unknown phy speed: %d\n", priv->phydev->speed); 473 return -EINVAL; 474 } 475 476 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 477 rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk); 478 479 return 0; 480 } 481 482 static int rv1108_set_rmii_speed(struct gmac_rockchip_platdata *pdata, 483 struct rockchip_eth_dev *dev) 484 { 485 struct dw_eth_dev *priv = &dev->dw; 486 struct rv1108_grf *grf; 487 int clk, speed; 488 enum { 489 RV1108_GMAC_SPEED_MASK = BIT(2), 490 RV1108_GMAC_SPEED_10M = 0 << 2, 491 RV1108_GMAC_SPEED_100M = 1 << 2, 492 RV1108_GMAC_CLK_SEL_MASK = BIT(7), 493 RV1108_GMAC_CLK_SEL_2_5M = 0 << 7, 494 RV1108_GMAC_CLK_SEL_25M = 1 << 7, 495 }; 496 497 switch (priv->phydev->speed) { 498 case 10: 499 clk = RV1108_GMAC_CLK_SEL_2_5M; 500 speed = RV1108_GMAC_SPEED_10M; 501 break; 502 case 100: 503 clk = RV1108_GMAC_CLK_SEL_25M; 504 speed = RV1108_GMAC_SPEED_100M; 505 break; 506 default: 507 debug("Unknown phy speed: %d\n", priv->phydev->speed); 508 return -EINVAL; 509 } 510 511 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 512 rk_clrsetreg(&grf->gmac_con0, 513 RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK, 514 clk | speed); 515 516 return 0; 517 } 518 #else 519 static int rk3588_set_rgmii_speed(struct gmac_rockchip_platdata *pdata, 520 struct rockchip_eth_dev *dev) 521 { 522 struct eqos_priv *priv = &dev->eqos; 523 struct rk3588_php_grf *php_grf; 524 unsigned int div, div_mask; 525 526 enum { 527 RK3588_GMAC_CLK_RGMII_DIV_SHIFT = 2, 528 RK3588_GMAC_CLK_RGMII_DIV_MASK = GENMASK(3, 2), 529 RK3588_GMAC_CLK_RGMII_DIV1 = 0, 530 RK3588_GMAC_CLK_RGMII_DIV5 = GENMASK(3, 2), 531 RK3588_GMAC_CLK_RGMII_DIV50 = BIT(3), 532 RK3588_GMAC_CLK_RMII_DIV2 = BIT(2), 533 RK3588_GMAC_CLK_RMII_DIV20 = 0, 534 RK3588_GMAC1_ID_SHIFT = 5, 535 }; 536 537 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 538 539 switch (priv->phy->speed) { 540 case 10: 541 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) 542 div = RK3588_GMAC_CLK_RMII_DIV20; 543 else 544 div = RK3588_GMAC_CLK_RGMII_DIV50; 545 break; 546 case 100: 547 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) 548 div = RK3588_GMAC_CLK_RMII_DIV2; 549 else 550 div = RK3588_GMAC_CLK_RGMII_DIV5; 551 break; 552 case 1000: 553 if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII) 554 div = RK3588_GMAC_CLK_RGMII_DIV1; 555 else 556 return -EINVAL; 557 break; 558 default: 559 debug("Unknown phy speed: %d\n", priv->phy->speed); 560 return -EINVAL; 561 } 562 563 if (pdata->bus_id == 1) { 564 div <<= 5; 565 div_mask = RK3588_GMAC_CLK_RGMII_DIV_MASK << 5; 566 } 567 568 div <<= pdata->bus_id ? RK3588_GMAC1_ID_SHIFT : 0; 569 div_mask = pdata->bus_id ? (RK3588_GMAC_CLK_RGMII_DIV_MASK << 5) : 570 RK3588_GMAC_CLK_RGMII_DIV_MASK; 571 572 rk_clrsetreg(&php_grf->clk_con1, div_mask, div); 573 574 return 0; 575 } 576 577 static int rv1106_set_rmii_speed(struct gmac_rockchip_platdata *pdata, 578 struct rockchip_eth_dev *dev) 579 { 580 struct eqos_priv *priv = &dev->eqos; 581 struct rv1106_grf *grf; 582 unsigned int div; 583 584 enum { 585 RV1106_GMAC_CLK_RMII_DIV_SHIFT = 2, 586 RV1106_GMAC_CLK_RMII_DIV_MASK = GENMASK(3, 2), 587 RV1106_GMAC_CLK_RMII_DIV2 = BIT(2), 588 RV1106_GMAC_CLK_RMII_DIV20 = 0, 589 }; 590 591 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 592 593 switch (priv->phy->speed) { 594 case 10: 595 div = RV1106_GMAC_CLK_RMII_DIV20; 596 break; 597 case 100: 598 div = RV1106_GMAC_CLK_RMII_DIV2; 599 break; 600 default: 601 debug("Unknown phy speed: %d\n", priv->phy->speed); 602 return -EINVAL; 603 } 604 605 rk_clrsetreg(&grf->gmac_clk_con, RV1106_GMAC_CLK_RMII_DIV_MASK, div); 606 607 return 0; 608 } 609 610 static int rv1126_set_rgmii_speed(struct gmac_rockchip_platdata *pdata, 611 struct rockchip_eth_dev *dev) 612 { 613 struct eqos_priv *priv = &dev->eqos; 614 struct clk clk_speed; 615 int ret; 616 617 ret = clk_get_by_name(priv->phy->dev, "clk_mac_speed", 618 &clk_speed); 619 if (ret) { 620 printf("%s can't get clk_mac_speed clock (ret=%d):\n", 621 __func__, ret); 622 return ret; 623 } 624 625 switch ( priv->phy->speed) { 626 case 10: 627 ret = clk_set_rate(&clk_speed, 2500000); 628 if (ret) 629 return ret; 630 break; 631 case 100: 632 ret = clk_set_rate(&clk_speed, 25000000); 633 if (ret) 634 return ret; 635 break; 636 case 1000: 637 ret = clk_set_rate(&clk_speed, 125000000); 638 if (ret) 639 return ret; 640 break; 641 default: 642 debug("Unknown phy speed: %d\n", priv->phy->speed); 643 return -EINVAL; 644 } 645 646 return 0; 647 } 648 #endif 649 650 #ifndef CONFIG_DWC_ETH_QOS 651 static void px30_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 652 { 653 struct px30_grf *grf; 654 enum { 655 px30_GMAC_PHY_INTF_SEL_SHIFT = 4, 656 px30_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 6), 657 px30_GMAC_PHY_INTF_SEL_RMII = BIT(6), 658 }; 659 660 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 661 662 rk_clrsetreg(&grf->mac_con1, 663 px30_GMAC_PHY_INTF_SEL_MASK, 664 px30_GMAC_PHY_INTF_SEL_RMII); 665 } 666 667 static void rk1808_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 668 { 669 struct rk1808_grf *grf; 670 enum { 671 RK1808_GMAC_PHY_INTF_SEL_SHIFT = 4, 672 RK1808_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 673 RK1808_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 674 675 RK1808_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 676 RK1808_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 677 RK1808_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 678 679 RK1808_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 680 RK1808_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 681 RK1808_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 682 }; 683 enum { 684 RK1808_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 685 RK1808_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 7), 686 687 RK1808_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 688 RK1808_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 689 }; 690 691 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 692 rk_clrsetreg(&grf->mac_con1, 693 RK1808_GMAC_PHY_INTF_SEL_MASK | 694 RK1808_RXCLK_DLY_ENA_GMAC_MASK | 695 RK1808_TXCLK_DLY_ENA_GMAC_MASK, 696 RK1808_GMAC_PHY_INTF_SEL_RGMII | 697 RK1808_RXCLK_DLY_ENA_GMAC_ENABLE | 698 RK1808_TXCLK_DLY_ENA_GMAC_ENABLE); 699 700 rk_clrsetreg(&grf->mac_con0, 701 RK1808_CLK_RX_DL_CFG_GMAC_MASK | 702 RK1808_CLK_TX_DL_CFG_GMAC_MASK, 703 (pdata->rx_delay << RK1808_CLK_RX_DL_CFG_GMAC_SHIFT) | 704 (pdata->tx_delay << RK1808_CLK_TX_DL_CFG_GMAC_SHIFT)); 705 } 706 707 static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 708 { 709 struct rk322x_grf *grf; 710 enum { 711 RK3228_RMII_MODE_SHIFT = 10, 712 RK3228_RMII_MODE_MASK = BIT(10), 713 714 RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4, 715 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 716 RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 717 718 RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 719 RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 720 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 721 722 RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 723 RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 724 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 725 }; 726 enum { 727 RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 728 RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 729 730 RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 731 RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 732 }; 733 734 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 735 rk_clrsetreg(&grf->mac_con[1], 736 RK3228_RMII_MODE_MASK | 737 RK3228_GMAC_PHY_INTF_SEL_MASK | 738 RK3228_RXCLK_DLY_ENA_GMAC_MASK | 739 RK3228_TXCLK_DLY_ENA_GMAC_MASK, 740 RK3228_GMAC_PHY_INTF_SEL_RGMII | 741 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE | 742 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE); 743 744 rk_clrsetreg(&grf->mac_con[0], 745 RK3228_CLK_RX_DL_CFG_GMAC_MASK | 746 RK3228_CLK_TX_DL_CFG_GMAC_MASK, 747 pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT | 748 pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT); 749 } 750 751 static void rk3228_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 752 { 753 struct rk322x_grf *grf; 754 enum { 755 RK3228_GRF_CON_RMII_MODE_MASK = BIT(11), 756 RK3228_GRF_CON_RMII_MODE_SEL = BIT(11), 757 RK3228_RMII_MODE_MASK = BIT(10), 758 RK3228_RMII_MODE_SEL = BIT(10), 759 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 760 RK3228_GMAC_PHY_INTF_SEL_RMII = BIT(6), 761 }; 762 763 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 764 rk_clrsetreg(&grf->mac_con[1], 765 RK3228_GRF_CON_RMII_MODE_MASK | 766 RK3228_RMII_MODE_MASK | 767 RK3228_GMAC_PHY_INTF_SEL_MASK, 768 RK3228_GRF_CON_RMII_MODE_SEL | 769 RK3228_RMII_MODE_SEL | 770 RK3228_GMAC_PHY_INTF_SEL_RMII); 771 } 772 773 static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 774 { 775 struct rk3288_grf *grf; 776 777 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 778 rk_clrsetreg(&grf->soc_con1, 779 RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK, 780 RK3288_GMAC_PHY_INTF_SEL_RGMII); 781 782 rk_clrsetreg(&grf->soc_con3, 783 RK3288_RXCLK_DLY_ENA_GMAC_MASK | 784 RK3288_TXCLK_DLY_ENA_GMAC_MASK | 785 RK3288_CLK_RX_DL_CFG_GMAC_MASK | 786 RK3288_CLK_TX_DL_CFG_GMAC_MASK, 787 RK3288_RXCLK_DLY_ENA_GMAC_ENABLE | 788 RK3288_TXCLK_DLY_ENA_GMAC_ENABLE | 789 pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT | 790 pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT); 791 } 792 793 static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 794 { 795 struct rk3308_grf *grf; 796 enum { 797 RK3308_GMAC_PHY_INTF_SEL_SHIFT = 2, 798 RK3308_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 2), 799 RK3308_GMAC_PHY_INTF_SEL_RMII = BIT(4), 800 }; 801 802 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 803 804 rk_clrsetreg(&grf->mac_con0, 805 RK3308_GMAC_PHY_INTF_SEL_MASK, 806 RK3308_GMAC_PHY_INTF_SEL_RMII); 807 } 808 809 static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 810 { 811 struct rk3328_grf_regs *grf; 812 enum { 813 RK3328_RMII_MODE_SHIFT = 9, 814 RK3328_RMII_MODE_MASK = BIT(9), 815 816 RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4, 817 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 818 RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 819 820 RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 821 RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 822 RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 823 824 RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 825 RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 826 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 827 }; 828 enum { 829 RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 830 RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 831 832 RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 833 RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 834 }; 835 836 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 837 rk_clrsetreg(&grf->mac_con[1], 838 RK3328_RMII_MODE_MASK | 839 RK3328_GMAC_PHY_INTF_SEL_MASK | 840 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 841 RK3328_TXCLK_DLY_ENA_GMAC_MASK, 842 RK3328_GMAC_PHY_INTF_SEL_RGMII | 843 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 844 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE); 845 846 rk_clrsetreg(&grf->mac_con[0], 847 RK3328_CLK_RX_DL_CFG_GMAC_MASK | 848 RK3328_CLK_TX_DL_CFG_GMAC_MASK, 849 pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT | 850 pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT); 851 } 852 853 static void rk3328_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 854 { 855 struct rk3328_grf_regs *grf; 856 enum { 857 RK3328_RMII_MODE_MASK = BIT(9), 858 RK3328_RMII_MODE = BIT(9), 859 860 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 861 RK3328_GMAC_PHY_INTF_SEL_RMII = BIT(6), 862 }; 863 864 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 865 rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1], 866 RK3328_RMII_MODE_MASK | 867 RK3328_GMAC_PHY_INTF_SEL_MASK, 868 RK3328_GMAC_PHY_INTF_SEL_RMII | 869 RK3328_RMII_MODE); 870 } 871 872 static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 873 { 874 struct rk3368_grf *grf; 875 enum { 876 RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9, 877 RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9), 878 RK3368_RMII_MODE_MASK = BIT(6), 879 RK3368_RMII_MODE = BIT(6), 880 }; 881 enum { 882 RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15), 883 RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 884 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15), 885 RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7), 886 RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 887 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7), 888 RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8, 889 RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 890 RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0, 891 RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 892 }; 893 894 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 895 rk_clrsetreg(&grf->soc_con15, 896 RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK, 897 RK3368_GMAC_PHY_INTF_SEL_RGMII); 898 899 rk_clrsetreg(&grf->soc_con16, 900 RK3368_RXCLK_DLY_ENA_GMAC_MASK | 901 RK3368_TXCLK_DLY_ENA_GMAC_MASK | 902 RK3368_CLK_RX_DL_CFG_GMAC_MASK | 903 RK3368_CLK_TX_DL_CFG_GMAC_MASK, 904 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE | 905 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE | 906 (pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT) | 907 (pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT)); 908 } 909 910 static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 911 { 912 struct rk3399_grf_regs *grf; 913 914 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 915 916 rk_clrsetreg(&grf->soc_con5, 917 RK3399_GMAC_PHY_INTF_SEL_MASK, 918 RK3399_GMAC_PHY_INTF_SEL_RGMII); 919 920 rk_clrsetreg(&grf->soc_con6, 921 RK3399_RXCLK_DLY_ENA_GMAC_MASK | 922 RK3399_TXCLK_DLY_ENA_GMAC_MASK | 923 RK3399_CLK_RX_DL_CFG_GMAC_MASK | 924 RK3399_CLK_TX_DL_CFG_GMAC_MASK, 925 RK3399_RXCLK_DLY_ENA_GMAC_ENABLE | 926 RK3399_TXCLK_DLY_ENA_GMAC_ENABLE | 927 (pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT) | 928 (pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT)); 929 } 930 931 static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 932 { 933 struct rv1108_grf *grf; 934 935 enum { 936 RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 937 RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4, 938 }; 939 940 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 941 rk_clrsetreg(&grf->gmac_con0, 942 RV1108_GMAC_PHY_INTF_SEL_MASK, 943 RV1108_GMAC_PHY_INTF_SEL_RMII); 944 } 945 946 static void rk3228_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 947 { 948 struct rk322x_grf *grf; 949 enum { 950 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK = BIT(15), 951 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY = BIT(15), 952 }; 953 enum { 954 RK3228_MACPHY_CFG_CLK_50M_MASK = BIT(14), 955 RK3228_MACPHY_CFG_CLK_50M = BIT(14), 956 957 RK3228_MACPHY_RMII_MODE_MASK = GENMASK(7, 6), 958 RK3228_MACPHY_RMII_MODE = BIT(6), 959 960 RK3228_MACPHY_ENABLE_MASK = BIT(0), 961 RK3228_MACPHY_DISENABLE = 0, 962 RK3228_MACPHY_ENABLE = BIT(0), 963 }; 964 enum { 965 RK3228_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0), 966 RK3228_RK_GRF_CON2_MACPHY_ID = 0x1234, 967 }; 968 enum { 969 RK3228_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0), 970 RK3228_RK_GRF_CON3_MACPHY_ID = 0x35, 971 }; 972 973 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 974 rk_clrsetreg(&grf->con_iomux, 975 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK, 976 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY); 977 978 rk_clrsetreg(&grf->macphy_con[2], 979 RK3228_RK_GRF_CON2_MACPHY_ID_MASK, 980 RK3228_RK_GRF_CON2_MACPHY_ID); 981 982 rk_clrsetreg(&grf->macphy_con[3], 983 RK3228_RK_GRF_CON3_MACPHY_ID_MASK, 984 RK3228_RK_GRF_CON3_MACPHY_ID); 985 986 /* disabled before trying to reset it &*/ 987 rk_clrsetreg(&grf->macphy_con[0], 988 RK3228_MACPHY_CFG_CLK_50M_MASK | 989 RK3228_MACPHY_RMII_MODE_MASK | 990 RK3228_MACPHY_ENABLE_MASK, 991 RK3228_MACPHY_CFG_CLK_50M | 992 RK3228_MACPHY_RMII_MODE | 993 RK3228_MACPHY_DISENABLE); 994 995 reset_assert(&pdata->phy_reset); 996 udelay(10); 997 reset_deassert(&pdata->phy_reset); 998 udelay(10); 999 1000 rk_clrsetreg(&grf->macphy_con[0], 1001 RK3228_MACPHY_ENABLE_MASK, 1002 RK3228_MACPHY_ENABLE); 1003 udelay(30 * 1000); 1004 } 1005 1006 static void rk3328_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 1007 { 1008 struct rk3328_grf_regs *grf; 1009 enum { 1010 RK3328_GRF_CON_RMII_MODE_MASK = BIT(9), 1011 RK3328_GRF_CON_RMII_MODE = BIT(9), 1012 }; 1013 enum { 1014 RK3328_MACPHY_CFG_CLK_50M_MASK = BIT(14), 1015 RK3328_MACPHY_CFG_CLK_50M = BIT(14), 1016 1017 RK3328_MACPHY_RMII_MODE_MASK = GENMASK(7, 6), 1018 RK3328_MACPHY_RMII_MODE = BIT(6), 1019 1020 RK3328_MACPHY_ENABLE_MASK = BIT(0), 1021 RK3328_MACPHY_DISENABLE = 0, 1022 RK3328_MACPHY_ENABLE = BIT(0), 1023 }; 1024 enum { 1025 RK3328_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0), 1026 RK3328_RK_GRF_CON2_MACPHY_ID = 0x1234, 1027 }; 1028 enum { 1029 RK3328_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0), 1030 RK3328_RK_GRF_CON3_MACPHY_ID = 0x35, 1031 }; 1032 1033 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1034 rk_clrsetreg(&grf->macphy_con[1], 1035 RK3328_GRF_CON_RMII_MODE_MASK, 1036 RK3328_GRF_CON_RMII_MODE); 1037 1038 rk_clrsetreg(&grf->macphy_con[2], 1039 RK3328_RK_GRF_CON2_MACPHY_ID_MASK, 1040 RK3328_RK_GRF_CON2_MACPHY_ID); 1041 1042 rk_clrsetreg(&grf->macphy_con[3], 1043 RK3328_RK_GRF_CON3_MACPHY_ID_MASK, 1044 RK3328_RK_GRF_CON3_MACPHY_ID); 1045 1046 /* disabled before trying to reset it &*/ 1047 rk_clrsetreg(&grf->macphy_con[0], 1048 RK3328_MACPHY_CFG_CLK_50M_MASK | 1049 RK3328_MACPHY_RMII_MODE_MASK | 1050 RK3328_MACPHY_ENABLE_MASK, 1051 RK3328_MACPHY_CFG_CLK_50M | 1052 RK3328_MACPHY_RMII_MODE | 1053 RK3328_MACPHY_DISENABLE); 1054 1055 reset_assert(&pdata->phy_reset); 1056 udelay(10); 1057 reset_deassert(&pdata->phy_reset); 1058 udelay(10); 1059 1060 rk_clrsetreg(&grf->macphy_con[0], 1061 RK3328_MACPHY_ENABLE_MASK, 1062 RK3328_MACPHY_ENABLE); 1063 udelay(30 * 1000); 1064 } 1065 1066 #else 1067 static void rk3568_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1068 { 1069 struct rk3568_grf *grf; 1070 void *con1; 1071 1072 enum { 1073 RK3568_GMAC_PHY_INTF_SEL_SHIFT = 4, 1074 RK3568_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1075 RK3568_GMAC_PHY_INTF_SEL_RMII = BIT(6), 1076 }; 1077 1078 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1079 1080 if (pdata->bus_id == 1) 1081 con1 = &grf->mac1_con1; 1082 else 1083 con1 = &grf->mac0_con1; 1084 1085 rk_clrsetreg(con1, 1086 RK3568_GMAC_PHY_INTF_SEL_MASK, 1087 RK3568_GMAC_PHY_INTF_SEL_RMII); 1088 } 1089 1090 static void rk3568_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1091 { 1092 struct rk3568_grf *grf; 1093 void *con0, *con1; 1094 1095 enum { 1096 RK3568_GMAC_PHY_INTF_SEL_SHIFT = 4, 1097 RK3568_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1098 RK3568_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 1099 1100 RK3568_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 1101 RK3568_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 1102 RK3568_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 1103 1104 RK3568_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 1105 RK3568_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 1106 RK3568_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 1107 }; 1108 1109 enum { 1110 RK3568_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1111 RK3568_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 8), 1112 1113 RK3568_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1114 RK3568_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 1115 }; 1116 1117 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1118 1119 if (pdata->bus_id == 1) { 1120 con0 = &grf->mac1_con0; 1121 con1 = &grf->mac1_con1; 1122 } else { 1123 con0 = &grf->mac0_con0; 1124 con1 = &grf->mac0_con1; 1125 } 1126 1127 rk_clrsetreg(con0, 1128 RK3568_CLK_RX_DL_CFG_GMAC_MASK | 1129 RK3568_CLK_TX_DL_CFG_GMAC_MASK, 1130 (pdata->rx_delay << RK3568_CLK_RX_DL_CFG_GMAC_SHIFT) | 1131 (pdata->tx_delay << RK3568_CLK_TX_DL_CFG_GMAC_SHIFT)); 1132 1133 rk_clrsetreg(con1, 1134 RK3568_TXCLK_DLY_ENA_GMAC_MASK | 1135 RK3568_RXCLK_DLY_ENA_GMAC_MASK | 1136 RK3568_GMAC_PHY_INTF_SEL_MASK, 1137 RK3568_TXCLK_DLY_ENA_GMAC_ENABLE | 1138 RK3568_RXCLK_DLY_ENA_GMAC_ENABLE | 1139 RK3568_GMAC_PHY_INTF_SEL_RGMII); 1140 } 1141 1142 static void rk3588_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1143 { 1144 unsigned int intf_sel, intf_sel_mask; 1145 unsigned int clk_mode, clk_mode_mask; 1146 struct rk3588_php_grf *php_grf; 1147 1148 enum { 1149 RK3588_GMAC_PHY_INTF_SEL_SHIFT = 3, 1150 RK3588_GMAC_PHY_INTF_SEL_MASK = GENMASK(5, 3), 1151 RK3588_GMAC_PHY_INTF_SEL_RMII = BIT(5), 1152 }; 1153 1154 enum { 1155 RK3588_GMAC_CLK_RMII_MODE_SHIFT = 0x0, 1156 RK3588_GMAC_CLK_RMII_MODE_MASK = BIT(0), 1157 RK3588_GMAC_CLK_RMII_MODE = 0x1, 1158 }; 1159 1160 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 1161 1162 if (pdata->bus_id == 1) { 1163 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RMII << 6; 1164 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK << 6; 1165 clk_mode = RK3588_GMAC_CLK_RMII_MODE << 5; 1166 clk_mode_mask = RK3588_GMAC_CLK_RMII_MODE_MASK << 5; 1167 } else { 1168 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RMII; 1169 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK; 1170 clk_mode = RK3588_GMAC_CLK_RMII_MODE; 1171 clk_mode_mask = RK3588_GMAC_CLK_RMII_MODE_MASK; 1172 } 1173 1174 rk_clrsetreg(&php_grf->gmac_con0, intf_sel_mask, intf_sel); 1175 rk_clrsetreg(&php_grf->clk_con1, clk_mode_mask, clk_mode); 1176 } 1177 1178 static void rk3588_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1179 { 1180 unsigned int rx_enable, rx_enable_mask, tx_enable, tx_enable_mask; 1181 unsigned int intf_sel, intf_sel_mask; 1182 unsigned int clk_mode, clk_mode_mask; 1183 unsigned int rx_delay; 1184 struct rk3588_php_grf *php_grf; 1185 struct rk3588_sys_grf *grf; 1186 void *offset_con; 1187 1188 enum { 1189 RK3588_GMAC_PHY_INTF_SEL_SHIFT = 3, 1190 RK3588_GMAC_PHY_INTF_SEL_MASK = GENMASK(5, 3), 1191 RK3588_GMAC_PHY_INTF_SEL_RGMII = BIT(3), 1192 1193 RK3588_RXCLK_DLY_ENA_GMAC_MASK = BIT(3), 1194 RK3588_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 1195 RK3588_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(3), 1196 1197 RK3588_TXCLK_DLY_ENA_GMAC_MASK = BIT(2), 1198 RK3588_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 1199 RK3588_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(2), 1200 }; 1201 1202 enum { 1203 RK3588_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1204 RK3588_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 8), 1205 1206 RK3588_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1207 RK3588_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 1208 }; 1209 1210 enum { 1211 RK3588_GMAC_CLK_RGMII_MODE_SHIFT = 0x0, 1212 RK3588_GMAC_CLK_RGMII_MODE_MASK = BIT(0), 1213 RK3588_GMAC_CLK_RGMII_MODE = 0x0, 1214 }; 1215 1216 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1217 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 1218 1219 if (pdata->rx_delay < 0) { 1220 rx_enable = RK3588_RXCLK_DLY_ENA_GMAC_DISABLE; 1221 rx_delay = 0; 1222 } else { 1223 rx_enable = RK3588_RXCLK_DLY_ENA_GMAC_ENABLE; 1224 rx_delay = pdata->rx_delay << RK3588_CLK_RX_DL_CFG_GMAC_SHIFT; 1225 } 1226 1227 if (pdata->bus_id == 1) { 1228 offset_con = &grf->soc_con9; 1229 rx_enable = rx_delay << 2; 1230 rx_enable_mask = RK3588_RXCLK_DLY_ENA_GMAC_MASK << 2; 1231 tx_enable = RK3588_TXCLK_DLY_ENA_GMAC_ENABLE << 2; 1232 tx_enable_mask = RK3588_TXCLK_DLY_ENA_GMAC_MASK << 2; 1233 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RGMII << 6; 1234 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK << 6; 1235 clk_mode = RK3588_GMAC_CLK_RGMII_MODE << 5; 1236 clk_mode_mask = RK3588_GMAC_CLK_RGMII_MODE_MASK << 5; 1237 } else { 1238 offset_con = &grf->soc_con8; 1239 rx_enable_mask = RK3588_RXCLK_DLY_ENA_GMAC_MASK; 1240 tx_enable = RK3588_TXCLK_DLY_ENA_GMAC_ENABLE; 1241 tx_enable_mask = RK3588_TXCLK_DLY_ENA_GMAC_MASK; 1242 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RGMII; 1243 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK; 1244 clk_mode = RK3588_GMAC_CLK_RGMII_MODE; 1245 clk_mode_mask = RK3588_GMAC_CLK_RGMII_MODE_MASK; 1246 } 1247 1248 rk_clrsetreg(offset_con, 1249 RK3588_CLK_TX_DL_CFG_GMAC_MASK | 1250 RK3588_CLK_RX_DL_CFG_GMAC_MASK, 1251 (pdata->tx_delay << RK3588_CLK_TX_DL_CFG_GMAC_SHIFT) | 1252 rx_delay); 1253 1254 rk_clrsetreg(&grf->soc_con7, tx_enable_mask | rx_enable_mask, 1255 tx_enable | rx_enable); 1256 1257 rk_clrsetreg(&php_grf->gmac_con0, intf_sel_mask, intf_sel); 1258 rk_clrsetreg(&php_grf->clk_con1, clk_mode_mask, clk_mode); 1259 } 1260 1261 static void rv1106_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 1262 { 1263 struct rv1106_grf *grf; 1264 unsigned char bgs[1] = {0}; 1265 1266 enum { 1267 RV1106_VOGRF_GMAC_CLK_RMII_MODE_MASK = BIT(0), 1268 RV1106_VOGRF_GMAC_CLK_RMII_MODE = BIT(0), 1269 }; 1270 1271 enum { 1272 RV1106_MACPHY_ENABLE_MASK = BIT(1), 1273 RV1106_MACPHY_DISENABLE = BIT(1), 1274 RV1106_MACPHY_ENABLE = 0, 1275 RV1106_MACPHY_XMII_SEL_MASK = GENMASK(6, 5), 1276 RV1106_MACPHY_XMII_SEL = BIT(6), 1277 RV1106_MACPHY_24M_CLK_SEL_MASK = GENMASK(9, 7), 1278 RV1106_MACPHY_24M_CLK_SEL_24M = (BIT(8) | BIT(9)), 1279 RV1106_MACPHY_PHY_ID_MASK = GENMASK(14, 10), 1280 RV1106_MACPHY_PHY_ID = BIT(11), 1281 }; 1282 1283 enum { 1284 RV1106_MACPHY_BGS_MASK = GENMASK(3, 0), 1285 RV1106_MACPHY_BGS = BIT(2), 1286 }; 1287 1288 #if defined(CONFIG_ROCKCHIP_EFUSE) || defined(CONFIG_ROCKCHIP_OTP) 1289 struct udevice *dev; 1290 u32 regs[2] = {0}; 1291 ofnode node; 1292 int ret = 0; 1293 1294 /* retrieve the device */ 1295 if (IS_ENABLED(CONFIG_ROCKCHIP_EFUSE)) 1296 ret = uclass_get_device_by_driver(UCLASS_MISC, 1297 DM_GET_DRIVER(rockchip_efuse), 1298 &dev); 1299 else 1300 ret = uclass_get_device_by_driver(UCLASS_MISC, 1301 DM_GET_DRIVER(rockchip_otp), 1302 &dev); 1303 if (!ret) { 1304 node = dev_read_subnode(dev, "macphy-bgs"); 1305 if (ofnode_valid(node)) { 1306 if (!ofnode_read_u32_array(node, "reg", regs, 2)) { 1307 /* read the bgs from the efuses */ 1308 ret = misc_read(dev, regs[0], &bgs, 1); 1309 if (ret) { 1310 printf("read bgs from efuse/otp failed, ret=%d\n", 1311 ret); 1312 bgs[0] = 0; 1313 } 1314 } 1315 } 1316 } 1317 #endif 1318 1319 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1320 1321 reset_assert(&pdata->phy_reset); 1322 udelay(20); 1323 rk_clrsetreg(&grf->macphy_con0, 1324 RV1106_MACPHY_ENABLE_MASK | 1325 RV1106_MACPHY_XMII_SEL_MASK | 1326 RV1106_MACPHY_24M_CLK_SEL_MASK | 1327 RV1106_MACPHY_PHY_ID_MASK, 1328 RV1106_MACPHY_ENABLE | 1329 RV1106_MACPHY_XMII_SEL | 1330 RV1106_MACPHY_24M_CLK_SEL_24M | 1331 RV1106_MACPHY_PHY_ID); 1332 1333 rk_clrsetreg(&grf->macphy_con1, 1334 RV1106_MACPHY_BGS_MASK, 1335 bgs[0]); 1336 udelay(20); 1337 reset_deassert(&pdata->phy_reset); 1338 udelay(30 * 1000); 1339 } 1340 1341 static void rv1106_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1342 { 1343 struct rv1106_grf *grf; 1344 enum { 1345 RV1106_VOGRF_GMAC_CLK_RMII_MODE_MASK = BIT(0), 1346 RV1106_VOGRF_GMAC_CLK_RMII_MODE = BIT(0), 1347 }; 1348 1349 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1350 rk_clrsetreg(&grf->gmac_clk_con, 1351 RV1106_VOGRF_GMAC_CLK_RMII_MODE_MASK, 1352 RV1106_VOGRF_GMAC_CLK_RMII_MODE); 1353 }; 1354 1355 static void rv1126_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1356 { 1357 struct rv1126_grf *grf; 1358 1359 enum { 1360 RV1126_GMAC_PHY_INTF_SEL_SHIFT = 4, 1361 RV1126_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1362 RV1126_GMAC_PHY_INTF_SEL_RMII = BIT(6), 1363 }; 1364 1365 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1366 1367 rk_clrsetreg(&grf->mac_con0, 1368 RV1126_GMAC_PHY_INTF_SEL_MASK, 1369 RV1126_GMAC_PHY_INTF_SEL_RMII); 1370 } 1371 1372 static void rv1126_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1373 { 1374 struct rv1126_grf *grf; 1375 1376 enum { 1377 RV1126_GMAC_PHY_INTF_SEL_SHIFT = 4, 1378 RV1126_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1379 RV1126_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 1380 1381 RV1126_RXCLK_M1_DLY_ENA_GMAC_MASK = BIT(3), 1382 RV1126_RXCLK_M1_DLY_ENA_GMAC_DISABLE = 0, 1383 RV1126_RXCLK_M1_DLY_ENA_GMAC_ENABLE = BIT(3), 1384 1385 RV1126_TXCLK_M1_DLY_ENA_GMAC_MASK = BIT(2), 1386 RV1126_TXCLK_M1_DLY_ENA_GMAC_DISABLE = 0, 1387 RV1126_TXCLK_M1_DLY_ENA_GMAC_ENABLE = BIT(2), 1388 1389 RV1126_RXCLK_M0_DLY_ENA_GMAC_MASK = BIT(1), 1390 RV1126_RXCLK_M0_DLY_ENA_GMAC_DISABLE = 0, 1391 RV1126_RXCLK_M0_DLY_ENA_GMAC_ENABLE = BIT(1), 1392 1393 RV1126_TXCLK_M0_DLY_ENA_GMAC_MASK = BIT(0), 1394 RV1126_TXCLK_M0_DLY_ENA_GMAC_DISABLE = 0, 1395 RV1126_TXCLK_M0_DLY_ENA_GMAC_ENABLE = BIT(0), 1396 }; 1397 enum { 1398 RV1126_M0_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1399 RV1126_M0_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 1400 1401 RV1126_M0_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1402 RV1126_M0_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 1403 }; 1404 enum { 1405 RV1126_M1_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1406 RV1126_M1_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 1407 1408 RV1126_M1_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1409 RV1126_M1_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 1410 }; 1411 1412 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1413 1414 rk_clrsetreg(&grf->mac_con0, 1415 RV1126_TXCLK_M0_DLY_ENA_GMAC_MASK | 1416 RV1126_RXCLK_M0_DLY_ENA_GMAC_MASK | 1417 RV1126_TXCLK_M1_DLY_ENA_GMAC_MASK | 1418 RV1126_RXCLK_M1_DLY_ENA_GMAC_MASK | 1419 RV1126_GMAC_PHY_INTF_SEL_MASK, 1420 RV1126_TXCLK_M0_DLY_ENA_GMAC_ENABLE | 1421 RV1126_RXCLK_M0_DLY_ENA_GMAC_ENABLE | 1422 RV1126_TXCLK_M1_DLY_ENA_GMAC_ENABLE | 1423 RV1126_RXCLK_M1_DLY_ENA_GMAC_ENABLE | 1424 RV1126_GMAC_PHY_INTF_SEL_RGMII); 1425 1426 rk_clrsetreg(&grf->mac_con1, 1427 RV1126_M0_CLK_RX_DL_CFG_GMAC_MASK | 1428 RV1126_M0_CLK_TX_DL_CFG_GMAC_MASK, 1429 (pdata->rx_delay << RV1126_M0_CLK_RX_DL_CFG_GMAC_SHIFT) | 1430 (pdata->tx_delay << RV1126_M0_CLK_TX_DL_CFG_GMAC_SHIFT)); 1431 1432 rk_clrsetreg(&grf->mac_con2, 1433 RV1126_M1_CLK_RX_DL_CFG_GMAC_MASK | 1434 RV1126_M1_CLK_TX_DL_CFG_GMAC_MASK, 1435 (pdata->rx_delay << RV1126_M1_CLK_RX_DL_CFG_GMAC_SHIFT) | 1436 (pdata->tx_delay << RV1126_M1_CLK_TX_DL_CFG_GMAC_SHIFT)); 1437 } 1438 #endif 1439 1440 #ifdef CONFIG_DWC_ETH_QOS 1441 static void rk3588_set_clock_selection(struct gmac_rockchip_platdata *pdata) 1442 { 1443 struct rk3588_php_grf *php_grf; 1444 unsigned int val, mask; 1445 1446 enum { 1447 RK3588_GMAC_CLK_SELET_SHIFT = 0x4, 1448 RK3588_GMAC_CLK_SELET_MASK = BIT(4), 1449 RK3588_GMAC_CLK_SELET_CRU = BIT(4), 1450 RK3588_GMAC_CLK_SELET_IO = 0, 1451 }; 1452 1453 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 1454 val = pdata->clock_input ? RK3588_GMAC_CLK_SELET_IO : 1455 RK3588_GMAC_CLK_SELET_CRU; 1456 mask = RK3588_GMAC_CLK_SELET_MASK; 1457 1458 if (pdata->bus_id == 1) { 1459 val <<= 5; 1460 mask <<= 5; 1461 } 1462 1463 rk_clrsetreg(&php_grf->clk_con1, mask, val); 1464 } 1465 #endif 1466 1467 static int gmac_rockchip_probe(struct udevice *dev) 1468 { 1469 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 1470 struct rk_gmac_ops *ops = 1471 (struct rk_gmac_ops *)dev_get_driver_data(dev); 1472 #ifdef CONFIG_DWC_ETH_QOS 1473 struct eqos_config *config; 1474 #else 1475 struct dw_eth_pdata *dw_pdata; 1476 #endif 1477 struct eth_pdata *eth_pdata; 1478 struct clk clk; 1479 ulong rate; 1480 int ret; 1481 1482 #ifdef CONFIG_DWC_ETH_QOS 1483 eth_pdata = &pdata->eth_pdata; 1484 config = (struct eqos_config *)&ops->config; 1485 memcpy(config, &eqos_rockchip_config, sizeof(struct eqos_config)); 1486 eth_pdata->phy_interface = config->ops->eqos_get_interface(dev); 1487 #else 1488 dw_pdata = &pdata->dw_eth_pdata; 1489 eth_pdata = &dw_pdata->eth_pdata; 1490 #endif 1491 pdata->bus_id = dev->seq; 1492 1493 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 1494 ret = clk_set_defaults(dev); 1495 if (ret) 1496 debug("%s clk_set_defaults failed %d\n", __func__, ret); 1497 1498 ret = clk_get_by_index(dev, 0, &clk); 1499 if (ret) 1500 return ret; 1501 1502 pdata->phy_interface = eth_pdata->phy_interface; 1503 1504 if (ops->set_clock_selection) 1505 ops->set_clock_selection(pdata); 1506 1507 if (pdata->integrated_phy && ops->integrated_phy_powerup) 1508 ops->integrated_phy_powerup(pdata); 1509 1510 switch (eth_pdata->phy_interface) { 1511 case PHY_INTERFACE_MODE_RGMII: 1512 case PHY_INTERFACE_MODE_RGMII_RXID: 1513 /* 1514 * If the gmac clock is from internal pll, need to set and 1515 * check the return value for gmac clock at RGMII mode. If 1516 * the gmac clock is from external source, the clock rate 1517 * is not set, because of it is bypassed. 1518 */ 1519 if (!pdata->clock_input) { 1520 rate = clk_set_rate(&clk, 125000000); 1521 if (rate != 125000000) 1522 return -EINVAL; 1523 } 1524 1525 if (eth_pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) 1526 pdata->rx_delay = -1; 1527 1528 /* Set to RGMII mode */ 1529 if (ops->set_to_rgmii) 1530 ops->set_to_rgmii(pdata); 1531 else 1532 return -EPERM; 1533 1534 break; 1535 case PHY_INTERFACE_MODE_RMII: 1536 /* The commet is the same as RGMII mode */ 1537 if (!pdata->clock_input) { 1538 rate = clk_set_rate(&clk, 50000000); 1539 if (rate != 50000000) 1540 return -EINVAL; 1541 } 1542 1543 /* Set to RMII mode */ 1544 if (ops->set_to_rmii) 1545 ops->set_to_rmii(pdata); 1546 1547 break; 1548 default: 1549 debug("NO interface defined!\n"); 1550 return -ENXIO; 1551 } 1552 1553 #ifdef CONFIG_DWC_ETH_QOS 1554 return eqos_probe(dev); 1555 #else 1556 return designware_eth_probe(dev); 1557 #endif 1558 } 1559 1560 static int gmac_rockchip_eth_write_hwaddr(struct udevice *dev) 1561 { 1562 #if defined(CONFIG_DWC_ETH_QOS) 1563 return eqos_write_hwaddr(dev); 1564 #else 1565 return designware_eth_write_hwaddr(dev); 1566 #endif 1567 } 1568 1569 static int gmac_rockchip_eth_free_pkt(struct udevice *dev, uchar *packet, 1570 int length) 1571 { 1572 #ifdef CONFIG_DWC_ETH_QOS 1573 return eqos_free_pkt(dev, packet, length); 1574 #else 1575 return designware_eth_free_pkt(dev, packet, length); 1576 #endif 1577 } 1578 1579 static int gmac_rockchip_eth_send(struct udevice *dev, void *packet, 1580 int length) 1581 { 1582 #ifdef CONFIG_DWC_ETH_QOS 1583 return eqos_send(dev, packet, length); 1584 #else 1585 return designware_eth_send(dev, packet, length); 1586 #endif 1587 } 1588 1589 static int gmac_rockchip_eth_recv(struct udevice *dev, int flags, 1590 uchar **packetp) 1591 { 1592 #ifdef CONFIG_DWC_ETH_QOS 1593 return eqos_recv(dev, flags, packetp); 1594 #else 1595 return designware_eth_recv(dev, flags, packetp); 1596 #endif 1597 } 1598 1599 static int gmac_rockchip_eth_start(struct udevice *dev) 1600 { 1601 struct rockchip_eth_dev *priv = dev_get_priv(dev); 1602 struct rk_gmac_ops *ops = 1603 (struct rk_gmac_ops *)dev_get_driver_data(dev); 1604 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 1605 #ifndef CONFIG_DWC_ETH_QOS 1606 struct dw_eth_pdata *dw_pdata; 1607 struct eth_pdata *eth_pdata; 1608 #endif 1609 int ret; 1610 1611 #ifdef CONFIG_DWC_ETH_QOS 1612 ret = eqos_init(dev); 1613 #else 1614 dw_pdata = &pdata->dw_eth_pdata; 1615 eth_pdata = &dw_pdata->eth_pdata; 1616 ret = designware_eth_init((struct dw_eth_dev *)priv, 1617 eth_pdata->enetaddr); 1618 #endif 1619 if (ret) 1620 return ret; 1621 ret = ops->fix_mac_speed(pdata, priv); 1622 if (ret) 1623 return ret; 1624 1625 #ifdef CONFIG_DWC_ETH_QOS 1626 eqos_enable(dev); 1627 #else 1628 ret = designware_eth_enable((struct dw_eth_dev *)priv); 1629 if (ret) 1630 return ret; 1631 #endif 1632 1633 return 0; 1634 } 1635 1636 static void gmac_rockchip_eth_stop(struct udevice *dev) 1637 { 1638 #ifdef CONFIG_DWC_ETH_QOS 1639 eqos_stop(dev); 1640 #else 1641 designware_eth_stop(dev); 1642 #endif 1643 } 1644 1645 const struct eth_ops gmac_rockchip_eth_ops = { 1646 .start = gmac_rockchip_eth_start, 1647 .send = gmac_rockchip_eth_send, 1648 .recv = gmac_rockchip_eth_recv, 1649 .free_pkt = gmac_rockchip_eth_free_pkt, 1650 .stop = gmac_rockchip_eth_stop, 1651 .write_hwaddr = gmac_rockchip_eth_write_hwaddr, 1652 }; 1653 1654 #ifndef CONFIG_DWC_ETH_QOS 1655 const struct rk_gmac_ops px30_gmac_ops = { 1656 .fix_mac_speed = px30_gmac_fix_mac_speed, 1657 .set_to_rmii = px30_gmac_set_to_rmii, 1658 }; 1659 1660 const struct rk_gmac_ops rk1808_gmac_ops = { 1661 .fix_mac_speed = rk1808_gmac_fix_mac_speed, 1662 .set_to_rgmii = rk1808_gmac_set_to_rgmii, 1663 }; 1664 1665 const struct rk_gmac_ops rk3228_gmac_ops = { 1666 .fix_mac_speed = rk3228_gmac_fix_mac_speed, 1667 .set_to_rmii = rk3228_gmac_set_to_rmii, 1668 .set_to_rgmii = rk3228_gmac_set_to_rgmii, 1669 .integrated_phy_powerup = rk3228_gmac_integrated_phy_powerup, 1670 }; 1671 1672 const struct rk_gmac_ops rk3288_gmac_ops = { 1673 .fix_mac_speed = rk3288_gmac_fix_mac_speed, 1674 .set_to_rgmii = rk3288_gmac_set_to_rgmii, 1675 }; 1676 1677 const struct rk_gmac_ops rk3308_gmac_ops = { 1678 .fix_mac_speed = rk3308_gmac_fix_mac_speed, 1679 .set_to_rmii = rk3308_gmac_set_to_rmii, 1680 }; 1681 1682 const struct rk_gmac_ops rk3328_gmac_ops = { 1683 .fix_mac_speed = rk3328_gmac_fix_mac_speed, 1684 .set_to_rmii = rk3328_gmac_set_to_rmii, 1685 .set_to_rgmii = rk3328_gmac_set_to_rgmii, 1686 .integrated_phy_powerup = rk3328_gmac_integrated_phy_powerup, 1687 }; 1688 1689 const struct rk_gmac_ops rk3368_gmac_ops = { 1690 .fix_mac_speed = rk3368_gmac_fix_mac_speed, 1691 .set_to_rgmii = rk3368_gmac_set_to_rgmii, 1692 }; 1693 1694 const struct rk_gmac_ops rk3399_gmac_ops = { 1695 .fix_mac_speed = rk3399_gmac_fix_mac_speed, 1696 .set_to_rgmii = rk3399_gmac_set_to_rgmii, 1697 }; 1698 1699 const struct rk_gmac_ops rv1108_gmac_ops = { 1700 .fix_mac_speed = rv1108_set_rmii_speed, 1701 .set_to_rmii = rv1108_gmac_set_to_rmii, 1702 }; 1703 #else 1704 const struct rk_gmac_ops rk3568_gmac_ops = { 1705 .fix_mac_speed = rv1126_set_rgmii_speed, 1706 .set_to_rgmii = rk3568_set_to_rgmii, 1707 .set_to_rmii = rk3568_set_to_rmii, 1708 }; 1709 1710 const struct rk_gmac_ops rk3588_gmac_ops = { 1711 .fix_mac_speed = rk3588_set_rgmii_speed, 1712 .set_to_rgmii = rk3588_set_to_rgmii, 1713 .set_to_rmii = rk3588_set_to_rmii, 1714 .set_clock_selection = rk3588_set_clock_selection, 1715 }; 1716 1717 const struct rk_gmac_ops rv1106_gmac_ops = { 1718 .fix_mac_speed = rv1106_set_rmii_speed, 1719 .set_to_rmii = rv1106_set_to_rmii, 1720 .integrated_phy_powerup = rv1106_gmac_integrated_phy_powerup, 1721 }; 1722 1723 const struct rk_gmac_ops rv1126_gmac_ops = { 1724 .fix_mac_speed = rv1126_set_rgmii_speed, 1725 .set_to_rgmii = rv1126_set_to_rgmii, 1726 .set_to_rmii = rv1126_set_to_rmii, 1727 }; 1728 #endif 1729 1730 static const struct udevice_id rockchip_gmac_ids[] = { 1731 #ifndef CONFIG_DWC_ETH_QOS 1732 #ifdef CONFIG_ROCKCHIP_PX30 1733 { .compatible = "rockchip,px30-gmac", 1734 .data = (ulong)&px30_gmac_ops }, 1735 #endif 1736 1737 #ifdef CONFIG_ROCKCHIP_RK1808 1738 { .compatible = "rockchip,rk1808-gmac", 1739 .data = (ulong)&rk1808_gmac_ops }, 1740 #endif 1741 1742 #ifdef CONFIG_ROCKCHIP_RK3228 1743 { .compatible = "rockchip,rk3228-gmac", 1744 .data = (ulong)&rk3228_gmac_ops }, 1745 #endif 1746 1747 #ifdef CONFIG_ROCKCHIP_RK3288 1748 { .compatible = "rockchip,rk3288-gmac", 1749 .data = (ulong)&rk3288_gmac_ops }, 1750 #endif 1751 1752 #ifdef CONFIG_ROCKCHIP_RK3308 1753 { .compatible = "rockchip,rk3308-mac", 1754 .data = (ulong)&rk3308_gmac_ops }, 1755 #endif 1756 1757 #ifdef CONFIG_ROCKCHIP_RK3328 1758 { .compatible = "rockchip,rk3328-gmac", 1759 .data = (ulong)&rk3328_gmac_ops }, 1760 #endif 1761 1762 #ifdef CONFIG_ROCKCHIP_RK3368 1763 { .compatible = "rockchip,rk3368-gmac", 1764 .data = (ulong)&rk3368_gmac_ops }, 1765 #endif 1766 1767 #ifdef CONFIG_ROCKCHIP_RK3399 1768 { .compatible = "rockchip,rk3399-gmac", 1769 .data = (ulong)&rk3399_gmac_ops }, 1770 #endif 1771 1772 #ifdef CONFIG_ROCKCHIP_RV1108 1773 { .compatible = "rockchip,rv1108-gmac", 1774 .data = (ulong)&rv1108_gmac_ops }, 1775 #endif 1776 #else 1777 #ifdef CONFIG_ROCKCHIP_RK3568 1778 { .compatible = "rockchip,rk3568-gmac", 1779 .data = (ulong)&rk3568_gmac_ops }, 1780 #endif 1781 1782 #ifdef CONFIG_ROCKCHIP_RK3588 1783 { .compatible = "rockchip,rk3588-gmac", 1784 .data = (ulong)&rk3588_gmac_ops }, 1785 #endif 1786 1787 #ifdef CONFIG_ROCKCHIP_RV1106 1788 { .compatible = "rockchip,rv1106-gmac", 1789 .data = (ulong)&rv1106_gmac_ops }, 1790 #endif 1791 1792 #ifdef CONFIG_ROCKCHIP_RV1126 1793 { .compatible = "rockchip,rv1126-gmac", 1794 .data = (ulong)&rv1126_gmac_ops }, 1795 #endif 1796 #endif 1797 { } 1798 }; 1799 1800 U_BOOT_DRIVER(eth_gmac_rockchip) = { 1801 .name = "gmac_rockchip", 1802 .id = UCLASS_ETH, 1803 .of_match = rockchip_gmac_ids, 1804 .ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata, 1805 .probe = gmac_rockchip_probe, 1806 .ops = &gmac_rockchip_eth_ops, 1807 .priv_auto_alloc_size = sizeof(struct rockchip_eth_dev), 1808 .platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata), 1809 .flags = DM_FLAG_ALLOC_PRIV_DMA, 1810 }; 1811