1 /* 2 * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Rockchip GMAC ethernet IP driver for U-Boot 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <clk.h> 12 #include <phy.h> 13 #include <syscon.h> 14 #include <asm/io.h> 15 #include <asm/arch/periph.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/hardware.h> 18 #include <asm/arch/grf_rk3288.h> 19 #include <asm/arch/grf_rk3368.h> 20 #include <asm/arch/grf_rk3399.h> 21 #include <asm/arch/grf_rv1108.h> 22 #include <dm/pinctrl.h> 23 #include <dt-bindings/clock/rk3288-cru.h> 24 #include "designware.h" 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 /* 29 * Platform data for the gmac 30 * 31 * dw_eth_pdata: Required platform data for designware driver (must be first) 32 */ 33 struct gmac_rockchip_platdata { 34 struct dw_eth_pdata dw_eth_pdata; 35 bool clock_input; 36 int tx_delay; 37 int rx_delay; 38 }; 39 40 struct rk_gmac_ops { 41 int (*fix_mac_speed)(struct dw_eth_dev *priv); 42 void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata); 43 void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata); 44 }; 45 46 void gmac_set_rgmii(struct udevice *dev, u32 tx_delay, u32 rx_delay) 47 { 48 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 49 struct rk_gmac_ops *ops = 50 (struct rk_gmac_ops *)dev_get_driver_data(dev); 51 52 pdata->tx_delay = tx_delay; 53 pdata->rx_delay = rx_delay; 54 55 ops->set_to_rgmii(pdata); 56 } 57 58 static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) 59 { 60 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 61 const char *string; 62 63 string = dev_read_string(dev, "clock_in_out"); 64 if (!strcmp(string, "input")) 65 pdata->clock_input = true; 66 else 67 pdata->clock_input = false; 68 69 /* Check the new naming-style first... */ 70 pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT); 71 pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT); 72 73 /* ... and fall back to the old naming style or default, if necessary */ 74 if (pdata->tx_delay == -ENOENT) 75 pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30); 76 if (pdata->rx_delay == -ENOENT) 77 pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10); 78 79 return designware_eth_ofdata_to_platdata(dev); 80 } 81 82 static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv) 83 { 84 struct rk3288_grf *grf; 85 int clk; 86 87 switch (priv->phydev->speed) { 88 case 10: 89 clk = RK3288_GMAC_CLK_SEL_2_5M; 90 break; 91 case 100: 92 clk = RK3288_GMAC_CLK_SEL_25M; 93 break; 94 case 1000: 95 clk = RK3288_GMAC_CLK_SEL_125M; 96 break; 97 default: 98 debug("Unknown phy speed: %d\n", priv->phydev->speed); 99 return -EINVAL; 100 } 101 102 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 103 rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk); 104 105 return 0; 106 } 107 108 static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv) 109 { 110 struct rk3368_grf *grf; 111 int clk; 112 enum { 113 RK3368_GMAC_CLK_SEL_2_5M = 2 << 4, 114 RK3368_GMAC_CLK_SEL_25M = 3 << 4, 115 RK3368_GMAC_CLK_SEL_125M = 0 << 4, 116 RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4), 117 }; 118 119 switch (priv->phydev->speed) { 120 case 10: 121 clk = RK3368_GMAC_CLK_SEL_2_5M; 122 break; 123 case 100: 124 clk = RK3368_GMAC_CLK_SEL_25M; 125 break; 126 case 1000: 127 clk = RK3368_GMAC_CLK_SEL_125M; 128 break; 129 default: 130 debug("Unknown phy speed: %d\n", priv->phydev->speed); 131 return -EINVAL; 132 } 133 134 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 135 rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk); 136 137 return 0; 138 } 139 140 static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv) 141 { 142 struct rk3399_grf_regs *grf; 143 int clk; 144 145 switch (priv->phydev->speed) { 146 case 10: 147 clk = RK3399_GMAC_CLK_SEL_2_5M; 148 break; 149 case 100: 150 clk = RK3399_GMAC_CLK_SEL_25M; 151 break; 152 case 1000: 153 clk = RK3399_GMAC_CLK_SEL_125M; 154 break; 155 default: 156 debug("Unknown phy speed: %d\n", priv->phydev->speed); 157 return -EINVAL; 158 } 159 160 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 161 rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk); 162 163 return 0; 164 } 165 166 static int rv1108_set_rmii_speed(struct dw_eth_dev *priv) 167 { 168 struct rv1108_grf *grf; 169 int clk, speed; 170 enum { 171 RV1108_GMAC_SPEED_MASK = BIT(2), 172 RV1108_GMAC_SPEED_10M = 0 << 2, 173 RV1108_GMAC_SPEED_100M = 1 << 2, 174 RV1108_GMAC_CLK_SEL_MASK = BIT(7), 175 RV1108_GMAC_CLK_SEL_2_5M = 0 << 7, 176 RV1108_GMAC_CLK_SEL_25M = 1 << 7, 177 }; 178 179 switch (priv->phydev->speed) { 180 case 10: 181 clk = RV1108_GMAC_CLK_SEL_2_5M; 182 speed = RV1108_GMAC_SPEED_10M; 183 break; 184 case 100: 185 clk = RV1108_GMAC_CLK_SEL_25M; 186 speed = RV1108_GMAC_SPEED_100M; 187 break; 188 default: 189 debug("Unknown phy speed: %d\n", priv->phydev->speed); 190 return -EINVAL; 191 } 192 193 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 194 rk_clrsetreg(&grf->gmac_con0, 195 RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK, 196 clk | speed); 197 198 return 0; 199 } 200 201 static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 202 { 203 struct rk3288_grf *grf; 204 205 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 206 rk_clrsetreg(&grf->soc_con1, 207 RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK, 208 RK3288_GMAC_PHY_INTF_SEL_RGMII); 209 210 rk_clrsetreg(&grf->soc_con3, 211 RK3288_RXCLK_DLY_ENA_GMAC_MASK | 212 RK3288_TXCLK_DLY_ENA_GMAC_MASK | 213 RK3288_CLK_RX_DL_CFG_GMAC_MASK | 214 RK3288_CLK_TX_DL_CFG_GMAC_MASK, 215 RK3288_RXCLK_DLY_ENA_GMAC_ENABLE | 216 RK3288_TXCLK_DLY_ENA_GMAC_ENABLE | 217 pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT | 218 pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT); 219 } 220 221 static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 222 { 223 struct rk3368_grf *grf; 224 enum { 225 RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9, 226 RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9), 227 RK3368_RMII_MODE_MASK = BIT(6), 228 RK3368_RMII_MODE = BIT(6), 229 }; 230 enum { 231 RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15), 232 RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 233 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15), 234 RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7), 235 RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 236 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7), 237 RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8, 238 RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 239 RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0, 240 RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 241 }; 242 243 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 244 rk_clrsetreg(&grf->soc_con15, 245 RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK, 246 RK3368_GMAC_PHY_INTF_SEL_RGMII); 247 248 rk_clrsetreg(&grf->soc_con16, 249 RK3368_RXCLK_DLY_ENA_GMAC_MASK | 250 RK3368_TXCLK_DLY_ENA_GMAC_MASK | 251 RK3368_CLK_RX_DL_CFG_GMAC_MASK | 252 RK3368_CLK_TX_DL_CFG_GMAC_MASK, 253 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE | 254 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE | 255 pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT | 256 pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT); 257 } 258 259 static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 260 { 261 struct rk3399_grf_regs *grf; 262 263 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 264 265 rk_clrsetreg(&grf->soc_con5, 266 RK3399_GMAC_PHY_INTF_SEL_MASK, 267 RK3399_GMAC_PHY_INTF_SEL_RGMII); 268 269 rk_clrsetreg(&grf->soc_con6, 270 RK3399_RXCLK_DLY_ENA_GMAC_MASK | 271 RK3399_TXCLK_DLY_ENA_GMAC_MASK | 272 RK3399_CLK_RX_DL_CFG_GMAC_MASK | 273 RK3399_CLK_TX_DL_CFG_GMAC_MASK, 274 RK3399_RXCLK_DLY_ENA_GMAC_ENABLE | 275 RK3399_TXCLK_DLY_ENA_GMAC_ENABLE | 276 pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT | 277 pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT); 278 } 279 280 static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 281 { 282 struct rv1108_grf *grf; 283 284 enum { 285 RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 286 RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4, 287 }; 288 289 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 290 rk_clrsetreg(&grf->gmac_con0, 291 RV1108_GMAC_PHY_INTF_SEL_MASK, 292 RV1108_GMAC_PHY_INTF_SEL_RMII); 293 } 294 295 static int gmac_rockchip_probe(struct udevice *dev) 296 { 297 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 298 struct rk_gmac_ops *ops = 299 (struct rk_gmac_ops *)dev_get_driver_data(dev); 300 struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev); 301 struct eth_pdata *eth_pdata = &dw_pdata->eth_pdata; 302 struct clk clk; 303 ulong rate; 304 int ret; 305 306 ret = clk_get_by_index(dev, 0, &clk); 307 if (ret) 308 return ret; 309 310 switch (eth_pdata->phy_interface) { 311 case PHY_INTERFACE_MODE_RGMII: 312 /* 313 * If the gmac clock is from internal pll, need to set and 314 * check the return value for gmac clock at RGMII mode. If 315 * the gmac clock is from external source, the clock rate 316 * is not set, because of it is bypassed. 317 */ 318 if (!pdata->clock_input) { 319 rate = clk_set_rate(&clk, 125000000); 320 if (rate != 125000000) 321 return -EINVAL; 322 } 323 324 /* Set to RGMII mode */ 325 if (ops->set_to_rgmii) 326 ops->set_to_rgmii(pdata); 327 else 328 return -EPERM; 329 330 break; 331 case PHY_INTERFACE_MODE_RMII: 332 /* The commet is the same as RGMII mode */ 333 if (!pdata->clock_input) { 334 rate = clk_set_rate(&clk, 50000000); 335 if (rate != 50000000) 336 return -EINVAL; 337 } 338 339 /* Set to RMII mode */ 340 if (ops->set_to_rmii) 341 ops->set_to_rmii(pdata); 342 else 343 return -EPERM; 344 345 break; 346 default: 347 debug("NO interface defined!\n"); 348 return -ENXIO; 349 } 350 351 return designware_eth_probe(dev); 352 } 353 354 static int gmac_rockchip_eth_start(struct udevice *dev) 355 { 356 struct eth_pdata *pdata = dev_get_platdata(dev); 357 struct dw_eth_dev *priv = dev_get_priv(dev); 358 struct rk_gmac_ops *ops = 359 (struct rk_gmac_ops *)dev_get_driver_data(dev); 360 int ret; 361 362 ret = designware_eth_init(priv, pdata->enetaddr); 363 if (ret) 364 return ret; 365 ret = ops->fix_mac_speed(priv); 366 if (ret) 367 return ret; 368 ret = designware_eth_enable(priv); 369 if (ret) 370 return ret; 371 372 return 0; 373 } 374 375 const struct eth_ops gmac_rockchip_eth_ops = { 376 .start = gmac_rockchip_eth_start, 377 .send = designware_eth_send, 378 .recv = designware_eth_recv, 379 .free_pkt = designware_eth_free_pkt, 380 .stop = designware_eth_stop, 381 .write_hwaddr = designware_eth_write_hwaddr, 382 }; 383 384 const struct rk_gmac_ops rk3288_gmac_ops = { 385 .fix_mac_speed = rk3288_gmac_fix_mac_speed, 386 .set_to_rgmii = rk3288_gmac_set_to_rgmii, 387 }; 388 389 const struct rk_gmac_ops rk3368_gmac_ops = { 390 .fix_mac_speed = rk3368_gmac_fix_mac_speed, 391 .set_to_rgmii = rk3368_gmac_set_to_rgmii, 392 }; 393 394 const struct rk_gmac_ops rk3399_gmac_ops = { 395 .fix_mac_speed = rk3399_gmac_fix_mac_speed, 396 .set_to_rgmii = rk3399_gmac_set_to_rgmii, 397 }; 398 399 const struct rk_gmac_ops rv1108_gmac_ops = { 400 .fix_mac_speed = rv1108_set_rmii_speed, 401 .set_to_rmii = rv1108_gmac_set_to_rmii, 402 }; 403 404 static const struct udevice_id rockchip_gmac_ids[] = { 405 { .compatible = "rockchip,rk3288-gmac", 406 .data = (ulong)&rk3288_gmac_ops }, 407 { .compatible = "rockchip,rk3368-gmac", 408 .data = (ulong)&rk3368_gmac_ops }, 409 { .compatible = "rockchip,rk3399-gmac", 410 .data = (ulong)&rk3399_gmac_ops }, 411 { .compatible = "rockchip,rv1108-gmac", 412 .data = (ulong)&rv1108_gmac_ops }, 413 { } 414 }; 415 416 U_BOOT_DRIVER(eth_gmac_rockchip) = { 417 .name = "gmac_rockchip", 418 .id = UCLASS_ETH, 419 .of_match = rockchip_gmac_ids, 420 .ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata, 421 .probe = gmac_rockchip_probe, 422 .ops = &gmac_rockchip_eth_ops, 423 .priv_auto_alloc_size = sizeof(struct dw_eth_dev), 424 .platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata), 425 .flags = DM_FLAG_ALLOC_PRIV_DMA, 426 }; 427