1 /* 2 * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Rockchip GMAC ethernet IP driver for U-Boot 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <clk.h> 12 #include <misc.h> 13 #include <phy.h> 14 #include <reset.h> 15 #include <syscon.h> 16 #include <asm/io.h> 17 #include <asm/arch/periph.h> 18 #include <asm/arch/clock.h> 19 #include <asm/arch/hardware.h> 20 #ifdef CONFIG_DWC_ETH_QOS 21 #include <asm/arch/grf_rk3506.h> 22 #include <asm/arch/grf_rk3528.h> 23 #include <asm/arch/grf_rk3562.h> 24 #include <asm/arch/ioc_rk3562.h> 25 #include <asm/arch/grf_rk3568.h> 26 #include <asm/arch/grf_rk3576.h> 27 #include <asm/arch/ioc_rk3576.h> 28 #include <asm/arch/grf_rk3588.h> 29 #include <asm/arch/grf_rv1103b.h> 30 #include <asm/arch/grf_rv1106.h> 31 #include <asm/arch/grf_rv1126.h> 32 #include <asm/arch/grf_rv1126b.h> 33 #include <asm/arch/ioc_rv1126b.h> 34 #include "dwc_eth_qos.h" 35 #else 36 #include <asm/arch/grf_px30.h> 37 #include <asm/arch/grf_rk1808.h> 38 #include <asm/arch/grf_rk322x.h> 39 #include <asm/arch/grf_rk3288.h> 40 #include <asm/arch/grf_rk3308.h> 41 #include <asm/arch/grf_rk3328.h> 42 #include <asm/arch/grf_rk3368.h> 43 #include <asm/arch/grf_rk3399.h> 44 #include <asm/arch/grf_rv1108.h> 45 #include "designware.h" 46 #include <dt-bindings/clock/rk3288-cru.h> 47 #endif 48 #include <dm/pinctrl.h> 49 #include <dm/of_access.h> 50 51 DECLARE_GLOBAL_DATA_PTR; 52 53 struct rockchip_eth_dev { 54 #ifdef CONFIG_DWC_ETH_QOS 55 struct eqos_priv eqos; 56 #else 57 struct dw_eth_dev dw; 58 #endif 59 int phy_interface; 60 }; 61 62 #define HIWORD_UPDATE(val, mask, shift) ((val) << (shift) | (mask) << ((shift) + 16)) 63 64 #define DELAY_VALUE(soc, tx, rx) ((((tx) >= 0) ? soc##_GMAC_CLK_TX_DL_CFG(tx) : 0) | (((rx) >= 0) ? soc##_GMAC_CLK_RX_DL_CFG(rx) : 0)) 65 66 #define RK3576_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 67 #define RK3576_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 68 69 /* 70 * Platform data for the gmac 71 * 72 * dw_eth_pdata: Required platform data for designware driver (must be first) 73 */ 74 struct gmac_rockchip_platdata { 75 #ifndef CONFIG_DWC_ETH_QOS 76 struct dw_eth_pdata dw_eth_pdata; 77 #else 78 struct eth_pdata eth_pdata; 79 #endif 80 struct reset_ctl phy_reset; 81 bool integrated_phy; 82 bool clock_input; 83 int phy_interface; 84 int tx_delay; 85 int rx_delay; 86 int bus_id; 87 }; 88 89 struct rk_gmac_ops { 90 #ifdef CONFIG_DWC_ETH_QOS 91 const struct eqos_config config; 92 #endif 93 int (*fix_mac_speed)(struct gmac_rockchip_platdata *pdata, 94 struct rockchip_eth_dev *dev); 95 void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata); 96 void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata); 97 void (*set_clock_selection)(struct gmac_rockchip_platdata *pdata); 98 void (*integrated_phy_powerup)(struct gmac_rockchip_platdata *pdata); 99 }; 100 101 #ifdef CONFIG_DWC_ETH_QOS 102 static const struct eqos_config eqos_rockchip_config = { 103 .reg_access_always_ok = false, 104 .mdio_wait = 10000, 105 .swr_wait = 200, 106 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED, 107 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_100_150, 108 .ops = &eqos_rockchip_ops, 109 }; 110 #endif 111 112 void gmac_set_rgmii(struct udevice *dev, u32 tx_delay, u32 rx_delay) 113 { 114 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 115 struct rk_gmac_ops *ops = 116 (struct rk_gmac_ops *)dev_get_driver_data(dev); 117 118 pdata->tx_delay = tx_delay; 119 pdata->rx_delay = rx_delay; 120 121 ops->set_to_rgmii(pdata); 122 } 123 124 static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) 125 { 126 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 127 struct ofnode_phandle_args args; 128 struct udevice *phydev; 129 const char *string; 130 int ret; 131 132 string = dev_read_string(dev, "clock_in_out"); 133 if (!strcmp(string, "input")) 134 pdata->clock_input = true; 135 else 136 pdata->clock_input = false; 137 138 /* If phy-handle property is passed from DT, use it as the PHY */ 139 ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &args); 140 if (ret) { 141 debug("Cannot get phy phandle: ret=%d\n", ret); 142 pdata->integrated_phy = dev_read_bool(dev, "phy-is-integrated"); 143 } else { 144 debug("Found phy-handle subnode\n"); 145 pdata->integrated_phy = ofnode_read_bool(args.node, 146 "phy-is-integrated"); 147 } 148 149 if (pdata->integrated_phy) { 150 ret = reset_get_by_name(dev, "mac-phy", &pdata->phy_reset); 151 if (ret) { 152 ret = uclass_get_device_by_ofnode(UCLASS_ETH_PHY, args.node, &phydev); 153 if (ret) { 154 debug("Get phydev by ofnode failed: err=%d\n", ret); 155 return ret; 156 } 157 158 ret = reset_get_by_index(phydev, 0, &pdata->phy_reset); 159 if (ret) { 160 debug("No PHY reset control found: ret=%d\n", ret); 161 return ret; 162 } 163 } 164 } 165 166 /* Check the new naming-style first... */ 167 pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT); 168 pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT); 169 170 /* ... and fall back to the old naming style or default, if necessary */ 171 if (pdata->tx_delay == -ENOENT) 172 pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30); 173 if (pdata->rx_delay == -ENOENT) 174 pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10); 175 176 #ifdef CONFIG_DWC_ETH_QOS 177 return 0; 178 #else 179 return designware_eth_ofdata_to_platdata(dev); 180 #endif 181 } 182 183 #ifndef CONFIG_DWC_ETH_QOS 184 static int px30_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 185 struct rockchip_eth_dev *dev) 186 { 187 struct dw_eth_dev *priv = &dev->dw; 188 struct px30_grf *grf; 189 struct clk clk_speed; 190 int speed, ret; 191 enum { 192 PX30_GMAC_SPEED_SHIFT = 0x2, 193 PX30_GMAC_SPEED_MASK = BIT(2), 194 PX30_GMAC_SPEED_10M = 0, 195 PX30_GMAC_SPEED_100M = BIT(2), 196 }; 197 198 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 199 &clk_speed); 200 if (ret) 201 return ret; 202 203 switch (priv->phydev->speed) { 204 case 10: 205 speed = PX30_GMAC_SPEED_10M; 206 ret = clk_set_rate(&clk_speed, 2500000); 207 if (ret) 208 return ret; 209 break; 210 case 100: 211 speed = PX30_GMAC_SPEED_100M; 212 ret = clk_set_rate(&clk_speed, 25000000); 213 if (ret) 214 return ret; 215 break; 216 default: 217 debug("Unknown phy speed: %d\n", priv->phydev->speed); 218 return -EINVAL; 219 } 220 221 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 222 rk_clrsetreg(&grf->mac_con1, PX30_GMAC_SPEED_MASK, speed); 223 224 return 0; 225 } 226 227 static int rk1808_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 228 struct rockchip_eth_dev *dev) 229 { 230 struct dw_eth_dev *priv = &dev->dw; 231 struct clk clk_speed; 232 int ret; 233 234 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 235 &clk_speed); 236 if (ret) 237 return ret; 238 239 switch (priv->phydev->speed) { 240 case 10: 241 ret = clk_set_rate(&clk_speed, 2500000); 242 if (ret) 243 return ret; 244 break; 245 case 100: 246 ret = clk_set_rate(&clk_speed, 25000000); 247 if (ret) 248 return ret; 249 break; 250 case 1000: 251 ret = clk_set_rate(&clk_speed, 125000000); 252 if (ret) 253 return ret; 254 break; 255 default: 256 debug("Unknown phy speed: %d\n", priv->phydev->speed); 257 return -EINVAL; 258 } 259 260 return 0; 261 } 262 263 static int rk3228_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 264 struct rockchip_eth_dev *dev) 265 { 266 struct dw_eth_dev *priv = &dev->dw; 267 struct rk322x_grf *grf; 268 int clk; 269 enum { 270 RK3228_GMAC_CLK_SEL_SHIFT = 8, 271 RK3228_GMAC_CLK_SEL_MASK = GENMASK(9, 8), 272 RK3228_GMAC_CLK_SEL_125M = 0 << 8, 273 RK3228_GMAC_CLK_SEL_25M = 3 << 8, 274 RK3228_GMAC_CLK_SEL_2_5M = 2 << 8, 275 276 RK3228_GMAC_RMII_CLK_MASK = BIT(7), 277 RK3228_GMAC_RMII_CLK_2_5M = 0, 278 RK3228_GMAC_RMII_CLK_25M = BIT(7), 279 280 RK3228_GMAC_RMII_SPEED_MASK = BIT(2), 281 RK3228_GMAC_RMII_SPEED_10 = 0, 282 RK3228_GMAC_RMII_SPEED_100 = BIT(2), 283 }; 284 285 switch (priv->phydev->speed) { 286 case 10: 287 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 288 (RK3228_GMAC_RMII_CLK_2_5M | RK3228_GMAC_RMII_SPEED_10) : 289 RK3228_GMAC_CLK_SEL_2_5M; 290 break; 291 case 100: 292 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 293 (RK3228_GMAC_RMII_CLK_25M | RK3228_GMAC_RMII_SPEED_100) : 294 RK3228_GMAC_CLK_SEL_25M; 295 break; 296 case 1000: 297 clk = RK3228_GMAC_CLK_SEL_125M; 298 break; 299 default: 300 debug("Unknown phy speed: %d\n", priv->phydev->speed); 301 return -EINVAL; 302 } 303 304 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 305 rk_clrsetreg(&grf->mac_con[1], 306 RK3228_GMAC_CLK_SEL_MASK | 307 RK3228_GMAC_RMII_CLK_MASK | 308 RK3228_GMAC_RMII_SPEED_MASK, 309 clk); 310 311 return 0; 312 } 313 314 static int rk3288_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 315 struct rockchip_eth_dev *dev) 316 { 317 struct dw_eth_dev *priv = &dev->dw; 318 struct rk3288_grf *grf; 319 int clk; 320 321 switch (priv->phydev->speed) { 322 case 10: 323 clk = RK3288_GMAC_CLK_SEL_2_5M; 324 break; 325 case 100: 326 clk = RK3288_GMAC_CLK_SEL_25M; 327 break; 328 case 1000: 329 clk = RK3288_GMAC_CLK_SEL_125M; 330 break; 331 default: 332 debug("Unknown phy speed: %d\n", priv->phydev->speed); 333 return -EINVAL; 334 } 335 336 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 337 rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk); 338 339 return 0; 340 } 341 342 static int rk3308_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 343 struct rockchip_eth_dev *dev) 344 { 345 struct dw_eth_dev *priv = &dev->dw; 346 struct rk3308_grf *grf; 347 struct clk clk_speed; 348 int speed, ret; 349 enum { 350 RK3308_GMAC_SPEED_SHIFT = 0x0, 351 RK3308_GMAC_SPEED_MASK = BIT(0), 352 RK3308_GMAC_SPEED_10M = 0, 353 RK3308_GMAC_SPEED_100M = BIT(0), 354 }; 355 356 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", 357 &clk_speed); 358 if (ret) 359 return ret; 360 361 switch (priv->phydev->speed) { 362 case 10: 363 speed = RK3308_GMAC_SPEED_10M; 364 ret = clk_set_rate(&clk_speed, 2500000); 365 if (ret) 366 return ret; 367 break; 368 case 100: 369 speed = RK3308_GMAC_SPEED_100M; 370 ret = clk_set_rate(&clk_speed, 25000000); 371 if (ret) 372 return ret; 373 break; 374 default: 375 debug("Unknown phy speed: %d\n", priv->phydev->speed); 376 return -EINVAL; 377 } 378 379 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 380 rk_clrsetreg(&grf->mac_con0, RK3308_GMAC_SPEED_MASK, speed); 381 382 return 0; 383 } 384 385 static int rk3328_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 386 struct rockchip_eth_dev *dev) 387 { 388 struct dw_eth_dev *priv = &dev->dw; 389 struct rk3328_grf_regs *grf; 390 int clk; 391 enum { 392 RK3328_GMAC_CLK_SEL_SHIFT = 11, 393 RK3328_GMAC_CLK_SEL_MASK = GENMASK(12, 11), 394 RK3328_GMAC_CLK_SEL_125M = 0 << 11, 395 RK3328_GMAC_CLK_SEL_25M = 3 << 11, 396 RK3328_GMAC_CLK_SEL_2_5M = 2 << 11, 397 398 RK3328_GMAC_RMII_CLK_MASK = BIT(7), 399 RK3328_GMAC_RMII_CLK_2_5M = 0, 400 RK3328_GMAC_RMII_CLK_25M = BIT(7), 401 402 RK3328_GMAC_RMII_SPEED_MASK = BIT(2), 403 RK3328_GMAC_RMII_SPEED_10 = 0, 404 RK3328_GMAC_RMII_SPEED_100 = BIT(2), 405 }; 406 407 switch (priv->phydev->speed) { 408 case 10: 409 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 410 (RK3328_GMAC_RMII_CLK_2_5M | RK3328_GMAC_RMII_SPEED_10) : 411 RK3328_GMAC_CLK_SEL_2_5M; 412 break; 413 case 100: 414 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? 415 (RK3328_GMAC_RMII_CLK_25M | RK3328_GMAC_RMII_SPEED_100) : 416 RK3328_GMAC_CLK_SEL_25M; 417 break; 418 case 1000: 419 clk = RK3328_GMAC_CLK_SEL_125M; 420 break; 421 default: 422 debug("Unknown phy speed: %d\n", priv->phydev->speed); 423 return -EINVAL; 424 } 425 426 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 427 rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1], 428 RK3328_GMAC_CLK_SEL_MASK | 429 RK3328_GMAC_RMII_CLK_MASK | 430 RK3328_GMAC_RMII_SPEED_MASK, 431 clk); 432 433 return 0; 434 } 435 436 static int rk3368_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 437 struct rockchip_eth_dev *dev) 438 { 439 struct dw_eth_dev *priv = &dev->dw; 440 struct rk3368_grf *grf; 441 int clk; 442 enum { 443 RK3368_GMAC_CLK_SEL_2_5M = 2 << 4, 444 RK3368_GMAC_CLK_SEL_25M = 3 << 4, 445 RK3368_GMAC_CLK_SEL_125M = 0 << 4, 446 RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4), 447 }; 448 449 switch (priv->phydev->speed) { 450 case 10: 451 clk = RK3368_GMAC_CLK_SEL_2_5M; 452 break; 453 case 100: 454 clk = RK3368_GMAC_CLK_SEL_25M; 455 break; 456 case 1000: 457 clk = RK3368_GMAC_CLK_SEL_125M; 458 break; 459 default: 460 debug("Unknown phy speed: %d\n", priv->phydev->speed); 461 return -EINVAL; 462 } 463 464 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 465 rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk); 466 467 return 0; 468 } 469 470 static int rk3399_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata, 471 struct rockchip_eth_dev *dev) 472 { 473 struct dw_eth_dev *priv = &dev->dw; 474 struct rk3399_grf_regs *grf; 475 int clk; 476 477 switch (priv->phydev->speed) { 478 case 10: 479 clk = RK3399_GMAC_CLK_SEL_2_5M; 480 break; 481 case 100: 482 clk = RK3399_GMAC_CLK_SEL_25M; 483 break; 484 case 1000: 485 clk = RK3399_GMAC_CLK_SEL_125M; 486 break; 487 default: 488 debug("Unknown phy speed: %d\n", priv->phydev->speed); 489 return -EINVAL; 490 } 491 492 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 493 rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk); 494 495 return 0; 496 } 497 498 static int rv1108_set_rmii_speed(struct gmac_rockchip_platdata *pdata, 499 struct rockchip_eth_dev *dev) 500 { 501 struct dw_eth_dev *priv = &dev->dw; 502 struct rv1108_grf *grf; 503 int clk, speed; 504 enum { 505 RV1108_GMAC_SPEED_MASK = BIT(2), 506 RV1108_GMAC_SPEED_10M = 0 << 2, 507 RV1108_GMAC_SPEED_100M = 1 << 2, 508 RV1108_GMAC_CLK_SEL_MASK = BIT(7), 509 RV1108_GMAC_CLK_SEL_2_5M = 0 << 7, 510 RV1108_GMAC_CLK_SEL_25M = 1 << 7, 511 }; 512 513 switch (priv->phydev->speed) { 514 case 10: 515 clk = RV1108_GMAC_CLK_SEL_2_5M; 516 speed = RV1108_GMAC_SPEED_10M; 517 break; 518 case 100: 519 clk = RV1108_GMAC_CLK_SEL_25M; 520 speed = RV1108_GMAC_SPEED_100M; 521 break; 522 default: 523 debug("Unknown phy speed: %d\n", priv->phydev->speed); 524 return -EINVAL; 525 } 526 527 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 528 rk_clrsetreg(&grf->gmac_con0, 529 RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK, 530 clk | speed); 531 532 return 0; 533 } 534 #else 535 static int rk3506_set_rmii_speed(struct gmac_rockchip_platdata *pdata, 536 struct rockchip_eth_dev *dev) 537 { 538 struct eqos_priv *priv = &dev->eqos; 539 struct rk3506_grf_reg *grf; 540 unsigned int div; 541 542 enum { 543 RK3506_GMAC_CLK_RMII_DIV_SHIFT = 3, 544 RK3506_GMAC_CLK_RMII_DIV_MASK = BIT(3), 545 RK3506_GMAC_CLK_RMII_DIV2 = BIT(3), 546 RK3506_GMAC_CLK_RMII_DIV20 = 0, 547 }; 548 549 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 550 551 switch (priv->phy->speed) { 552 case 10: 553 div = RK3506_GMAC_CLK_RMII_DIV20; 554 break; 555 case 100: 556 div = RK3506_GMAC_CLK_RMII_DIV2; 557 break; 558 default: 559 debug("Unknown phy speed: %d\n", priv->phy->speed); 560 return -EINVAL; 561 } 562 563 if (pdata->bus_id) 564 rk_clrsetreg(&grf->soc_con11, RK3506_GMAC_CLK_RMII_DIV_MASK, div); 565 else 566 rk_clrsetreg(&grf->soc_con8, RK3506_GMAC_CLK_RMII_DIV_MASK, div); 567 568 return 0; 569 } 570 571 static int rk3528_set_rgmii_speed(struct gmac_rockchip_platdata *pdata, 572 struct rockchip_eth_dev *dev) 573 { 574 struct eqos_priv *priv = &dev->eqos; 575 struct rk3528_grf *grf; 576 unsigned int div; 577 578 enum { 579 RK3528_GMAC0_CLK_RMII_DIV_SHIFT = 3, 580 RK3528_GMAC0_CLK_RMII_DIV_MASK = GENMASK(4, 3), 581 RK3528_GMAC0_CLK_RMII_DIV2 = BIT(3), 582 RK3528_GMAC0_CLK_RMII_DIV20 = 0, 583 }; 584 585 enum { 586 RK3528_GMAC1_CLK_RGMII_DIV_SHIFT = 10, 587 RK3528_GMAC1_CLK_RGMII_DIV_MASK = GENMASK(11, 10), 588 RK3528_GMAC1_CLK_RGMII_DIV1 = 0, 589 RK3528_GMAC1_CLK_RGMII_DIV5 = GENMASK(11, 10), 590 RK3528_GMAC1_CLK_RGMII_DIV50 = BIT(11), 591 RK3528_GMAC1_CLK_RMII_DIV2 = BIT(11), 592 RK3528_GMAC1_CLK_RMII_DIV20 = 0, 593 }; 594 595 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 596 597 switch (priv->phy->speed) { 598 case 10: 599 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) 600 div = pdata->bus_id ? RK3528_GMAC1_CLK_RMII_DIV20 : 601 RK3528_GMAC0_CLK_RMII_DIV20; 602 else 603 div = RK3528_GMAC1_CLK_RGMII_DIV50; 604 break; 605 case 100: 606 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) 607 div = pdata->bus_id ? RK3528_GMAC1_CLK_RMII_DIV2 : 608 RK3528_GMAC0_CLK_RMII_DIV2; 609 else 610 div = RK3528_GMAC1_CLK_RGMII_DIV5; 611 break; 612 case 1000: 613 if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII) 614 div = RK3528_GMAC1_CLK_RGMII_DIV1; 615 else 616 return -EINVAL; 617 break; 618 default: 619 debug("Unknown phy speed: %d\n", priv->phy->speed); 620 return -EINVAL; 621 } 622 623 if (pdata->bus_id) 624 rk_clrsetreg(&grf->gmac1_con0, RK3528_GMAC1_CLK_RGMII_DIV_MASK, div); 625 else 626 rk_clrsetreg(&grf->gmac0_con, RK3528_GMAC0_CLK_RMII_DIV_MASK, div); 627 628 return 0; 629 } 630 631 static int rk3562_set_gmac_speed(struct gmac_rockchip_platdata *pdata, 632 struct rockchip_eth_dev *dev) 633 { 634 struct eqos_priv *priv = &dev->eqos; 635 struct rk3562_grf *grf; 636 unsigned int div; 637 638 enum { 639 RK3562_GMAC0_CLK_RGMII_DIV_SHIFT = 7, 640 RK3562_GMAC0_CLK_RGMII_DIV_MASK = GENMASK(8, 7), 641 RK3562_GMAC0_CLK_RGMII_DIV1 = 0, 642 RK3562_GMAC0_CLK_RGMII_DIV5 = GENMASK(8, 7), 643 RK3562_GMAC0_CLK_RGMII_DIV50 = BIT(8), 644 RK3562_GMAC0_CLK_RMII_DIV2 = BIT(7), 645 RK3562_GMAC0_CLK_RMII_DIV20 = 0, 646 }; 647 648 enum { 649 RK3562_GMAC1_SPEED_SHIFT = 0x0, 650 RK3562_GMAC1_SPEED_MASK = BIT(0), 651 RK3562_GMAC1_SPEED_10M = 0, 652 RK3562_GMAC1_SPEED_100M = BIT(0), 653 }; 654 655 enum { 656 RK3562_GMAC1_CLK_RMII_DIV_SHIFT = 13, 657 RK3562_GMAC1_CLK_RMII_DIV_MASK = BIT(13), 658 RK3562_GMAC1_CLK_RMII_DIV2 = BIT(13), 659 RK3562_GMAC1_CLK_RMII_DIV20 = 0, 660 }; 661 662 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 663 664 switch (priv->phy->speed) { 665 case 10: 666 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) { 667 if (pdata->bus_id > 0) { 668 div = RK3562_GMAC1_CLK_RMII_DIV20; 669 rk_clrsetreg(&grf->soc_con[0], 670 RK3562_GMAC1_SPEED_MASK, 671 RK3562_GMAC1_SPEED_10M); 672 } else { 673 div = RK3562_GMAC0_CLK_RMII_DIV20; 674 } 675 } else { 676 div = RK3562_GMAC0_CLK_RGMII_DIV50; 677 } 678 break; 679 case 100: 680 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) { 681 if (pdata->bus_id > 0) { 682 div = RK3562_GMAC1_CLK_RMII_DIV2; 683 rk_clrsetreg(&grf->soc_con[0], 684 RK3562_GMAC1_SPEED_MASK, 685 RK3562_GMAC1_SPEED_100M); 686 } else { 687 div = RK3562_GMAC0_CLK_RMII_DIV2; 688 } 689 } else { 690 div = RK3562_GMAC0_CLK_RGMII_DIV5; 691 } 692 break; 693 case 1000: 694 if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII) 695 div = RK3562_GMAC0_CLK_RGMII_DIV1; 696 else 697 return -EINVAL; 698 break; 699 default: 700 debug("Unknown phy speed: %d\n", priv->phy->speed); 701 return -EINVAL; 702 } 703 704 if (pdata->bus_id) 705 rk_clrsetreg(&grf->soc_con[1], RK3562_GMAC1_CLK_RMII_DIV_MASK, div); 706 else 707 rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_CLK_RGMII_DIV_MASK, div); 708 709 return 0; 710 } 711 712 static int rk3576_set_rgmii_speed(struct gmac_rockchip_platdata *pdata, 713 struct rockchip_eth_dev *dev) 714 { 715 struct eqos_priv *priv = &dev->eqos; 716 struct rk3576_sdgmac_grf_reg *s_grf; 717 unsigned int div, div_mask; 718 719 enum { 720 RK3576_GMAC_CLK_RGMII_DIV_MASK = GENMASK(6, 5), 721 RK3576_GMAC_CLK_RGMII_DIV1 = 0, 722 RK3576_GMAC_CLK_RGMII_DIV5 = GENMASK(6, 5), 723 RK3576_GMAC_CLK_RGMII_DIV50 = BIT(6), 724 RK3576_GMAC_CLK_RMII_DIV2 = BIT(5), 725 RK3576_GMAC_CLK_RMII_DIV20 = 0, 726 }; 727 728 s_grf = syscon_get_first_range(ROCKCHIP_SYSCON_SDGMAC_GRF); 729 730 switch (priv->phy->speed) { 731 case 10: 732 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) 733 div = RK3576_GMAC_CLK_RMII_DIV20; 734 else 735 div = RK3576_GMAC_CLK_RGMII_DIV50; 736 break; 737 case 100: 738 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) 739 div = RK3576_GMAC_CLK_RMII_DIV2; 740 else 741 div = RK3576_GMAC_CLK_RGMII_DIV5; 742 break; 743 case 1000: 744 if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII) 745 div = RK3576_GMAC_CLK_RGMII_DIV1; 746 else 747 return -EINVAL; 748 break; 749 default: 750 debug("Unknown phy speed: %d\n", priv->phy->speed); 751 return -EINVAL; 752 } 753 754 div_mask = RK3576_GMAC_CLK_RGMII_DIV_MASK; 755 756 if (pdata->bus_id == 1) 757 rk_clrsetreg(&s_grf->gmac1_con, div_mask, div); 758 else 759 rk_clrsetreg(&s_grf->gmac0_con, div_mask, div); 760 761 return 0; 762 } 763 764 static int rk3588_set_rgmii_speed(struct gmac_rockchip_platdata *pdata, 765 struct rockchip_eth_dev *dev) 766 { 767 struct eqos_priv *priv = &dev->eqos; 768 struct rk3588_php_grf *php_grf; 769 unsigned int div, div_mask; 770 771 enum { 772 RK3588_GMAC_CLK_RGMII_DIV_SHIFT = 2, 773 RK3588_GMAC_CLK_RGMII_DIV_MASK = GENMASK(3, 2), 774 RK3588_GMAC_CLK_RGMII_DIV1 = 0, 775 RK3588_GMAC_CLK_RGMII_DIV5 = GENMASK(3, 2), 776 RK3588_GMAC_CLK_RGMII_DIV50 = BIT(3), 777 RK3588_GMAC_CLK_RMII_DIV2 = BIT(2), 778 RK3588_GMAC_CLK_RMII_DIV20 = 0, 779 RK3588_GMAC1_ID_SHIFT = 5, 780 }; 781 782 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 783 784 switch (priv->phy->speed) { 785 case 10: 786 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) 787 div = RK3588_GMAC_CLK_RMII_DIV20; 788 else 789 div = RK3588_GMAC_CLK_RGMII_DIV50; 790 break; 791 case 100: 792 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) 793 div = RK3588_GMAC_CLK_RMII_DIV2; 794 else 795 div = RK3588_GMAC_CLK_RGMII_DIV5; 796 break; 797 case 1000: 798 if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII) 799 div = RK3588_GMAC_CLK_RGMII_DIV1; 800 else 801 return -EINVAL; 802 break; 803 default: 804 debug("Unknown phy speed: %d\n", priv->phy->speed); 805 return -EINVAL; 806 } 807 808 if (pdata->bus_id == 1) { 809 div <<= 5; 810 div_mask = RK3588_GMAC_CLK_RGMII_DIV_MASK << 5; 811 } 812 813 div <<= pdata->bus_id ? RK3588_GMAC1_ID_SHIFT : 0; 814 div_mask = pdata->bus_id ? (RK3588_GMAC_CLK_RGMII_DIV_MASK << 5) : 815 RK3588_GMAC_CLK_RGMII_DIV_MASK; 816 817 rk_clrsetreg(&php_grf->clk_con1, div_mask, div); 818 819 return 0; 820 } 821 822 static int rv1106_set_rmii_speed(struct gmac_rockchip_platdata *pdata, 823 struct rockchip_eth_dev *dev) 824 { 825 struct eqos_priv *priv = &dev->eqos; 826 #ifdef CONFIG_ROCKCHIP_RV1103B 827 struct rv1103b_grf *grf; 828 #else 829 struct rv1106_grf *grf; 830 #endif 831 unsigned int div; 832 833 enum { 834 RV1106_GMAC_CLK_RMII_DIV_SHIFT = 2, 835 RV1106_GMAC_CLK_RMII_DIV_MASK = GENMASK(3, 2), 836 RV1106_GMAC_CLK_RMII_DIV2 = BIT(2), 837 RV1106_GMAC_CLK_RMII_DIV20 = 0, 838 }; 839 840 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 841 842 switch (priv->phy->speed) { 843 case 10: 844 div = RV1106_GMAC_CLK_RMII_DIV20; 845 break; 846 case 100: 847 div = RV1106_GMAC_CLK_RMII_DIV2; 848 break; 849 default: 850 debug("Unknown phy speed: %d\n", priv->phy->speed); 851 return -EINVAL; 852 } 853 854 rk_clrsetreg(&grf->gmac_clk_con, RV1106_GMAC_CLK_RMII_DIV_MASK, div); 855 856 return 0; 857 } 858 859 static int rv1126_set_rgmii_speed(struct gmac_rockchip_platdata *pdata, 860 struct rockchip_eth_dev *dev) 861 { 862 struct eqos_priv *priv = &dev->eqos; 863 struct clk clk_speed; 864 int ret; 865 866 ret = clk_get_by_name(priv->phy->dev, "clk_mac_speed", 867 &clk_speed); 868 if (ret) { 869 printf("%s can't get clk_mac_speed clock (ret=%d):\n", 870 __func__, ret); 871 return ret; 872 } 873 874 switch ( priv->phy->speed) { 875 case 10: 876 ret = clk_set_rate(&clk_speed, 2500000); 877 if (ret) 878 return ret; 879 break; 880 case 100: 881 ret = clk_set_rate(&clk_speed, 25000000); 882 if (ret) 883 return ret; 884 break; 885 case 1000: 886 ret = clk_set_rate(&clk_speed, 125000000); 887 if (ret) 888 return ret; 889 break; 890 default: 891 debug("Unknown phy speed: %d\n", priv->phy->speed); 892 return -EINVAL; 893 } 894 895 return 0; 896 } 897 898 static int rv1126b_set_rgmii_speed(struct gmac_rockchip_platdata *pdata, 899 struct rockchip_eth_dev *dev) 900 { 901 struct eqos_priv *priv = &dev->eqos; 902 struct rv1126b_vi_grf_reg *grf; 903 unsigned int div; 904 905 enum { 906 RV1126B_GMAC_CLK_RMII_DIV2 = BIT(5), 907 RV1126B_GMAC_CLK_RMII_DIV20 = 0, 908 RV1126B_GMAC_CLK_RMII_DIV_MASK = GENMASK(6, 5), 909 RV1126B_GMAC_CLK_RGMII_DIV1 = 0, 910 RV1126B_GMAC_CLK_RGMII_DIV5 = BIT(5) | BIT(6), 911 RV1126B_GMAC_CLK_RGMII_DIV50 = BIT(6), 912 }; 913 914 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 915 916 switch (priv->phy->speed) { 917 case 10: 918 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) 919 div = RV1126B_GMAC_CLK_RMII_DIV20; 920 else 921 div = RV1126B_GMAC_CLK_RGMII_DIV50; 922 break; 923 case 100: 924 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) 925 div = RV1126B_GMAC_CLK_RMII_DIV2; 926 else 927 div = RV1126B_GMAC_CLK_RGMII_DIV5; 928 break; 929 case 1000: 930 if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII) 931 div = RV1126B_GMAC_CLK_RGMII_DIV1; 932 else 933 return -EINVAL; 934 break; 935 default: 936 debug("Unknown phy speed: %d\n", priv->phy->speed); 937 return -EINVAL; 938 } 939 940 rk_clrsetreg(&grf->gmac_grf_con0 + (0x50000 / 4), RV1126B_GMAC_CLK_RMII_DIV_MASK, div); 941 942 return 0; 943 } 944 #endif 945 946 #ifndef CONFIG_DWC_ETH_QOS 947 static void px30_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 948 { 949 struct px30_grf *grf; 950 enum { 951 px30_GMAC_PHY_INTF_SEL_SHIFT = 4, 952 px30_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 6), 953 px30_GMAC_PHY_INTF_SEL_RMII = BIT(6), 954 }; 955 956 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 957 958 rk_clrsetreg(&grf->mac_con1, 959 px30_GMAC_PHY_INTF_SEL_MASK, 960 px30_GMAC_PHY_INTF_SEL_RMII); 961 } 962 963 static void rk1808_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 964 { 965 struct rk1808_grf *grf; 966 enum { 967 RK1808_GMAC_PHY_INTF_SEL_SHIFT = 4, 968 RK1808_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 969 RK1808_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 970 971 RK1808_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 972 RK1808_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 973 RK1808_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 974 975 RK1808_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 976 RK1808_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 977 RK1808_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 978 }; 979 enum { 980 RK1808_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 981 RK1808_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 7), 982 983 RK1808_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 984 RK1808_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 985 }; 986 987 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 988 rk_clrsetreg(&grf->mac_con1, 989 RK1808_GMAC_PHY_INTF_SEL_MASK | 990 RK1808_RXCLK_DLY_ENA_GMAC_MASK | 991 RK1808_TXCLK_DLY_ENA_GMAC_MASK, 992 RK1808_GMAC_PHY_INTF_SEL_RGMII | 993 RK1808_RXCLK_DLY_ENA_GMAC_ENABLE | 994 RK1808_TXCLK_DLY_ENA_GMAC_ENABLE); 995 996 rk_clrsetreg(&grf->mac_con0, 997 RK1808_CLK_RX_DL_CFG_GMAC_MASK | 998 RK1808_CLK_TX_DL_CFG_GMAC_MASK, 999 (pdata->rx_delay << RK1808_CLK_RX_DL_CFG_GMAC_SHIFT) | 1000 (pdata->tx_delay << RK1808_CLK_TX_DL_CFG_GMAC_SHIFT)); 1001 } 1002 1003 static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1004 { 1005 struct rk322x_grf *grf; 1006 enum { 1007 RK3228_RMII_MODE_SHIFT = 10, 1008 RK3228_RMII_MODE_MASK = BIT(10), 1009 1010 RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4, 1011 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1012 RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 1013 1014 RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 1015 RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 1016 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 1017 1018 RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 1019 RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 1020 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 1021 }; 1022 enum { 1023 RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 1024 RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 1025 1026 RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1027 RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 1028 }; 1029 1030 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1031 rk_clrsetreg(&grf->mac_con[1], 1032 RK3228_RMII_MODE_MASK | 1033 RK3228_GMAC_PHY_INTF_SEL_MASK | 1034 RK3228_RXCLK_DLY_ENA_GMAC_MASK | 1035 RK3228_TXCLK_DLY_ENA_GMAC_MASK, 1036 RK3228_GMAC_PHY_INTF_SEL_RGMII | 1037 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE | 1038 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE); 1039 1040 rk_clrsetreg(&grf->mac_con[0], 1041 RK3228_CLK_RX_DL_CFG_GMAC_MASK | 1042 RK3228_CLK_TX_DL_CFG_GMAC_MASK, 1043 pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT | 1044 pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT); 1045 } 1046 1047 static void rk3228_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1048 { 1049 struct rk322x_grf *grf; 1050 enum { 1051 RK3228_GRF_CON_RMII_MODE_MASK = BIT(11), 1052 RK3228_GRF_CON_RMII_MODE_SEL = BIT(11), 1053 RK3228_RMII_MODE_MASK = BIT(10), 1054 RK3228_RMII_MODE_SEL = BIT(10), 1055 RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1056 RK3228_GMAC_PHY_INTF_SEL_RMII = BIT(6), 1057 }; 1058 1059 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1060 rk_clrsetreg(&grf->mac_con[1], 1061 RK3228_GRF_CON_RMII_MODE_MASK | 1062 RK3228_RMII_MODE_MASK | 1063 RK3228_GMAC_PHY_INTF_SEL_MASK, 1064 RK3228_GRF_CON_RMII_MODE_SEL | 1065 RK3228_RMII_MODE_SEL | 1066 RK3228_GMAC_PHY_INTF_SEL_RMII); 1067 } 1068 1069 static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1070 { 1071 struct rk3288_grf *grf; 1072 1073 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1074 rk_clrsetreg(&grf->soc_con1, 1075 RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK, 1076 RK3288_GMAC_PHY_INTF_SEL_RGMII); 1077 1078 rk_clrsetreg(&grf->soc_con3, 1079 RK3288_RXCLK_DLY_ENA_GMAC_MASK | 1080 RK3288_TXCLK_DLY_ENA_GMAC_MASK | 1081 RK3288_CLK_RX_DL_CFG_GMAC_MASK | 1082 RK3288_CLK_TX_DL_CFG_GMAC_MASK, 1083 RK3288_RXCLK_DLY_ENA_GMAC_ENABLE | 1084 RK3288_TXCLK_DLY_ENA_GMAC_ENABLE | 1085 pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT | 1086 pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT); 1087 } 1088 1089 static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1090 { 1091 struct rk3308_grf *grf; 1092 enum { 1093 RK3308_GMAC_PHY_INTF_SEL_SHIFT = 2, 1094 RK3308_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 2), 1095 RK3308_GMAC_PHY_INTF_SEL_RMII = BIT(4), 1096 }; 1097 1098 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1099 1100 rk_clrsetreg(&grf->mac_con0, 1101 RK3308_GMAC_PHY_INTF_SEL_MASK, 1102 RK3308_GMAC_PHY_INTF_SEL_RMII); 1103 } 1104 1105 static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1106 { 1107 struct rk3328_grf_regs *grf; 1108 enum { 1109 RK3328_RMII_MODE_SHIFT = 9, 1110 RK3328_RMII_MODE_MASK = BIT(9), 1111 1112 RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4, 1113 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1114 RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 1115 1116 RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 1117 RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 1118 RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 1119 1120 RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 1121 RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 1122 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 1123 }; 1124 enum { 1125 RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 1126 RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 1127 1128 RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1129 RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 1130 }; 1131 1132 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1133 rk_clrsetreg(&grf->mac_con[1], 1134 RK3328_RMII_MODE_MASK | 1135 RK3328_GMAC_PHY_INTF_SEL_MASK | 1136 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 1137 RK3328_TXCLK_DLY_ENA_GMAC_MASK, 1138 RK3328_GMAC_PHY_INTF_SEL_RGMII | 1139 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 1140 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE); 1141 1142 rk_clrsetreg(&grf->mac_con[0], 1143 RK3328_CLK_RX_DL_CFG_GMAC_MASK | 1144 RK3328_CLK_TX_DL_CFG_GMAC_MASK, 1145 pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT | 1146 pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT); 1147 } 1148 1149 static void rk3328_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1150 { 1151 struct rk3328_grf_regs *grf; 1152 enum { 1153 RK3328_RMII_MODE_MASK = BIT(9), 1154 RK3328_RMII_MODE = BIT(9), 1155 1156 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1157 RK3328_GMAC_PHY_INTF_SEL_RMII = BIT(6), 1158 }; 1159 1160 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1161 rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1], 1162 RK3328_RMII_MODE_MASK | 1163 RK3328_GMAC_PHY_INTF_SEL_MASK, 1164 RK3328_GMAC_PHY_INTF_SEL_RMII | 1165 RK3328_RMII_MODE); 1166 } 1167 1168 static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1169 { 1170 struct rk3368_grf *grf; 1171 enum { 1172 RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9, 1173 RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9), 1174 RK3368_RMII_MODE_MASK = BIT(6), 1175 RK3368_RMII_MODE = BIT(6), 1176 }; 1177 enum { 1178 RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15), 1179 RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 1180 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15), 1181 RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7), 1182 RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 1183 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7), 1184 RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8, 1185 RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 1186 RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0, 1187 RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 1188 }; 1189 1190 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1191 rk_clrsetreg(&grf->soc_con15, 1192 RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK, 1193 RK3368_GMAC_PHY_INTF_SEL_RGMII); 1194 1195 rk_clrsetreg(&grf->soc_con16, 1196 RK3368_RXCLK_DLY_ENA_GMAC_MASK | 1197 RK3368_TXCLK_DLY_ENA_GMAC_MASK | 1198 RK3368_CLK_RX_DL_CFG_GMAC_MASK | 1199 RK3368_CLK_TX_DL_CFG_GMAC_MASK, 1200 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE | 1201 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE | 1202 (pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT) | 1203 (pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT)); 1204 } 1205 1206 static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1207 { 1208 struct rk3399_grf_regs *grf; 1209 1210 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1211 1212 rk_clrsetreg(&grf->soc_con5, 1213 RK3399_GMAC_PHY_INTF_SEL_MASK, 1214 RK3399_GMAC_PHY_INTF_SEL_RGMII); 1215 1216 rk_clrsetreg(&grf->soc_con6, 1217 RK3399_RXCLK_DLY_ENA_GMAC_MASK | 1218 RK3399_TXCLK_DLY_ENA_GMAC_MASK | 1219 RK3399_CLK_RX_DL_CFG_GMAC_MASK | 1220 RK3399_CLK_TX_DL_CFG_GMAC_MASK, 1221 RK3399_RXCLK_DLY_ENA_GMAC_ENABLE | 1222 RK3399_TXCLK_DLY_ENA_GMAC_ENABLE | 1223 (pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT) | 1224 (pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT)); 1225 } 1226 1227 static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1228 { 1229 struct rv1108_grf *grf; 1230 1231 enum { 1232 RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1233 RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4, 1234 }; 1235 1236 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1237 rk_clrsetreg(&grf->gmac_con0, 1238 RV1108_GMAC_PHY_INTF_SEL_MASK, 1239 RV1108_GMAC_PHY_INTF_SEL_RMII); 1240 } 1241 1242 static void rk3228_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 1243 { 1244 struct rk322x_grf *grf; 1245 enum { 1246 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK = BIT(15), 1247 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY = BIT(15), 1248 }; 1249 enum { 1250 RK3228_MACPHY_CFG_CLK_50M_MASK = BIT(14), 1251 RK3228_MACPHY_CFG_CLK_50M = BIT(14), 1252 1253 RK3228_MACPHY_RMII_MODE_MASK = GENMASK(7, 6), 1254 RK3228_MACPHY_RMII_MODE = BIT(6), 1255 1256 RK3228_MACPHY_ENABLE_MASK = BIT(0), 1257 RK3228_MACPHY_DISENABLE = 0, 1258 RK3228_MACPHY_ENABLE = BIT(0), 1259 }; 1260 enum { 1261 RK3228_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0), 1262 RK3228_RK_GRF_CON2_MACPHY_ID = 0x1234, 1263 }; 1264 enum { 1265 RK3228_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0), 1266 RK3228_RK_GRF_CON3_MACPHY_ID = 0x35, 1267 }; 1268 1269 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1270 rk_clrsetreg(&grf->con_iomux, 1271 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK, 1272 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY); 1273 1274 rk_clrsetreg(&grf->macphy_con[2], 1275 RK3228_RK_GRF_CON2_MACPHY_ID_MASK, 1276 RK3228_RK_GRF_CON2_MACPHY_ID); 1277 1278 rk_clrsetreg(&grf->macphy_con[3], 1279 RK3228_RK_GRF_CON3_MACPHY_ID_MASK, 1280 RK3228_RK_GRF_CON3_MACPHY_ID); 1281 1282 /* disabled before trying to reset it &*/ 1283 rk_clrsetreg(&grf->macphy_con[0], 1284 RK3228_MACPHY_CFG_CLK_50M_MASK | 1285 RK3228_MACPHY_RMII_MODE_MASK | 1286 RK3228_MACPHY_ENABLE_MASK, 1287 RK3228_MACPHY_CFG_CLK_50M | 1288 RK3228_MACPHY_RMII_MODE | 1289 RK3228_MACPHY_DISENABLE); 1290 1291 reset_assert(&pdata->phy_reset); 1292 udelay(10); 1293 reset_deassert(&pdata->phy_reset); 1294 udelay(10); 1295 1296 rk_clrsetreg(&grf->macphy_con[0], 1297 RK3228_MACPHY_ENABLE_MASK, 1298 RK3228_MACPHY_ENABLE); 1299 udelay(30 * 1000); 1300 } 1301 1302 static void rk3328_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 1303 { 1304 struct rk3328_grf_regs *grf; 1305 enum { 1306 RK3328_GRF_CON_RMII_MODE_MASK = BIT(9), 1307 RK3328_GRF_CON_RMII_MODE = BIT(9), 1308 }; 1309 enum { 1310 RK3328_MACPHY_CFG_CLK_50M_MASK = BIT(14), 1311 RK3328_MACPHY_CFG_CLK_50M = BIT(14), 1312 1313 RK3328_MACPHY_RMII_MODE_MASK = GENMASK(7, 6), 1314 RK3328_MACPHY_RMII_MODE = BIT(6), 1315 1316 RK3328_MACPHY_ENABLE_MASK = BIT(0), 1317 RK3328_MACPHY_DISENABLE = 0, 1318 RK3328_MACPHY_ENABLE = BIT(0), 1319 }; 1320 enum { 1321 RK3328_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0), 1322 RK3328_RK_GRF_CON2_MACPHY_ID = 0x1234, 1323 }; 1324 enum { 1325 RK3328_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0), 1326 RK3328_RK_GRF_CON3_MACPHY_ID = 0x35, 1327 }; 1328 1329 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1330 rk_clrsetreg(&grf->macphy_con[1], 1331 RK3328_GRF_CON_RMII_MODE_MASK, 1332 RK3328_GRF_CON_RMII_MODE); 1333 1334 rk_clrsetreg(&grf->macphy_con[2], 1335 RK3328_RK_GRF_CON2_MACPHY_ID_MASK, 1336 RK3328_RK_GRF_CON2_MACPHY_ID); 1337 1338 rk_clrsetreg(&grf->macphy_con[3], 1339 RK3328_RK_GRF_CON3_MACPHY_ID_MASK, 1340 RK3328_RK_GRF_CON3_MACPHY_ID); 1341 1342 /* disabled before trying to reset it &*/ 1343 rk_clrsetreg(&grf->macphy_con[0], 1344 RK3328_MACPHY_CFG_CLK_50M_MASK | 1345 RK3328_MACPHY_RMII_MODE_MASK | 1346 RK3328_MACPHY_ENABLE_MASK, 1347 RK3328_MACPHY_CFG_CLK_50M | 1348 RK3328_MACPHY_RMII_MODE | 1349 RK3328_MACPHY_DISENABLE); 1350 1351 reset_assert(&pdata->phy_reset); 1352 udelay(10); 1353 reset_deassert(&pdata->phy_reset); 1354 udelay(10); 1355 1356 rk_clrsetreg(&grf->macphy_con[0], 1357 RK3328_MACPHY_ENABLE_MASK, 1358 RK3328_MACPHY_ENABLE); 1359 udelay(30 * 1000); 1360 } 1361 1362 #else 1363 static void rk3506_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1364 { 1365 unsigned int clk_mode; 1366 struct rk3506_grf_reg *grf; 1367 1368 enum { 1369 RK3506_GMAC_CLK_RMII_MODE_SHIFT = 0x1, 1370 RK3506_GMAC_CLK_RMII_MODE_MASK = BIT(1), 1371 RK3506_GMAC_CLK_RMII_MODE = BIT(1), 1372 }; 1373 1374 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1375 clk_mode = RK3506_GMAC_CLK_RMII_MODE; 1376 1377 if (pdata->bus_id == 1) 1378 rk_clrsetreg(&grf->soc_con11, RK3506_GMAC_CLK_RMII_MODE_MASK, clk_mode); 1379 else 1380 rk_clrsetreg(&grf->soc_con8, RK3506_GMAC_CLK_RMII_MODE_MASK, clk_mode); 1381 } 1382 1383 static void rk3528_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 1384 { 1385 struct rk3528_grf *grf; 1386 unsigned char bgs[1] = {0}; 1387 1388 enum { 1389 RK3528_MACPHY_ENABLE_MASK = BIT(1), 1390 RK3528_MACPHY_DISENABLE = BIT(1), 1391 RK3528_MACPHY_ENABLE = 0, 1392 RK3528_MACPHY_XMII_SEL_MASK = GENMASK(6, 5), 1393 RK3528_MACPHY_XMII_SEL = BIT(6), 1394 RK3528_MACPHY_24M_CLK_SEL_MASK = GENMASK(9, 7), 1395 RK3528_MACPHY_24M_CLK_SEL_24M = (BIT(8) | BIT(9)), 1396 RK3528_MACPHY_PHY_ID_MASK = GENMASK(14, 10), 1397 RK3528_MACPHY_PHY_ID = BIT(11), 1398 }; 1399 1400 enum { 1401 RK3528_MACPHY_BGS_MASK = GENMASK(3, 0), 1402 }; 1403 1404 #if defined(CONFIG_ROCKCHIP_EFUSE) || defined(CONFIG_ROCKCHIP_OTP) 1405 struct udevice *dev; 1406 u32 regs[2] = {0}; 1407 ofnode node; 1408 int ret = 0; 1409 1410 /* retrieve the device */ 1411 if (IS_ENABLED(CONFIG_ROCKCHIP_EFUSE)) 1412 ret = uclass_get_device_by_driver(UCLASS_MISC, 1413 DM_GET_DRIVER(rockchip_efuse), 1414 &dev); 1415 else 1416 ret = uclass_get_device_by_driver(UCLASS_MISC, 1417 DM_GET_DRIVER(rockchip_otp), 1418 &dev); 1419 if (!ret) { 1420 node = dev_read_subnode(dev, "macphy-bgs"); 1421 if (ofnode_valid(node)) { 1422 if (!ofnode_read_u32_array(node, "reg", regs, 2)) { 1423 /* read the bgs from the efuses */ 1424 ret = misc_read(dev, regs[0], &bgs, 1); 1425 if (ret) { 1426 printf("read bgs from efuse/otp failed, ret=%d\n", 1427 ret); 1428 bgs[0] = 0; 1429 } 1430 } 1431 } 1432 } 1433 #endif 1434 1435 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1436 1437 reset_assert(&pdata->phy_reset); 1438 udelay(20); 1439 rk_clrsetreg(&grf->macphy_con0, 1440 RK3528_MACPHY_ENABLE_MASK | 1441 RK3528_MACPHY_XMII_SEL_MASK | 1442 RK3528_MACPHY_24M_CLK_SEL_MASK | 1443 RK3528_MACPHY_PHY_ID_MASK, 1444 RK3528_MACPHY_ENABLE | 1445 RK3528_MACPHY_XMII_SEL | 1446 RK3528_MACPHY_24M_CLK_SEL_24M | 1447 RK3528_MACPHY_PHY_ID); 1448 1449 rk_clrsetreg(&grf->macphy_con1, 1450 RK3528_MACPHY_BGS_MASK, 1451 bgs[0]); 1452 udelay(20); 1453 reset_deassert(&pdata->phy_reset); 1454 udelay(30 * 1000); 1455 } 1456 1457 static void rk3528_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1458 { 1459 unsigned int clk_mode; 1460 struct rk3528_grf *grf; 1461 1462 enum { 1463 RK3528_GMAC0_CLK_RMII_MODE_SHIFT = 0x1, 1464 RK3528_GMAC0_CLK_RMII_MODE_MASK = BIT(1), 1465 RK3528_GMAC0_CLK_RMII_MODE = 0x1, 1466 }; 1467 1468 enum { 1469 RK3528_GMAC1_CLK_RMII_MODE_SHIFT = 0x8, 1470 RK3528_GMAC1_CLK_RMII_MODE_MASK = BIT(8), 1471 RK3528_GMAC1_CLK_RMII_MODE = 0x1, 1472 }; 1473 1474 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1475 1476 if (pdata->bus_id == 1) { 1477 clk_mode = RK3528_GMAC1_CLK_RMII_MODE << RK3528_GMAC1_CLK_RMII_MODE_SHIFT; 1478 rk_clrsetreg(&grf->gmac1_con1, RK3528_GMAC1_CLK_RMII_MODE_MASK, clk_mode); 1479 } else { 1480 clk_mode = RK3528_GMAC0_CLK_RMII_MODE << RK3528_GMAC0_CLK_RMII_MODE_SHIFT; 1481 rk_clrsetreg(&grf->gmac0_con, RK3528_GMAC0_CLK_RMII_MODE_MASK, clk_mode); 1482 } 1483 } 1484 1485 static void rk3528_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1486 { 1487 unsigned int rx_enable; 1488 unsigned int rx_delay; 1489 struct rk3528_grf *grf; 1490 1491 enum { 1492 RK3528_GMAC1_RGMII_MODE_SHIFT = 0x8, 1493 RK3528_GMAC1_RGMII_MODE_MASK = BIT(8), 1494 RK3528_GMAC1_RGMII_MODE = 0x0, 1495 1496 RK3528_GMAC1_TXCLK_DLY_ENA_MASK = BIT(14), 1497 RK3528_GMAC1_TXCLK_DLY_ENA_DISABLE = 0, 1498 RK3528_GMAC1_TXCLK_DLY_ENA_ENABLE = BIT(14), 1499 1500 RK3528_GMAC1_RXCLK_DLY_ENA_MASK = BIT(15), 1501 RK3528_GMAC1_RXCLK_DLY_ENA_DISABLE = 0, 1502 RK3528_GMAC1_RXCLK_DLY_ENA_ENABLE = BIT(15), 1503 }; 1504 1505 enum { 1506 RK3528_GMAC1_RX_DL_CFG_SHIFT = 0x8, 1507 RK3528_GMAC1_RX_DL_CFG_MASK = GENMASK(15, 8), 1508 1509 RK3528_GMAC1_TX_DL_CFG_SHIFT = 0x0, 1510 RK3528_GMAC1_TX_DL_CFG_MASK = GENMASK(7, 0), 1511 }; 1512 1513 if (!pdata->bus_id) 1514 return; 1515 1516 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1517 1518 if (pdata->rx_delay < 0) { 1519 rx_enable = RK3528_GMAC1_RXCLK_DLY_ENA_DISABLE; 1520 rx_delay = 0; 1521 } else { 1522 rx_enable = RK3528_GMAC1_RXCLK_DLY_ENA_ENABLE; 1523 rx_delay = pdata->rx_delay << RK3528_GMAC1_RX_DL_CFG_SHIFT; 1524 } 1525 1526 rk_clrsetreg(&grf->gmac1_con0, 1527 RK3528_GMAC1_TXCLK_DLY_ENA_MASK | 1528 RK3528_GMAC1_RXCLK_DLY_ENA_MASK | 1529 RK3528_GMAC1_RGMII_MODE_MASK, 1530 rx_enable | RK3528_GMAC1_TXCLK_DLY_ENA_ENABLE | 1531 (RK3528_GMAC1_RGMII_MODE << RK3528_GMAC1_RGMII_MODE_SHIFT)); 1532 1533 rk_clrsetreg(&grf->gmac1_con1, 1534 RK3528_GMAC1_RX_DL_CFG_MASK | 1535 RK3528_GMAC1_TX_DL_CFG_MASK, 1536 (pdata->tx_delay << RK3528_GMAC1_TX_DL_CFG_SHIFT) | 1537 rx_delay); 1538 } 1539 1540 static void rk3562_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1541 { 1542 struct rk3562_grf *grf; 1543 unsigned int mode; 1544 1545 enum { 1546 RK3562_GMAC0_RMII_MODE_SHIFT = 0x5, 1547 RK3562_GMAC0_RMII_MODE_MASK = BIT(5), 1548 RK3562_GMAC0_RMII_MODE = 0x1, 1549 }; 1550 1551 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1552 1553 if (!pdata->bus_id) { 1554 mode = RK3562_GMAC0_RMII_MODE << RK3562_GMAC0_RMII_MODE_SHIFT; 1555 rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_RMII_MODE_MASK, mode); 1556 } 1557 } 1558 1559 static void rk3562_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1560 { 1561 struct rk3562_grf *grf; 1562 struct rk3562_ioc *ioc; 1563 unsigned int rx_enable; 1564 unsigned int rx_delay; 1565 1566 enum { 1567 RK3562_GMAC0_RGMII_MODE_SHIFT = 0x5, 1568 RK3562_GMAC0_RGMII_MODE_MASK = BIT(5), 1569 RK3562_GMAC0_RGMII_MODE = 0x0, 1570 1571 RK3562_GMAC0_TXCLK_DLY_ENA_MASK = BIT(0), 1572 RK3562_GMAC0_TXCLK_DLY_ENA_DISABLE = 0, 1573 RK3562_GMAC0_TXCLK_DLY_ENA_ENABLE = BIT(0), 1574 1575 RK3562_GMAC0_RXCLK_DLY_ENA_MASK = BIT(1), 1576 RK3562_GMAC0_RXCLK_DLY_ENA_DISABLE = 0, 1577 RK3562_GMAC0_RXCLK_DLY_ENA_ENABLE = BIT(1), 1578 }; 1579 1580 enum { 1581 RK3562_GMAC0_RX_DL_CFG_SHIFT = 0x8, 1582 RK3562_GMAC0_RX_DL_CFG_MASK = GENMASK(15, 8), 1583 1584 RK3562_GMAC0_TX_DL_CFG_SHIFT = 0x0, 1585 RK3562_GMAC0_TX_DL_CFG_MASK = GENMASK(7, 0), 1586 }; 1587 1588 if (pdata->bus_id) 1589 return; 1590 1591 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1592 ioc = syscon_get_first_range(ROCKCHIP_SYSCON_IOC); 1593 1594 rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_RGMII_MODE_MASK, 1595 RK3562_GMAC0_RGMII_MODE << RK3562_GMAC0_RGMII_MODE_SHIFT); 1596 1597 if (pdata->rx_delay < 0) { 1598 rx_enable = RK3562_GMAC0_RXCLK_DLY_ENA_DISABLE; 1599 rx_delay = 0; 1600 } else { 1601 rx_enable = RK3562_GMAC0_RXCLK_DLY_ENA_ENABLE; 1602 rx_delay = pdata->rx_delay << RK3562_GMAC0_RX_DL_CFG_SHIFT; 1603 } 1604 1605 rk_clrsetreg(&ioc->mac0_io_con1, 1606 RK3562_GMAC0_TXCLK_DLY_ENA_MASK | 1607 RK3562_GMAC0_RXCLK_DLY_ENA_MASK, 1608 rx_enable | RK3562_GMAC0_TXCLK_DLY_ENA_ENABLE); 1609 1610 rk_clrsetreg(&ioc->mac0_io_con0, 1611 RK3562_GMAC0_RX_DL_CFG_MASK | 1612 RK3562_GMAC0_TX_DL_CFG_MASK, 1613 (pdata->tx_delay << RK3562_GMAC0_TX_DL_CFG_SHIFT) | 1614 rx_delay); 1615 1616 rk_clrsetreg(&ioc->mac1_io_con1, 1617 RK3562_GMAC0_TXCLK_DLY_ENA_MASK | 1618 RK3562_GMAC0_RXCLK_DLY_ENA_MASK, 1619 rx_enable | RK3562_GMAC0_TXCLK_DLY_ENA_ENABLE); 1620 1621 rk_clrsetreg(&ioc->mac1_io_con0, 1622 RK3562_GMAC0_RX_DL_CFG_MASK | 1623 RK3562_GMAC0_TX_DL_CFG_MASK, 1624 (pdata->tx_delay << RK3562_GMAC0_TX_DL_CFG_SHIFT) | 1625 rx_delay); 1626 } 1627 1628 static void rk3568_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1629 { 1630 struct rk3568_grf *grf; 1631 void *con1; 1632 1633 enum { 1634 RK3568_GMAC_PHY_INTF_SEL_SHIFT = 4, 1635 RK3568_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1636 RK3568_GMAC_PHY_INTF_SEL_RMII = BIT(6), 1637 }; 1638 1639 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1640 1641 if (pdata->bus_id == 1) 1642 con1 = &grf->mac1_con1; 1643 else 1644 con1 = &grf->mac0_con1; 1645 1646 rk_clrsetreg(con1, 1647 RK3568_GMAC_PHY_INTF_SEL_MASK, 1648 RK3568_GMAC_PHY_INTF_SEL_RMII); 1649 } 1650 1651 static void rk3568_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1652 { 1653 struct rk3568_grf *grf; 1654 void *con0, *con1; 1655 1656 enum { 1657 RK3568_GMAC_PHY_INTF_SEL_SHIFT = 4, 1658 RK3568_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 1659 RK3568_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 1660 1661 RK3568_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 1662 RK3568_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 1663 RK3568_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 1664 1665 RK3568_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 1666 RK3568_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 1667 RK3568_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 1668 }; 1669 1670 enum { 1671 RK3568_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1672 RK3568_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 8), 1673 1674 RK3568_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1675 RK3568_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 1676 }; 1677 1678 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1679 1680 if (pdata->bus_id == 1) { 1681 con0 = &grf->mac1_con0; 1682 con1 = &grf->mac1_con1; 1683 } else { 1684 con0 = &grf->mac0_con0; 1685 con1 = &grf->mac0_con1; 1686 } 1687 1688 rk_clrsetreg(con0, 1689 RK3568_CLK_RX_DL_CFG_GMAC_MASK | 1690 RK3568_CLK_TX_DL_CFG_GMAC_MASK, 1691 (pdata->rx_delay << RK3568_CLK_RX_DL_CFG_GMAC_SHIFT) | 1692 (pdata->tx_delay << RK3568_CLK_TX_DL_CFG_GMAC_SHIFT)); 1693 1694 rk_clrsetreg(con1, 1695 RK3568_TXCLK_DLY_ENA_GMAC_MASK | 1696 RK3568_RXCLK_DLY_ENA_GMAC_MASK | 1697 RK3568_GMAC_PHY_INTF_SEL_MASK, 1698 RK3568_TXCLK_DLY_ENA_GMAC_ENABLE | 1699 RK3568_RXCLK_DLY_ENA_GMAC_ENABLE | 1700 RK3568_GMAC_PHY_INTF_SEL_RGMII); 1701 } 1702 1703 static void rk3576_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1704 { 1705 unsigned int clk_mode, clk_mode_mask; 1706 struct rk3576_sdgmac_grf_reg *s_grf; 1707 1708 enum { 1709 RK3576_GMAC_RMII_MODE_MASK = BIT(3), 1710 RK3576_GMAC_RMII_MODE = 0x1, 1711 }; 1712 1713 s_grf = syscon_get_first_range(ROCKCHIP_SYSCON_SDGMAC_GRF); 1714 1715 clk_mode = RK3576_GMAC_RMII_MODE; 1716 clk_mode_mask = RK3576_GMAC_RMII_MODE_MASK; 1717 1718 if (pdata->bus_id == 1) 1719 rk_clrsetreg(&s_grf->gmac1_con, clk_mode_mask, clk_mode); 1720 else 1721 rk_clrsetreg(&s_grf->gmac0_con, clk_mode_mask, clk_mode); 1722 } 1723 1724 static void rk3576_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1725 { 1726 struct rk3576_sdgmac_grf_reg *s_grf; 1727 struct rk3576_vccio_ioc_reg *ioc; 1728 unsigned int clk_mode, clk_mode_mask; 1729 unsigned int rx_enable, tx_enable; 1730 void *offset_con; 1731 1732 enum { 1733 RK3576_GMAC_RXCLK_DLY_DISABLE = 0, 1734 RK3576_GMAC_RXCLK_DLY_ENABLE = BIT(15), 1735 1736 RK3576_GMAC_TXCLK_DLY_DISABLE = 0, 1737 RK3576_GMAC_TXCLK_DLY_ENABLE = BIT(7), 1738 }; 1739 1740 enum { 1741 RK3576_GMAC_CLK_RGMII_MODE_MASK = BIT(3), 1742 RK3576_GMAC_CLK_RGMII_MODE = 0x0, 1743 }; 1744 1745 ioc = syscon_get_first_range(ROCKCHIP_SYSCON_IOC); 1746 s_grf = syscon_get_first_range(ROCKCHIP_SYSCON_SDGMAC_GRF); 1747 1748 if (pdata->rx_delay < 0) 1749 rx_enable = RK3576_GMAC_RXCLK_DLY_DISABLE; 1750 else 1751 rx_enable = RK3576_GMAC_RXCLK_DLY_ENABLE; 1752 1753 clk_mode = RK3576_GMAC_CLK_RGMII_MODE; 1754 clk_mode_mask = RK3576_GMAC_CLK_RGMII_MODE_MASK; 1755 tx_enable = RK3576_GMAC_TXCLK_DLY_ENABLE; 1756 1757 if (pdata->bus_id == 1) { 1758 offset_con = &ioc->misc_con[4]; 1759 offset_con += 0x6000; 1760 rk_clrsetreg(&s_grf->gmac1_con, clk_mode_mask, clk_mode); 1761 1762 } else { 1763 offset_con = &ioc->misc_con[2]; 1764 offset_con += 0x6000; 1765 rk_clrsetreg(&s_grf->gmac0_con, clk_mode_mask, clk_mode); 1766 } 1767 1768 rk_setreg(offset_con, tx_enable | rx_enable); 1769 rk_setreg(offset_con + 0x4, tx_enable | rx_enable); 1770 rk_setreg(offset_con, DELAY_VALUE(RK3576, pdata->tx_delay, pdata->rx_delay)); 1771 rk_setreg(offset_con + 0X4, DELAY_VALUE(RK3576, pdata->tx_delay, pdata->rx_delay)); 1772 } 1773 1774 static void rk3588_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1775 { 1776 unsigned int intf_sel, intf_sel_mask; 1777 unsigned int clk_mode, clk_mode_mask; 1778 struct rk3588_php_grf *php_grf; 1779 1780 enum { 1781 RK3588_GMAC_PHY_INTF_SEL_SHIFT = 3, 1782 RK3588_GMAC_PHY_INTF_SEL_MASK = GENMASK(5, 3), 1783 RK3588_GMAC_PHY_INTF_SEL_RMII = BIT(5), 1784 }; 1785 1786 enum { 1787 RK3588_GMAC_CLK_RMII_MODE_SHIFT = 0x0, 1788 RK3588_GMAC_CLK_RMII_MODE_MASK = BIT(0), 1789 RK3588_GMAC_CLK_RMII_MODE = 0x1, 1790 }; 1791 1792 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 1793 1794 if (pdata->bus_id == 1) { 1795 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RMII << 6; 1796 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK << 6; 1797 clk_mode = RK3588_GMAC_CLK_RMII_MODE << 5; 1798 clk_mode_mask = RK3588_GMAC_CLK_RMII_MODE_MASK << 5; 1799 } else { 1800 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RMII; 1801 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK; 1802 clk_mode = RK3588_GMAC_CLK_RMII_MODE; 1803 clk_mode_mask = RK3588_GMAC_CLK_RMII_MODE_MASK; 1804 } 1805 1806 rk_clrsetreg(&php_grf->gmac_con0, intf_sel_mask, intf_sel); 1807 rk_clrsetreg(&php_grf->clk_con1, clk_mode_mask, clk_mode); 1808 } 1809 1810 static void rk3588_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 1811 { 1812 unsigned int rx_enable, rx_enable_mask, tx_enable, tx_enable_mask; 1813 unsigned int intf_sel, intf_sel_mask; 1814 unsigned int clk_mode, clk_mode_mask; 1815 unsigned int rx_delay; 1816 struct rk3588_php_grf *php_grf; 1817 struct rk3588_sys_grf *grf; 1818 void *offset_con; 1819 1820 enum { 1821 RK3588_GMAC_PHY_INTF_SEL_SHIFT = 3, 1822 RK3588_GMAC_PHY_INTF_SEL_MASK = GENMASK(5, 3), 1823 RK3588_GMAC_PHY_INTF_SEL_RGMII = BIT(3), 1824 1825 RK3588_RXCLK_DLY_ENA_GMAC_MASK = BIT(3), 1826 RK3588_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 1827 RK3588_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(3), 1828 1829 RK3588_TXCLK_DLY_ENA_GMAC_MASK = BIT(2), 1830 RK3588_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 1831 RK3588_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(2), 1832 }; 1833 1834 enum { 1835 RK3588_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 1836 RK3588_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 8), 1837 1838 RK3588_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1839 RK3588_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0), 1840 }; 1841 1842 enum { 1843 RK3588_GMAC_CLK_RGMII_MODE_SHIFT = 0x0, 1844 RK3588_GMAC_CLK_RGMII_MODE_MASK = BIT(0), 1845 RK3588_GMAC_CLK_RGMII_MODE = 0x0, 1846 }; 1847 1848 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1849 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 1850 1851 if (pdata->rx_delay < 0) { 1852 rx_enable = RK3588_RXCLK_DLY_ENA_GMAC_DISABLE; 1853 rx_delay = 0; 1854 } else { 1855 rx_enable = RK3588_RXCLK_DLY_ENA_GMAC_ENABLE; 1856 rx_delay = pdata->rx_delay << RK3588_CLK_RX_DL_CFG_GMAC_SHIFT; 1857 } 1858 1859 if (pdata->bus_id == 1) { 1860 offset_con = &grf->soc_con9; 1861 rx_enable = rx_delay << 2; 1862 rx_enable_mask = RK3588_RXCLK_DLY_ENA_GMAC_MASK << 2; 1863 tx_enable = RK3588_TXCLK_DLY_ENA_GMAC_ENABLE << 2; 1864 tx_enable_mask = RK3588_TXCLK_DLY_ENA_GMAC_MASK << 2; 1865 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RGMII << 6; 1866 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK << 6; 1867 clk_mode = RK3588_GMAC_CLK_RGMII_MODE << 5; 1868 clk_mode_mask = RK3588_GMAC_CLK_RGMII_MODE_MASK << 5; 1869 } else { 1870 offset_con = &grf->soc_con8; 1871 rx_enable_mask = RK3588_RXCLK_DLY_ENA_GMAC_MASK; 1872 tx_enable = RK3588_TXCLK_DLY_ENA_GMAC_ENABLE; 1873 tx_enable_mask = RK3588_TXCLK_DLY_ENA_GMAC_MASK; 1874 intf_sel = RK3588_GMAC_PHY_INTF_SEL_RGMII; 1875 intf_sel_mask = RK3588_GMAC_PHY_INTF_SEL_MASK; 1876 clk_mode = RK3588_GMAC_CLK_RGMII_MODE; 1877 clk_mode_mask = RK3588_GMAC_CLK_RGMII_MODE_MASK; 1878 } 1879 1880 rk_clrsetreg(offset_con, 1881 RK3588_CLK_TX_DL_CFG_GMAC_MASK | 1882 RK3588_CLK_RX_DL_CFG_GMAC_MASK, 1883 (pdata->tx_delay << RK3588_CLK_TX_DL_CFG_GMAC_SHIFT) | 1884 rx_delay); 1885 1886 rk_clrsetreg(&grf->soc_con7, tx_enable_mask | rx_enable_mask, 1887 tx_enable | rx_enable); 1888 1889 rk_clrsetreg(&php_grf->gmac_con0, intf_sel_mask, intf_sel); 1890 rk_clrsetreg(&php_grf->clk_con1, clk_mode_mask, clk_mode); 1891 } 1892 1893 static void rv1103b_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1894 { 1895 struct rv1103b_grf *grf; 1896 enum { 1897 RV1103B_SYSGRF_GMAC_CLK_RMII_50M_MASK = BIT(2), 1898 RV1103B_SYSGRF_GMAC_CLK_RMII_50M = BIT(2), 1899 }; 1900 1901 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1902 rk_clrsetreg(&grf->gmac_clk_con, 1903 RV1103B_SYSGRF_GMAC_CLK_RMII_50M_MASK, 1904 RV1103B_SYSGRF_GMAC_CLK_RMII_50M); 1905 }; 1906 1907 static void rv1106_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 1908 { 1909 #ifdef CONFIG_ROCKCHIP_RV1103B 1910 struct rv1103b_grf *grf; 1911 #else 1912 struct rv1106_grf *grf; 1913 #endif 1914 unsigned char bgs[1] = {0}; 1915 1916 enum { 1917 RV1106_VOGRF_GMAC_CLK_RMII_MODE_MASK = BIT(0), 1918 RV1106_VOGRF_GMAC_CLK_RMII_MODE = BIT(0), 1919 }; 1920 1921 enum { 1922 RV1106_MACPHY_ENABLE_MASK = BIT(1), 1923 RV1106_MACPHY_DISENABLE = BIT(1), 1924 RV1106_MACPHY_ENABLE = 0, 1925 RV1106_MACPHY_XMII_SEL_MASK = GENMASK(6, 5), 1926 RV1106_MACPHY_XMII_SEL = BIT(6), 1927 RV1106_MACPHY_24M_CLK_SEL_MASK = GENMASK(9, 7), 1928 RV1106_MACPHY_24M_CLK_SEL_24M = (BIT(8) | BIT(9)), 1929 RV1106_MACPHY_PHY_ID_MASK = GENMASK(14, 10), 1930 RV1106_MACPHY_PHY_ID = BIT(11), 1931 }; 1932 1933 enum { 1934 RV1106_MACPHY_BGS_MASK = GENMASK(3, 0), 1935 RV1106_MACPHY_BGS = BIT(2), 1936 }; 1937 1938 #if defined(CONFIG_ROCKCHIP_EFUSE) || defined(CONFIG_ROCKCHIP_OTP) 1939 struct udevice *dev; 1940 u32 regs[2] = {0}; 1941 ofnode node; 1942 int ret = 0; 1943 1944 /* retrieve the device */ 1945 if (IS_ENABLED(CONFIG_ROCKCHIP_EFUSE)) 1946 ret = uclass_get_device_by_driver(UCLASS_MISC, 1947 DM_GET_DRIVER(rockchip_efuse), 1948 &dev); 1949 else 1950 ret = uclass_get_device_by_driver(UCLASS_MISC, 1951 DM_GET_DRIVER(rockchip_otp), 1952 &dev); 1953 if (!ret) { 1954 node = dev_read_subnode(dev, "macphy-bgs"); 1955 if (ofnode_valid(node)) { 1956 if (!ofnode_read_u32_array(node, "reg", regs, 2)) { 1957 /* read the bgs from the efuses */ 1958 ret = misc_read(dev, regs[0], &bgs, 1); 1959 if (ret) { 1960 printf("read bgs from efuse/otp failed, ret=%d\n", 1961 ret); 1962 bgs[0] = 0; 1963 } 1964 } 1965 } 1966 } 1967 #endif 1968 1969 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1970 1971 reset_assert(&pdata->phy_reset); 1972 udelay(20); 1973 rk_clrsetreg(&grf->macphy_con0, 1974 RV1106_MACPHY_ENABLE_MASK | 1975 RV1106_MACPHY_XMII_SEL_MASK | 1976 RV1106_MACPHY_24M_CLK_SEL_MASK | 1977 RV1106_MACPHY_PHY_ID_MASK, 1978 RV1106_MACPHY_ENABLE | 1979 RV1106_MACPHY_XMII_SEL | 1980 RV1106_MACPHY_24M_CLK_SEL_24M | 1981 RV1106_MACPHY_PHY_ID); 1982 1983 rk_clrsetreg(&grf->macphy_con1, 1984 RV1106_MACPHY_BGS_MASK, 1985 bgs[0]); 1986 udelay(20); 1987 reset_deassert(&pdata->phy_reset); 1988 udelay(30 * 1000); 1989 } 1990 1991 static void rv1106_set_to_rmii(struct gmac_rockchip_platdata *pdata) 1992 { 1993 struct rv1106_grf *grf; 1994 enum { 1995 RV1106_VOGRF_GMAC_CLK_RMII_MODE_MASK = BIT(0), 1996 RV1106_VOGRF_GMAC_CLK_RMII_MODE = BIT(0), 1997 }; 1998 1999 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 2000 rk_clrsetreg(&grf->gmac_clk_con, 2001 RV1106_VOGRF_GMAC_CLK_RMII_MODE_MASK, 2002 RV1106_VOGRF_GMAC_CLK_RMII_MODE); 2003 }; 2004 2005 static void rv1126_set_to_rmii(struct gmac_rockchip_platdata *pdata) 2006 { 2007 struct rv1126_grf *grf; 2008 2009 enum { 2010 RV1126_GMAC_PHY_INTF_SEL_SHIFT = 4, 2011 RV1126_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 2012 RV1126_GMAC_PHY_INTF_SEL_RMII = BIT(6), 2013 }; 2014 2015 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 2016 2017 rk_clrsetreg(&grf->mac_con0, 2018 RV1126_GMAC_PHY_INTF_SEL_MASK, 2019 RV1126_GMAC_PHY_INTF_SEL_RMII); 2020 } 2021 2022 static void rv1126_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 2023 { 2024 struct rv1126_grf *grf; 2025 2026 enum { 2027 RV1126_GMAC_PHY_INTF_SEL_SHIFT = 4, 2028 RV1126_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 2029 RV1126_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 2030 2031 RV1126_RXCLK_M1_DLY_ENA_GMAC_MASK = BIT(3), 2032 RV1126_RXCLK_M1_DLY_ENA_GMAC_DISABLE = 0, 2033 RV1126_RXCLK_M1_DLY_ENA_GMAC_ENABLE = BIT(3), 2034 2035 RV1126_TXCLK_M1_DLY_ENA_GMAC_MASK = BIT(2), 2036 RV1126_TXCLK_M1_DLY_ENA_GMAC_DISABLE = 0, 2037 RV1126_TXCLK_M1_DLY_ENA_GMAC_ENABLE = BIT(2), 2038 2039 RV1126_RXCLK_M0_DLY_ENA_GMAC_MASK = BIT(1), 2040 RV1126_RXCLK_M0_DLY_ENA_GMAC_DISABLE = 0, 2041 RV1126_RXCLK_M0_DLY_ENA_GMAC_ENABLE = BIT(1), 2042 2043 RV1126_TXCLK_M0_DLY_ENA_GMAC_MASK = BIT(0), 2044 RV1126_TXCLK_M0_DLY_ENA_GMAC_DISABLE = 0, 2045 RV1126_TXCLK_M0_DLY_ENA_GMAC_ENABLE = BIT(0), 2046 }; 2047 enum { 2048 RV1126_M0_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 2049 RV1126_M0_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 2050 2051 RV1126_M0_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 2052 RV1126_M0_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 2053 }; 2054 enum { 2055 RV1126_M1_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8, 2056 RV1126_M1_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 2057 2058 RV1126_M1_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 2059 RV1126_M1_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 2060 }; 2061 2062 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 2063 2064 rk_clrsetreg(&grf->mac_con0, 2065 RV1126_TXCLK_M0_DLY_ENA_GMAC_MASK | 2066 RV1126_RXCLK_M0_DLY_ENA_GMAC_MASK | 2067 RV1126_TXCLK_M1_DLY_ENA_GMAC_MASK | 2068 RV1126_RXCLK_M1_DLY_ENA_GMAC_MASK | 2069 RV1126_GMAC_PHY_INTF_SEL_MASK, 2070 RV1126_TXCLK_M0_DLY_ENA_GMAC_ENABLE | 2071 RV1126_RXCLK_M0_DLY_ENA_GMAC_ENABLE | 2072 RV1126_TXCLK_M1_DLY_ENA_GMAC_ENABLE | 2073 RV1126_RXCLK_M1_DLY_ENA_GMAC_ENABLE | 2074 RV1126_GMAC_PHY_INTF_SEL_RGMII); 2075 2076 rk_clrsetreg(&grf->mac_con1, 2077 RV1126_M0_CLK_RX_DL_CFG_GMAC_MASK | 2078 RV1126_M0_CLK_TX_DL_CFG_GMAC_MASK, 2079 (pdata->rx_delay << RV1126_M0_CLK_RX_DL_CFG_GMAC_SHIFT) | 2080 (pdata->tx_delay << RV1126_M0_CLK_TX_DL_CFG_GMAC_SHIFT)); 2081 2082 rk_clrsetreg(&grf->mac_con2, 2083 RV1126_M1_CLK_RX_DL_CFG_GMAC_MASK | 2084 RV1126_M1_CLK_TX_DL_CFG_GMAC_MASK, 2085 (pdata->rx_delay << RV1126_M1_CLK_RX_DL_CFG_GMAC_SHIFT) | 2086 (pdata->tx_delay << RV1126_M1_CLK_TX_DL_CFG_GMAC_SHIFT)); 2087 } 2088 2089 static void rv1126b_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) 2090 { 2091 struct rv1126b_vi_grf_reg *grf; 2092 unsigned int value; 2093 2094 enum { 2095 RV1126B_MACPHY_PHY_ID_SHIFT = 5, 2096 RV1126B_MACPHY_PHY_ADDR_SHIFT = 0, 2097 }; 2098 2099 enum { 2100 RV1126B_MACPHY_ENABLE_SHIFT = 31, 2101 RV1126B_MACPHY_PHY_REVISION_SHIFT = 6, 2102 RV1126B_MACPHY_PHY_MODEL_SHIFT = 0, 2103 }; 2104 2105 enum { 2106 RV1126B_MACPHY_EXTCLK_SEL_INPUT = 0, 2107 RV1126B_MACPHY_EXTCLK_SEL_OUTPUT = (1 << 8), 2108 RV1126B_MACPHY_CLK_SEL_24M = 0, 2109 RV1126B_MACPHY_CLK_SEL_50M = (1 << 11), 2110 }; 2111 2112 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 2113 2114 writel(0, &grf->rkmacphy_grf_con1 + (0x50000 / 4)); 2115 reset_assert(&pdata->phy_reset); 2116 udelay(20); 2117 value = RV1126B_MACPHY_CLK_SEL_24M; 2118 if (pdata->clock_input) 2119 value |= RV1126B_MACPHY_EXTCLK_SEL_INPUT; 2120 else 2121 value |= RV1126B_MACPHY_EXTCLK_SEL_OUTPUT; 2122 writel(value, &grf->rkmacphy_grf_con2 + (0x50000 / 4)); 2123 2124 value = (0x200680 << RV1126B_MACPHY_PHY_ID_SHIFT) | 2125 (0x2 << RV1126B_MACPHY_PHY_ADDR_SHIFT); 2126 writel(value, &grf->rkmacphy_grf_con0 + (0x50000 / 4)); 2127 2128 value = (0x10 << RV1126B_MACPHY_PHY_MODEL_SHIFT) | 2129 (0x1 << RV1126B_MACPHY_PHY_REVISION_SHIFT) | 2130 (0x1 << RV1126B_MACPHY_ENABLE_SHIFT); 2131 writel(value, &grf->rkmacphy_grf_con1 + (0x50000 / 4)); 2132 udelay(100); 2133 reset_deassert(&pdata->phy_reset); 2134 } 2135 2136 static void rv1126b_set_to_rmii(struct gmac_rockchip_platdata *pdata) 2137 { 2138 struct rv1126b_vi_grf_reg *grf; 2139 2140 enum { 2141 RV1126B_GMAC_CLK_RMII_MODE_MASK = BIT(3), 2142 RV1126B_GMAC_CLK_RMII_MODE = BIT(3), 2143 RV1126B_GMAC_RK_MACPHY_ENABLE_MASK = BIT(15), 2144 RV1126B_GMAC_RK_MACPHY_ENABLE = BIT(15), 2145 }; 2146 2147 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 2148 2149 if (pdata->integrated_phy) 2150 rk_clrsetreg(&grf->gmac_grf_con0 + (0x50000 / 4), 2151 RV1126B_GMAC_RK_MACPHY_ENABLE_MASK, 2152 RV1126B_GMAC_RK_MACPHY_ENABLE); 2153 2154 rk_clrsetreg(&grf->gmac_grf_con0 + (0x50000 / 4), 2155 RV1126B_GMAC_CLK_RMII_MODE_MASK, 2156 RV1126B_GMAC_CLK_RMII_MODE); 2157 }; 2158 2159 static void rv1126b_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 2160 { 2161 struct rv1126b_vi_grf_reg *grf; 2162 struct rv1126b_vccio5_ioc_reg *ioc0; 2163 struct rv1126b_vccio6_ioc_reg *ioc1; 2164 unsigned int rx_enable; 2165 unsigned int rx_delay; 2166 2167 enum { 2168 RV1126B_GMAC_RGMII_MODE_MASK = BIT(3), 2169 RV1126B_GMAC_RGMII_MODE = 0x0, 2170 }; 2171 2172 enum { 2173 RV1126B_GMAC_TXCLK_DLY_ENA_MASK = BIT(0), 2174 RV1126B_GMAC_TXCLK_DLY_ENA_DISABLE = 0, 2175 RV1126B_GMAC_TXCLK_DLY_ENA_ENABLE = BIT(0), 2176 2177 RV1126B_GMAC_RXCLK_DLY_ENA_MASK = BIT(1), 2178 RV1126B_GMAC_RXCLK_DLY_ENA_DISABLE = 0, 2179 RV1126B_GMAC_RXCLK_DLY_ENA_ENABLE = BIT(1), 2180 }; 2181 2182 enum { 2183 RV1126B_GMAC_RX_DL_CFG_SHIFT = 0x8, 2184 RV1126B_GMAC_RX_DL_CFG_MASK = GENMASK(15, 8), 2185 2186 RV1126B_GMAC_TX_DL_CFG_SHIFT = 0x0, 2187 RV1126B_GMAC_TX_DL_CFG_MASK = GENMASK(7, 0), 2188 }; 2189 2190 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 2191 ioc0 = syscon_get_first_range(ROCKCHIP_SYSCON_IOC); 2192 ioc1 = syscon_get_first_range(ROCKCHIP_SYSCON_IOC); 2193 2194 rk_clrsetreg(&grf->gmac_grf_con0 + (0x50000 / 4), 2195 RV1126B_GMAC_RGMII_MODE_MASK, 2196 RV1126B_GMAC_RGMII_MODE); 2197 2198 if (pdata->rx_delay < 0) { 2199 rx_enable = RV1126B_GMAC_RXCLK_DLY_ENA_DISABLE; 2200 rx_delay = 0; 2201 } else { 2202 rx_enable = RV1126B_GMAC_RXCLK_DLY_ENA_ENABLE; 2203 rx_delay = pdata->rx_delay << RV1126B_GMAC_RX_DL_CFG_SHIFT; 2204 } 2205 2206 rk_clrsetreg(&ioc1->grf_gmacio_m0_con1 + (0x38000 / 4), 2207 RV1126B_GMAC_TXCLK_DLY_ENA_MASK | 2208 RV1126B_GMAC_RXCLK_DLY_ENA_MASK, 2209 rx_enable | RV1126B_GMAC_TXCLK_DLY_ENA_ENABLE); 2210 2211 rk_clrsetreg(&ioc0->grf_gmacio_m1_con1 + (0x30000 / 4), 2212 RV1126B_GMAC_TXCLK_DLY_ENA_MASK | 2213 RV1126B_GMAC_RXCLK_DLY_ENA_MASK, 2214 rx_enable | RV1126B_GMAC_TXCLK_DLY_ENA_ENABLE); 2215 2216 rk_clrsetreg(&ioc1->grf_gmacio_m0_con0 + (0x38000 / 4), 2217 RV1126B_GMAC_RX_DL_CFG_MASK | 2218 RV1126B_GMAC_TX_DL_CFG_MASK, 2219 (pdata->tx_delay << RV1126B_GMAC_TX_DL_CFG_SHIFT) | 2220 rx_delay); 2221 2222 rk_clrsetreg(&ioc0->grf_gmacio_m1_con0 + (0x30000 / 4), 2223 RV1126B_GMAC_RX_DL_CFG_MASK | 2224 RV1126B_GMAC_TX_DL_CFG_MASK, 2225 (pdata->tx_delay << RV1126B_GMAC_TX_DL_CFG_SHIFT) | 2226 rx_delay); 2227 } 2228 #endif 2229 2230 #ifdef CONFIG_DWC_ETH_QOS 2231 static void rk3506_set_clock_selection(struct gmac_rockchip_platdata *pdata) 2232 { 2233 struct rk3506_grf_reg *grf; 2234 unsigned int val; 2235 2236 enum { 2237 RK3506_GMAC_CLK_SELET_SHIFT = 5, 2238 RK3506_GMAC_CLK_SELET_MASK = BIT(5), 2239 RK3506_GMAC_CLK_SELET_CRU = 0, 2240 RK3506_GMAC_CLK_SELET_IO = BIT(5), 2241 }; 2242 2243 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 2244 2245 val = pdata->clock_input ? RK3506_GMAC_CLK_SELET_IO : 2246 RK3506_GMAC_CLK_SELET_CRU; 2247 2248 if (pdata->bus_id) 2249 rk_clrsetreg(&grf->soc_con11, RK3506_GMAC_CLK_SELET_MASK, val); 2250 else 2251 rk_clrsetreg(&grf->soc_con8, RK3506_GMAC_CLK_SELET_MASK, val); 2252 } 2253 2254 static void rk3528_set_clock_selection(struct gmac_rockchip_platdata *pdata) 2255 { 2256 struct rk3528_grf *grf; 2257 unsigned int val; 2258 2259 enum { 2260 RK3528_GMAC1_CLK_SELET_SHIFT = 0x12, 2261 RK3528_GMAC1_CLK_SELET_MASK = BIT(12), 2262 RK3528_GMAC1_CLK_SELET_CRU = 0, 2263 RK3528_GMAC1_CLK_SELET_IO = BIT(12), 2264 }; 2265 2266 if (!pdata->bus_id) 2267 return; 2268 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 2269 2270 val = pdata->clock_input ? RK3528_GMAC1_CLK_SELET_IO : 2271 RK3528_GMAC1_CLK_SELET_CRU; 2272 rk_clrsetreg(&grf->gmac1_con0, RK3528_GMAC1_CLK_SELET_MASK, val); 2273 } 2274 2275 static void rk3562_set_clock_selection(struct gmac_rockchip_platdata *pdata) 2276 { 2277 struct rk3562_grf *grf; 2278 struct rk3562_ioc *ioc; 2279 unsigned int val; 2280 2281 enum { 2282 RK3562_GMAC0_CLK_SELET_SHIFT = 0x9, 2283 RK3562_GMAC0_CLK_SELET_MASK = BIT(9), 2284 RK3562_GMAC0_CLK_SELET_CRU = 0, 2285 RK3562_GMAC0_CLK_SELET_IO = BIT(9), 2286 }; 2287 2288 enum { 2289 RK3562_GMAC1_CLK_SELET_SHIFT = 15, 2290 RK3562_GMAC1_CLK_SELET_MASK = BIT(15), 2291 RK3562_GMAC1_CLK_SELET_CRU = 0, 2292 RK3562_GMAC1_CLK_SELET_IO = BIT(15), 2293 }; 2294 2295 enum { 2296 RK3562_GMAC0_IO_EXTCLK_SELET_SHIFT = 0x2, 2297 RK3562_GMAC0_IO_EXTCLK_SELET_MASK = BIT(2), 2298 RK3562_GMAC0_IO_EXTCLK_SELET_CRU = 0, 2299 RK3562_GMAC0_IO_EXTCLK_SELET_IO = BIT(2), 2300 }; 2301 2302 enum { 2303 RK3562_GMAC1_IO_EXTCLK_SELET_SHIFT = 0x3, 2304 RK3562_GMAC1_IO_EXTCLK_SELET_MASK = BIT(3), 2305 RK3562_GMAC1_IO_EXTCLK_SELET_CRU = 0, 2306 RK3562_GMAC1_IO_EXTCLK_SELET_IO = BIT(3), 2307 }; 2308 2309 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 2310 ioc = syscon_get_first_range(ROCKCHIP_SYSCON_IOC); 2311 2312 if (!pdata->bus_id) { 2313 val = pdata->clock_input ? RK3562_GMAC0_CLK_SELET_IO : 2314 RK3562_GMAC0_CLK_SELET_CRU; 2315 rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_CLK_SELET_MASK, val); 2316 val = pdata->clock_input ? RK3562_GMAC0_IO_EXTCLK_SELET_IO : 2317 RK3562_GMAC0_IO_EXTCLK_SELET_CRU; 2318 rk_clrsetreg(&ioc->mac1_io_con1, 2319 RK3562_GMAC0_IO_EXTCLK_SELET_MASK, val); 2320 rk_clrsetreg(&ioc->mac0_io_con1, 2321 RK3562_GMAC0_IO_EXTCLK_SELET_MASK, val); 2322 2323 } else { 2324 val = pdata->clock_input ? RK3562_GMAC1_CLK_SELET_IO : 2325 RK3562_GMAC1_CLK_SELET_CRU; 2326 rk_clrsetreg(&grf->soc_con[1], RK3562_GMAC1_CLK_SELET_MASK, val); 2327 val = pdata->clock_input ? RK3562_GMAC1_IO_EXTCLK_SELET_IO : 2328 RK3562_GMAC1_IO_EXTCLK_SELET_CRU; 2329 rk_clrsetreg(&ioc->mac1_io_con1, 2330 RK3562_GMAC1_IO_EXTCLK_SELET_MASK, val); 2331 } 2332 } 2333 2334 static void rk3576_set_clock_selection(struct gmac_rockchip_platdata *pdata) 2335 { 2336 struct rk3576_sdgmac_grf_reg *s_grf; 2337 unsigned int val, mask; 2338 2339 enum { 2340 RK3576_GMAC_CLK_SELET_MASK = BIT(7), 2341 RK3576_GMAC_CLK_SELET_CRU = 0, 2342 RK3576_GMAC_CLK_SELET_IO = BIT(7), 2343 }; 2344 2345 s_grf = syscon_get_first_range(ROCKCHIP_SYSCON_SDGMAC_GRF); 2346 val = pdata->clock_input ? RK3576_GMAC_CLK_SELET_IO : 2347 RK3576_GMAC_CLK_SELET_CRU; 2348 2349 mask = RK3576_GMAC_CLK_SELET_MASK; 2350 2351 if (pdata->bus_id == 1) 2352 rk_clrsetreg(&s_grf->gmac1_con, mask, val); 2353 else 2354 rk_clrsetreg(&s_grf->gmac0_con, mask, val); 2355 } 2356 2357 static void rk3588_set_clock_selection(struct gmac_rockchip_platdata *pdata) 2358 { 2359 struct rk3588_php_grf *php_grf; 2360 unsigned int val, mask; 2361 2362 enum { 2363 RK3588_GMAC_CLK_SELET_SHIFT = 0x4, 2364 RK3588_GMAC_CLK_SELET_MASK = BIT(4), 2365 RK3588_GMAC_CLK_SELET_CRU = BIT(4), 2366 RK3588_GMAC_CLK_SELET_IO = 0, 2367 }; 2368 2369 php_grf = syscon_get_first_range(ROCKCHIP_SYSCON_PHP_GRF); 2370 val = pdata->clock_input ? RK3588_GMAC_CLK_SELET_IO : 2371 RK3588_GMAC_CLK_SELET_CRU; 2372 mask = RK3588_GMAC_CLK_SELET_MASK; 2373 2374 if (pdata->bus_id == 1) { 2375 val <<= 5; 2376 mask <<= 5; 2377 } 2378 2379 rk_clrsetreg(&php_grf->clk_con1, mask, val); 2380 } 2381 2382 static void rv1126b_set_clock_selection(struct gmac_rockchip_platdata *pdata) 2383 { 2384 struct rv1126b_vi_grf_reg *grf; 2385 unsigned int val; 2386 2387 enum { 2388 RV1126B_GMAC_CLK_SELET_MASK = BIT(7), 2389 RV1126B_GMAC_CLK_SELET_CRU = 0, 2390 RV1126B_GMAC_CLK_SELET_IO = BIT(7), 2391 }; 2392 2393 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 2394 val = pdata->clock_input ? RV1126B_GMAC_CLK_SELET_IO : 2395 RV1126B_GMAC_CLK_SELET_CRU; 2396 2397 rk_clrsetreg(&grf->gmac_grf_con0 + (0x50000 / 4), RV1126B_GMAC_CLK_SELET_MASK, val); 2398 } 2399 #endif 2400 2401 static int gmac_rockchip_probe(struct udevice *dev) 2402 { 2403 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 2404 struct rk_gmac_ops *ops = 2405 (struct rk_gmac_ops *)dev_get_driver_data(dev); 2406 #ifdef CONFIG_DWC_ETH_QOS 2407 struct eqos_config *config; 2408 #else 2409 struct dw_eth_pdata *dw_pdata; 2410 #endif 2411 struct eth_pdata *eth_pdata; 2412 struct clk clk; 2413 ulong rate; 2414 int ret; 2415 2416 #ifdef CONFIG_DWC_ETH_QOS 2417 eth_pdata = &pdata->eth_pdata; 2418 config = (struct eqos_config *)&ops->config; 2419 memcpy(config, &eqos_rockchip_config, sizeof(struct eqos_config)); 2420 eth_pdata->phy_interface = config->ops->eqos_get_interface(dev); 2421 #else 2422 dw_pdata = &pdata->dw_eth_pdata; 2423 eth_pdata = &dw_pdata->eth_pdata; 2424 #endif 2425 pdata->bus_id = dev->seq; 2426 2427 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 2428 ret = clk_set_defaults(dev); 2429 if (ret) 2430 debug("%s clk_set_defaults failed %d\n", __func__, ret); 2431 2432 ret = clk_get_by_index(dev, 0, &clk); 2433 if (ret) 2434 debug("%s clk_get_by_index failed %d\n", __func__, ret); 2435 2436 pdata->phy_interface = eth_pdata->phy_interface; 2437 2438 if (ops->set_clock_selection) 2439 ops->set_clock_selection(pdata); 2440 2441 if (pdata->integrated_phy && ops->integrated_phy_powerup) 2442 ops->integrated_phy_powerup(pdata); 2443 2444 switch (eth_pdata->phy_interface) { 2445 case PHY_INTERFACE_MODE_RGMII: 2446 case PHY_INTERFACE_MODE_RGMII_RXID: 2447 /* 2448 * If the gmac clock is from internal pll, need to set and 2449 * check the return value for gmac clock at RGMII mode. If 2450 * the gmac clock is from external source, the clock rate 2451 * is not set, because of it is bypassed. 2452 */ 2453 if (!pdata->clock_input) { 2454 if (clk.id) { 2455 rate = clk_set_rate(&clk, 125000000); 2456 if (rate != 125000000) 2457 return -EINVAL; 2458 } 2459 } 2460 2461 if (eth_pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) 2462 pdata->rx_delay = -1; 2463 2464 /* Set to RGMII mode */ 2465 if (ops->set_to_rgmii) 2466 ops->set_to_rgmii(pdata); 2467 else 2468 return -EPERM; 2469 2470 break; 2471 case PHY_INTERFACE_MODE_RMII: 2472 /* The commet is the same as RGMII mode */ 2473 if (!pdata->clock_input) { 2474 if (clk.id) { 2475 rate = clk_set_rate(&clk, 50000000); 2476 if (rate != 50000000) 2477 return -EINVAL; 2478 } 2479 } 2480 2481 /* Set to RMII mode */ 2482 if (ops->set_to_rmii) 2483 ops->set_to_rmii(pdata); 2484 2485 break; 2486 default: 2487 debug("NO interface defined!\n"); 2488 return -ENXIO; 2489 } 2490 2491 #ifdef CONFIG_DWC_ETH_QOS 2492 return eqos_probe(dev); 2493 #else 2494 return designware_eth_probe(dev); 2495 #endif 2496 } 2497 2498 static int gmac_rockchip_eth_write_hwaddr(struct udevice *dev) 2499 { 2500 #if defined(CONFIG_DWC_ETH_QOS) 2501 return eqos_write_hwaddr(dev); 2502 #else 2503 return designware_eth_write_hwaddr(dev); 2504 #endif 2505 } 2506 2507 static int gmac_rockchip_eth_free_pkt(struct udevice *dev, uchar *packet, 2508 int length) 2509 { 2510 #ifdef CONFIG_DWC_ETH_QOS 2511 return eqos_free_pkt(dev, packet, length); 2512 #else 2513 return designware_eth_free_pkt(dev, packet, length); 2514 #endif 2515 } 2516 2517 static int gmac_rockchip_eth_send(struct udevice *dev, void *packet, 2518 int length) 2519 { 2520 #ifdef CONFIG_DWC_ETH_QOS 2521 return eqos_send(dev, packet, length); 2522 #else 2523 return designware_eth_send(dev, packet, length); 2524 #endif 2525 } 2526 2527 static int gmac_rockchip_eth_recv(struct udevice *dev, int flags, 2528 uchar **packetp) 2529 { 2530 #ifdef CONFIG_DWC_ETH_QOS 2531 return eqos_recv(dev, flags, packetp); 2532 #else 2533 return designware_eth_recv(dev, flags, packetp); 2534 #endif 2535 } 2536 2537 static int gmac_rockchip_eth_start(struct udevice *dev) 2538 { 2539 struct rockchip_eth_dev *priv = dev_get_priv(dev); 2540 struct rk_gmac_ops *ops = 2541 (struct rk_gmac_ops *)dev_get_driver_data(dev); 2542 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 2543 #ifndef CONFIG_DWC_ETH_QOS 2544 struct dw_eth_pdata *dw_pdata; 2545 struct eth_pdata *eth_pdata; 2546 #endif 2547 int ret; 2548 2549 #ifdef CONFIG_DWC_ETH_QOS 2550 ret = eqos_init(dev); 2551 #else 2552 dw_pdata = &pdata->dw_eth_pdata; 2553 eth_pdata = &dw_pdata->eth_pdata; 2554 ret = designware_eth_init((struct dw_eth_dev *)priv, 2555 eth_pdata->enetaddr); 2556 #endif 2557 if (ret) 2558 return ret; 2559 ret = ops->fix_mac_speed(pdata, priv); 2560 if (ret) 2561 return ret; 2562 2563 #ifdef CONFIG_DWC_ETH_QOS 2564 eqos_enable(dev); 2565 #else 2566 ret = designware_eth_enable((struct dw_eth_dev *)priv); 2567 if (ret) 2568 return ret; 2569 #endif 2570 2571 return 0; 2572 } 2573 2574 static void gmac_rockchip_eth_stop(struct udevice *dev) 2575 { 2576 #ifdef CONFIG_DWC_ETH_QOS 2577 eqos_stop(dev); 2578 #else 2579 designware_eth_stop(dev); 2580 #endif 2581 } 2582 2583 const struct eth_ops gmac_rockchip_eth_ops = { 2584 .start = gmac_rockchip_eth_start, 2585 .send = gmac_rockchip_eth_send, 2586 .recv = gmac_rockchip_eth_recv, 2587 .free_pkt = gmac_rockchip_eth_free_pkt, 2588 .stop = gmac_rockchip_eth_stop, 2589 .write_hwaddr = gmac_rockchip_eth_write_hwaddr, 2590 }; 2591 2592 #ifndef CONFIG_DWC_ETH_QOS 2593 const struct rk_gmac_ops px30_gmac_ops = { 2594 .fix_mac_speed = px30_gmac_fix_mac_speed, 2595 .set_to_rmii = px30_gmac_set_to_rmii, 2596 }; 2597 2598 const struct rk_gmac_ops rk1808_gmac_ops = { 2599 .fix_mac_speed = rk1808_gmac_fix_mac_speed, 2600 .set_to_rgmii = rk1808_gmac_set_to_rgmii, 2601 }; 2602 2603 const struct rk_gmac_ops rk3228_gmac_ops = { 2604 .fix_mac_speed = rk3228_gmac_fix_mac_speed, 2605 .set_to_rmii = rk3228_gmac_set_to_rmii, 2606 .set_to_rgmii = rk3228_gmac_set_to_rgmii, 2607 .integrated_phy_powerup = rk3228_gmac_integrated_phy_powerup, 2608 }; 2609 2610 const struct rk_gmac_ops rk3288_gmac_ops = { 2611 .fix_mac_speed = rk3288_gmac_fix_mac_speed, 2612 .set_to_rgmii = rk3288_gmac_set_to_rgmii, 2613 }; 2614 2615 const struct rk_gmac_ops rk3308_gmac_ops = { 2616 .fix_mac_speed = rk3308_gmac_fix_mac_speed, 2617 .set_to_rmii = rk3308_gmac_set_to_rmii, 2618 }; 2619 2620 const struct rk_gmac_ops rk3328_gmac_ops = { 2621 .fix_mac_speed = rk3328_gmac_fix_mac_speed, 2622 .set_to_rmii = rk3328_gmac_set_to_rmii, 2623 .set_to_rgmii = rk3328_gmac_set_to_rgmii, 2624 .integrated_phy_powerup = rk3328_gmac_integrated_phy_powerup, 2625 }; 2626 2627 const struct rk_gmac_ops rk3368_gmac_ops = { 2628 .fix_mac_speed = rk3368_gmac_fix_mac_speed, 2629 .set_to_rgmii = rk3368_gmac_set_to_rgmii, 2630 }; 2631 2632 const struct rk_gmac_ops rk3399_gmac_ops = { 2633 .fix_mac_speed = rk3399_gmac_fix_mac_speed, 2634 .set_to_rgmii = rk3399_gmac_set_to_rgmii, 2635 }; 2636 2637 const struct rk_gmac_ops rv1108_gmac_ops = { 2638 .fix_mac_speed = rv1108_set_rmii_speed, 2639 .set_to_rmii = rv1108_gmac_set_to_rmii, 2640 }; 2641 #else 2642 const struct rk_gmac_ops rk3506_gmac_ops = { 2643 .fix_mac_speed = rk3506_set_rmii_speed, 2644 .set_to_rmii = rk3506_set_to_rmii, 2645 .set_clock_selection = rk3506_set_clock_selection, 2646 }; 2647 2648 const struct rk_gmac_ops rk3528_gmac_ops = { 2649 .fix_mac_speed = rk3528_set_rgmii_speed, 2650 .set_to_rgmii = rk3528_set_to_rgmii, 2651 .set_to_rmii = rk3528_set_to_rmii, 2652 .set_clock_selection = rk3528_set_clock_selection, 2653 .integrated_phy_powerup = rk3528_gmac_integrated_phy_powerup, 2654 }; 2655 2656 const struct rk_gmac_ops rk3562_gmac_ops = { 2657 .fix_mac_speed = rk3562_set_gmac_speed, 2658 .set_to_rgmii = rk3562_set_to_rgmii, 2659 .set_to_rmii = rk3562_set_to_rmii, 2660 .set_clock_selection = rk3562_set_clock_selection, 2661 }; 2662 2663 const struct rk_gmac_ops rk3568_gmac_ops = { 2664 .fix_mac_speed = rv1126_set_rgmii_speed, 2665 .set_to_rgmii = rk3568_set_to_rgmii, 2666 .set_to_rmii = rk3568_set_to_rmii, 2667 }; 2668 2669 const struct rk_gmac_ops rk3576_gmac_ops = { 2670 .fix_mac_speed = rk3576_set_rgmii_speed, 2671 .set_to_rgmii = rk3576_set_to_rgmii, 2672 .set_to_rmii = rk3576_set_to_rmii, 2673 .set_clock_selection = rk3576_set_clock_selection, 2674 }; 2675 2676 const struct rk_gmac_ops rk3588_gmac_ops = { 2677 .fix_mac_speed = rk3588_set_rgmii_speed, 2678 .set_to_rgmii = rk3588_set_to_rgmii, 2679 .set_to_rmii = rk3588_set_to_rmii, 2680 .set_clock_selection = rk3588_set_clock_selection, 2681 }; 2682 2683 const struct rk_gmac_ops rv1103b_gmac_ops = { 2684 .fix_mac_speed = rv1106_set_rmii_speed, 2685 .set_to_rmii = rv1103b_set_to_rmii, 2686 .integrated_phy_powerup = rv1106_gmac_integrated_phy_powerup, 2687 }; 2688 2689 const struct rk_gmac_ops rv1106_gmac_ops = { 2690 .fix_mac_speed = rv1106_set_rmii_speed, 2691 .set_to_rmii = rv1106_set_to_rmii, 2692 .integrated_phy_powerup = rv1106_gmac_integrated_phy_powerup, 2693 }; 2694 2695 const struct rk_gmac_ops rv1126_gmac_ops = { 2696 .fix_mac_speed = rv1126_set_rgmii_speed, 2697 .set_to_rgmii = rv1126_set_to_rgmii, 2698 .set_to_rmii = rv1126_set_to_rmii, 2699 }; 2700 2701 const struct rk_gmac_ops rv1126b_gmac_ops = { 2702 .fix_mac_speed = rv1126b_set_rgmii_speed, 2703 .set_to_rgmii = rv1126b_set_to_rgmii, 2704 .set_to_rmii = rv1126b_set_to_rmii, 2705 .set_clock_selection = rv1126b_set_clock_selection, 2706 .integrated_phy_powerup = rv1126b_gmac_integrated_phy_powerup, 2707 }; 2708 #endif 2709 2710 static const struct udevice_id rockchip_gmac_ids[] = { 2711 #ifndef CONFIG_DWC_ETH_QOS 2712 #ifdef CONFIG_ROCKCHIP_PX30 2713 { .compatible = "rockchip,px30-gmac", 2714 .data = (ulong)&px30_gmac_ops }, 2715 #endif 2716 2717 #ifdef CONFIG_ROCKCHIP_RK1808 2718 { .compatible = "rockchip,rk1808-gmac", 2719 .data = (ulong)&rk1808_gmac_ops }, 2720 #endif 2721 2722 #ifdef CONFIG_ROCKCHIP_RK3228 2723 { .compatible = "rockchip,rk3228-gmac", 2724 .data = (ulong)&rk3228_gmac_ops }, 2725 #endif 2726 2727 #ifdef CONFIG_ROCKCHIP_RK3288 2728 { .compatible = "rockchip,rk3288-gmac", 2729 .data = (ulong)&rk3288_gmac_ops }, 2730 #endif 2731 2732 #ifdef CONFIG_ROCKCHIP_RK3308 2733 { .compatible = "rockchip,rk3308-mac", 2734 .data = (ulong)&rk3308_gmac_ops }, 2735 #endif 2736 2737 #ifdef CONFIG_ROCKCHIP_RK3328 2738 { .compatible = "rockchip,rk3328-gmac", 2739 .data = (ulong)&rk3328_gmac_ops }, 2740 #endif 2741 2742 #ifdef CONFIG_ROCKCHIP_RK3368 2743 { .compatible = "rockchip,rk3368-gmac", 2744 .data = (ulong)&rk3368_gmac_ops }, 2745 #endif 2746 2747 #ifdef CONFIG_ROCKCHIP_RK3399 2748 { .compatible = "rockchip,rk3399-gmac", 2749 .data = (ulong)&rk3399_gmac_ops }, 2750 #endif 2751 2752 #ifdef CONFIG_ROCKCHIP_RV1108 2753 { .compatible = "rockchip,rv1108-gmac", 2754 .data = (ulong)&rv1108_gmac_ops }, 2755 #endif 2756 #else 2757 #ifdef CONFIG_ROCKCHIP_RK3506 2758 { .compatible = "rockchip,rk3506-gmac", 2759 .data = (ulong)&rk3506_gmac_ops }, 2760 #endif 2761 2762 #ifdef CONFIG_ROCKCHIP_RK3528 2763 { .compatible = "rockchip,rk3528-gmac", 2764 .data = (ulong)&rk3528_gmac_ops }, 2765 #endif 2766 2767 #ifdef CONFIG_ROCKCHIP_RK3562 2768 { .compatible = "rockchip,rk3562-gmac", 2769 .data = (ulong)&rk3562_gmac_ops }, 2770 #endif 2771 2772 #ifdef CONFIG_ROCKCHIP_RK3568 2773 { .compatible = "rockchip,rk3568-gmac", 2774 .data = (ulong)&rk3568_gmac_ops }, 2775 #endif 2776 2777 #ifdef CONFIG_ROCKCHIP_RK3576 2778 { .compatible = "rockchip,rk3576-gmac", 2779 .data = (ulong)&rk3576_gmac_ops }, 2780 #endif 2781 2782 #ifdef CONFIG_ROCKCHIP_RK3588 2783 { .compatible = "rockchip,rk3588-gmac", 2784 .data = (ulong)&rk3588_gmac_ops }, 2785 #endif 2786 2787 #ifdef CONFIG_ROCKCHIP_RV1103B 2788 { .compatible = "rockchip,rv1103b-gmac", 2789 .data = (ulong)&rv1103b_gmac_ops }, 2790 #endif 2791 2792 #ifdef CONFIG_ROCKCHIP_RV1106 2793 { .compatible = "rockchip,rv1106-gmac", 2794 .data = (ulong)&rv1106_gmac_ops }, 2795 #endif 2796 2797 #ifdef CONFIG_ROCKCHIP_RV1126 2798 { .compatible = "rockchip,rv1126-gmac", 2799 .data = (ulong)&rv1126_gmac_ops }, 2800 #endif 2801 2802 #ifdef CONFIG_ROCKCHIP_RV1126B 2803 { .compatible = "rockchip,rv1126b-gmac", 2804 .data = (ulong)&rv1126b_gmac_ops }, 2805 #endif 2806 #endif 2807 { } 2808 }; 2809 2810 U_BOOT_DRIVER(eth_gmac_rockchip) = { 2811 .name = "gmac_rockchip", 2812 .id = UCLASS_ETH, 2813 .of_match = rockchip_gmac_ids, 2814 .ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata, 2815 .probe = gmac_rockchip_probe, 2816 .ops = &gmac_rockchip_eth_ops, 2817 .priv_auto_alloc_size = sizeof(struct rockchip_eth_dev), 2818 .platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata), 2819 .flags = DM_FLAG_ALLOC_PRIV_DMA, 2820 }; 2821