1 /* 2 * Copyright (C) 2014 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <errno.h> 7 #include <asm/io.h> 8 #include <fsl-mc/fsl_mc.h> 9 #include <fsl-mc/fsl_mc_sys.h> 10 #include <fsl-mc/fsl_mc_private.h> 11 #include <fsl-mc/fsl_dpmng.h> 12 #include <fsl-mc/fsl_dprc.h> 13 #include <fsl-mc/fsl_dpio.h> 14 #include <fsl-mc/fsl_qbman_portal.h> 15 16 #define MC_RAM_BASE_ADDR_ALIGNMENT (512UL * 1024 * 1024) 17 #define MC_RAM_BASE_ADDR_ALIGNMENT_MASK (~(MC_RAM_BASE_ADDR_ALIGNMENT - 1)) 18 #define MC_RAM_SIZE_ALIGNMENT (256UL * 1024 * 1024) 19 20 #define MC_MEM_SIZE_ENV_VAR "mcmemsize" 21 #define MC_BOOT_TIMEOUT_ENV_VAR "mcboottimeout" 22 23 DECLARE_GLOBAL_DATA_PTR; 24 static int mc_boot_status; 25 struct fsl_mc_io *dflt_mc_io = NULL; 26 uint16_t dflt_dprc_handle = 0; 27 struct fsl_dpbp_obj *dflt_dpbp = NULL; 28 struct fsl_dpio_obj *dflt_dpio = NULL; 29 uint16_t dflt_dpio_handle = 0; 30 31 #ifdef DEBUG 32 void dump_ram_words(const char *title, void *addr) 33 { 34 int i; 35 uint32_t *words = addr; 36 37 printf("Dumping beginning of %s (%p):\n", title, addr); 38 for (i = 0; i < 16; i++) 39 printf("%#x ", words[i]); 40 41 printf("\n"); 42 } 43 44 void dump_mc_ccsr_regs(struct mc_ccsr_registers __iomem *mc_ccsr_regs) 45 { 46 printf("MC CCSR registers:\n" 47 "reg_gcr1 %#x\n" 48 "reg_gsr %#x\n" 49 "reg_sicbalr %#x\n" 50 "reg_sicbahr %#x\n" 51 "reg_sicapr %#x\n" 52 "reg_mcfbalr %#x\n" 53 "reg_mcfbahr %#x\n" 54 "reg_mcfapr %#x\n" 55 "reg_psr %#x\n", 56 mc_ccsr_regs->reg_gcr1, 57 mc_ccsr_regs->reg_gsr, 58 mc_ccsr_regs->reg_sicbalr, 59 mc_ccsr_regs->reg_sicbahr, 60 mc_ccsr_regs->reg_sicapr, 61 mc_ccsr_regs->reg_mcfbalr, 62 mc_ccsr_regs->reg_mcfbahr, 63 mc_ccsr_regs->reg_mcfapr, 64 mc_ccsr_regs->reg_psr); 65 } 66 #else 67 68 #define dump_ram_words(title, addr) 69 #define dump_mc_ccsr_regs(mc_ccsr_regs) 70 71 #endif /* DEBUG */ 72 73 #ifndef CONFIG_SYS_LS_MC_FW_IN_DDR 74 /** 75 * Copying MC firmware or DPL image to DDR 76 */ 77 static int mc_copy_image(const char *title, 78 u64 image_addr, u32 image_size, u64 mc_ram_addr) 79 { 80 debug("%s copied to address %p\n", title, (void *)mc_ram_addr); 81 memcpy((void *)mc_ram_addr, (void *)image_addr, image_size); 82 flush_dcache_range(mc_ram_addr, mc_ram_addr + image_size); 83 return 0; 84 } 85 86 /** 87 * MC firmware FIT image parser checks if the image is in FIT 88 * format, verifies integrity of the image and calculates 89 * raw image address and size values. 90 * Returns 0 on success and a negative errno on error. 91 * task fail. 92 **/ 93 int parse_mc_firmware_fit_image(const void **raw_image_addr, 94 size_t *raw_image_size) 95 { 96 int format; 97 void *fit_hdr; 98 int node_offset; 99 const void *data; 100 size_t size; 101 const char *uname = "firmware"; 102 103 /* Check if the image is in NOR flash */ 104 #ifdef CONFIG_SYS_LS_MC_FW_IN_NOR 105 fit_hdr = (void *)CONFIG_SYS_LS_MC_FW_ADDR; 106 #else 107 #error "No CONFIG_SYS_LS_MC_FW_IN_xxx defined" 108 #endif 109 110 /* Check if Image is in FIT format */ 111 format = genimg_get_format(fit_hdr); 112 113 if (format != IMAGE_FORMAT_FIT) { 114 printf("fsl-mc: ERROR: Bad firmware image (not a FIT image)\n"); 115 return -EINVAL; 116 } 117 118 if (!fit_check_format(fit_hdr)) { 119 printf("fsl-mc: ERROR: Bad firmware image (bad FIT header)\n"); 120 return -EINVAL; 121 } 122 123 node_offset = fit_image_get_node(fit_hdr, uname); 124 125 if (node_offset < 0) { 126 printf("fsl-mc: ERROR: Bad firmware image (missing subimage)\n"); 127 return -ENOENT; 128 } 129 130 /* Verify MC firmware image */ 131 if (!(fit_image_verify(fit_hdr, node_offset))) { 132 printf("fsl-mc: ERROR: Bad firmware image (bad CRC)\n"); 133 return -EINVAL; 134 } 135 136 /* Get address and size of raw image */ 137 fit_image_get_data(fit_hdr, node_offset, &data, &size); 138 139 *raw_image_addr = data; 140 *raw_image_size = size; 141 142 return 0; 143 } 144 #endif 145 146 /* 147 * Calculates the values to be used to specify the address range 148 * for the MC private DRAM block, in the MCFBALR/MCFBAHR registers. 149 * It returns the highest 512MB-aligned address within the given 150 * address range, in '*aligned_base_addr', and the number of 256 MiB 151 * blocks in it, in 'num_256mb_blocks'. 152 */ 153 static int calculate_mc_private_ram_params(u64 mc_private_ram_start_addr, 154 size_t mc_ram_size, 155 u64 *aligned_base_addr, 156 u8 *num_256mb_blocks) 157 { 158 u64 addr; 159 u16 num_blocks; 160 161 if (mc_ram_size % MC_RAM_SIZE_ALIGNMENT != 0) { 162 printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n", 163 mc_ram_size); 164 return -EINVAL; 165 } 166 167 num_blocks = mc_ram_size / MC_RAM_SIZE_ALIGNMENT; 168 if (num_blocks < 1 || num_blocks > 0xff) { 169 printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n", 170 mc_ram_size); 171 return -EINVAL; 172 } 173 174 addr = (mc_private_ram_start_addr + mc_ram_size - 1) & 175 MC_RAM_BASE_ADDR_ALIGNMENT_MASK; 176 177 if (addr < mc_private_ram_start_addr) { 178 printf("fsl-mc: ERROR: bad start address %#llx\n", 179 mc_private_ram_start_addr); 180 return -EFAULT; 181 } 182 183 *aligned_base_addr = addr; 184 *num_256mb_blocks = num_blocks; 185 return 0; 186 } 187 188 static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size) 189 { 190 u64 mc_dpc_offset; 191 #ifndef CONFIG_SYS_LS_MC_DPC_IN_DDR 192 int error; 193 void *dpc_fdt_hdr; 194 int dpc_size; 195 #endif 196 197 #ifdef CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 198 BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET & 0x3) != 0 || 199 CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET > 0xffffffff); 200 201 mc_dpc_offset = CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET; 202 #else 203 #error "CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET not defined" 204 #endif 205 206 /* 207 * Load the MC DPC blob in the MC private DRAM block: 208 */ 209 #ifdef CONFIG_SYS_LS_MC_DPC_IN_DDR 210 printf("MC DPC is preloaded to %#llx\n", mc_ram_addr + mc_dpc_offset); 211 #else 212 /* 213 * Get address and size of the DPC blob stored in flash: 214 */ 215 #ifdef CONFIG_SYS_LS_MC_DPC_IN_NOR 216 dpc_fdt_hdr = (void *)CONFIG_SYS_LS_MC_DPC_ADDR; 217 #else 218 #error "No CONFIG_SYS_LS_MC_DPC_IN_xxx defined" 219 #endif 220 221 error = fdt_check_header(dpc_fdt_hdr); 222 if (error != 0) { 223 /* 224 * Don't return with error here, since the MC firmware can 225 * still boot without a DPC 226 */ 227 printf("\nfsl-mc: WARNING: No DPC image found"); 228 return 0; 229 } 230 231 dpc_size = fdt_totalsize(dpc_fdt_hdr); 232 if (dpc_size > CONFIG_SYS_LS_MC_DPC_MAX_LENGTH) { 233 printf("\nfsl-mc: ERROR: Bad DPC image (too large: %d)\n", 234 dpc_size); 235 return -EINVAL; 236 } 237 238 mc_copy_image("MC DPC blob", 239 (u64)dpc_fdt_hdr, dpc_size, mc_ram_addr + mc_dpc_offset); 240 #endif /* not defined CONFIG_SYS_LS_MC_DPC_IN_DDR */ 241 242 dump_ram_words("DPC", (void *)(mc_ram_addr + mc_dpc_offset)); 243 return 0; 244 } 245 246 static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size) 247 { 248 u64 mc_dpl_offset; 249 #ifndef CONFIG_SYS_LS_MC_DPL_IN_DDR 250 int error; 251 void *dpl_fdt_hdr; 252 int dpl_size; 253 #endif 254 255 #ifdef CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 256 BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 || 257 CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff); 258 259 mc_dpl_offset = CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET; 260 #else 261 #error "CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET not defined" 262 #endif 263 264 /* 265 * Load the MC DPL blob in the MC private DRAM block: 266 */ 267 #ifdef CONFIG_SYS_LS_MC_DPL_IN_DDR 268 printf("MC DPL is preloaded to %#llx\n", mc_ram_addr + mc_dpl_offset); 269 #else 270 /* 271 * Get address and size of the DPL blob stored in flash: 272 */ 273 #ifdef CONFIG_SYS_LS_MC_DPL_IN_NOR 274 dpl_fdt_hdr = (void *)CONFIG_SYS_LS_MC_DPL_ADDR; 275 #else 276 #error "No CONFIG_SYS_LS_MC_DPL_IN_xxx defined" 277 #endif 278 279 error = fdt_check_header(dpl_fdt_hdr); 280 if (error != 0) { 281 printf("\nfsl-mc: ERROR: Bad DPL image (bad header)\n"); 282 return error; 283 } 284 285 dpl_size = fdt_totalsize(dpl_fdt_hdr); 286 if (dpl_size > CONFIG_SYS_LS_MC_DPL_MAX_LENGTH) { 287 printf("\nfsl-mc: ERROR: Bad DPL image (too large: %d)\n", 288 dpl_size); 289 return -EINVAL; 290 } 291 292 mc_copy_image("MC DPL blob", 293 (u64)dpl_fdt_hdr, dpl_size, mc_ram_addr + mc_dpl_offset); 294 #endif /* not defined CONFIG_SYS_LS_MC_DPL_IN_DDR */ 295 296 dump_ram_words("DPL", (void *)(mc_ram_addr + mc_dpl_offset)); 297 return 0; 298 } 299 300 /** 301 * Return the MC boot timeout value in milliseconds 302 */ 303 static unsigned long get_mc_boot_timeout_ms(void) 304 { 305 unsigned long timeout_ms = CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS; 306 307 char *timeout_ms_env_var = getenv(MC_BOOT_TIMEOUT_ENV_VAR); 308 309 if (timeout_ms_env_var) { 310 timeout_ms = simple_strtoul(timeout_ms_env_var, NULL, 10); 311 if (timeout_ms == 0) { 312 printf("fsl-mc: WARNING: Invalid value for \'" 313 MC_BOOT_TIMEOUT_ENV_VAR 314 "\' environment variable: %lu\n", 315 timeout_ms); 316 317 timeout_ms = CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS; 318 } 319 } 320 321 return timeout_ms; 322 } 323 324 static int wait_for_mc(bool booting_mc, u32 *final_reg_gsr) 325 { 326 u32 reg_gsr; 327 u32 mc_fw_boot_status; 328 unsigned long timeout_ms = get_mc_boot_timeout_ms(); 329 struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR; 330 331 dmb(); 332 assert(timeout_ms > 0); 333 for (;;) { 334 udelay(1000); /* throttle polling */ 335 reg_gsr = in_le32(&mc_ccsr_regs->reg_gsr); 336 mc_fw_boot_status = (reg_gsr & GSR_FS_MASK); 337 if (mc_fw_boot_status & 0x1) 338 break; 339 340 timeout_ms--; 341 if (timeout_ms == 0) 342 break; 343 } 344 345 if (timeout_ms == 0) { 346 printf("ERROR: timeout\n"); 347 348 /* TODO: Get an error status from an MC CCSR register */ 349 return -ETIMEDOUT; 350 } 351 352 if (mc_fw_boot_status != 0x1) { 353 /* 354 * TODO: Identify critical errors from the GSR register's FS 355 * field and for those errors, set error to -ENODEV or other 356 * appropriate errno, so that the status property is set to 357 * failure in the fsl,dprc device tree node. 358 */ 359 printf("WARNING: Firmware returned an error (GSR: %#x)\n", 360 reg_gsr); 361 } else { 362 printf("SUCCESS\n"); 363 } 364 365 366 *final_reg_gsr = reg_gsr; 367 return 0; 368 } 369 370 int mc_init(void) 371 { 372 int error = 0; 373 int portal_id = 0; 374 struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR; 375 u64 mc_ram_addr; 376 u32 reg_gsr; 377 u32 reg_mcfbalr; 378 #ifndef CONFIG_SYS_LS_MC_FW_IN_DDR 379 const void *raw_image_addr; 380 size_t raw_image_size = 0; 381 #endif 382 struct mc_version mc_ver_info; 383 u64 mc_ram_aligned_base_addr; 384 u8 mc_ram_num_256mb_blocks; 385 size_t mc_ram_size = mc_get_dram_block_size(); 386 387 /* 388 * The MC private DRAM block was already carved at the end of DRAM 389 * by board_init_f() using CONFIG_SYS_MEM_TOP_HIDE: 390 */ 391 if (gd->bd->bi_dram[1].start) { 392 mc_ram_addr = 393 gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size; 394 } else { 395 mc_ram_addr = 396 gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; 397 } 398 399 error = calculate_mc_private_ram_params(mc_ram_addr, 400 mc_ram_size, 401 &mc_ram_aligned_base_addr, 402 &mc_ram_num_256mb_blocks); 403 if (error != 0) 404 goto out; 405 406 /* 407 * Management Complex cores should be held at reset out of POR. 408 * U-boot should be the first software to touch MC. To be safe, 409 * we reset all cores again by setting GCR1 to 0. It doesn't do 410 * anything if they are held at reset. After we setup the firmware 411 * we kick off MC by deasserting the reset bit for core 0, and 412 * deasserting the reset bits for Command Portal Managers. 413 * The stop bits are not touched here. They are used to stop the 414 * cores when they are active. Setting stop bits doesn't stop the 415 * cores from fetching instructions when they are released from 416 * reset. 417 */ 418 out_le32(&mc_ccsr_regs->reg_gcr1, 0); 419 dmb(); 420 421 #ifdef CONFIG_SYS_LS_MC_FW_IN_DDR 422 printf("MC firmware is preloaded to %#llx\n", mc_ram_addr); 423 #else 424 error = parse_mc_firmware_fit_image(&raw_image_addr, &raw_image_size); 425 if (error != 0) 426 goto out; 427 /* 428 * Load the MC FW at the beginning of the MC private DRAM block: 429 */ 430 mc_copy_image("MC Firmware", 431 (u64)raw_image_addr, raw_image_size, mc_ram_addr); 432 #endif 433 dump_ram_words("firmware", (void *)mc_ram_addr); 434 435 error = load_mc_dpc(mc_ram_addr, mc_ram_size); 436 if (error != 0) 437 goto out; 438 439 error = load_mc_dpl(mc_ram_addr, mc_ram_size); 440 if (error != 0) 441 goto out; 442 443 debug("mc_ccsr_regs %p\n", mc_ccsr_regs); 444 dump_mc_ccsr_regs(mc_ccsr_regs); 445 446 /* 447 * Tell MC what is the address range of the DRAM block assigned to it: 448 */ 449 reg_mcfbalr = (u32)mc_ram_aligned_base_addr | 450 (mc_ram_num_256mb_blocks - 1); 451 out_le32(&mc_ccsr_regs->reg_mcfbalr, reg_mcfbalr); 452 out_le32(&mc_ccsr_regs->reg_mcfbahr, 453 (u32)(mc_ram_aligned_base_addr >> 32)); 454 out_le32(&mc_ccsr_regs->reg_mcfapr, MCFAPR_BYPASS_ICID_MASK); 455 456 /* 457 * Tell the MC that we want delayed DPL deployment. 458 */ 459 out_le32(&mc_ccsr_regs->reg_gsr, 0xDD00); 460 461 printf("\nfsl-mc: Booting Management Complex ... "); 462 463 /* 464 * Deassert reset and release MC core 0 to run 465 */ 466 out_le32(&mc_ccsr_regs->reg_gcr1, GCR1_P1_DE_RST | GCR1_M_ALL_DE_RST); 467 error = wait_for_mc(true, ®_gsr); 468 if (error != 0) 469 goto out; 470 471 /* 472 * TODO: need to obtain the portal_id for the root container from the 473 * DPL 474 */ 475 portal_id = 0; 476 477 /* 478 * Initialize the global default MC portal 479 * And check that the MC firmware is responding portal commands: 480 */ 481 dflt_mc_io = (struct fsl_mc_io *)malloc(sizeof(struct fsl_mc_io)); 482 if (!dflt_mc_io) { 483 printf(" No memory: malloc() failed\n"); 484 return -ENOMEM; 485 } 486 487 dflt_mc_io->mmio_regs = SOC_MC_PORTAL_ADDR(portal_id); 488 debug("Checking access to MC portal of root DPRC container (portal_id %d, portal physical addr %p)\n", 489 portal_id, dflt_mc_io->mmio_regs); 490 491 error = mc_get_version(dflt_mc_io, &mc_ver_info); 492 if (error != 0) { 493 printf("fsl-mc: ERROR: Firmware version check failed (error: %d)\n", 494 error); 495 goto out; 496 } 497 498 if (MC_VER_MAJOR != mc_ver_info.major) 499 printf("fsl-mc: ERROR: Firmware major version mismatch (found: %d, expected: %d)\n", 500 mc_ver_info.major, MC_VER_MAJOR); 501 502 if (MC_VER_MINOR != mc_ver_info.minor) 503 printf("fsl-mc: WARNING: Firmware minor version mismatch (found: %d, expected: %d)\n", 504 mc_ver_info.minor, MC_VER_MINOR); 505 506 printf("fsl-mc: Management Complex booted (version: %d.%d.%d, boot status: %#x)\n", 507 mc_ver_info.major, mc_ver_info.minor, mc_ver_info.revision, 508 reg_gsr & GSR_FS_MASK); 509 510 /* 511 * Tell the MC to deploy the DPL: 512 */ 513 out_le32(&mc_ccsr_regs->reg_gsr, 0x0); 514 printf("fsl-mc: Deploying data path layout ... "); 515 error = wait_for_mc(false, ®_gsr); 516 if (error != 0) 517 goto out; 518 519 out: 520 if (error != 0) 521 mc_boot_status = -error; 522 else 523 mc_boot_status = 0; 524 525 return error; 526 } 527 528 int get_mc_boot_status(void) 529 { 530 return mc_boot_status; 531 } 532 533 /** 534 * Return the actual size of the MC private DRAM block. 535 */ 536 unsigned long mc_get_dram_block_size(void) 537 { 538 unsigned long dram_block_size = CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE; 539 540 char *dram_block_size_env_var = getenv(MC_MEM_SIZE_ENV_VAR); 541 542 if (dram_block_size_env_var) { 543 dram_block_size = simple_strtoul(dram_block_size_env_var, NULL, 544 10); 545 546 if (dram_block_size < CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE) { 547 printf("fsl-mc: WARNING: Invalid value for \'" 548 MC_MEM_SIZE_ENV_VAR 549 "\' environment variable: %lu\n", 550 dram_block_size); 551 552 dram_block_size = CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE; 553 } 554 } 555 556 return dram_block_size; 557 } 558 559 int dpio_init(struct dprc_obj_desc obj_desc) 560 { 561 struct qbman_swp_desc p_des; 562 struct dpio_attr attr; 563 int err = 0; 564 565 dflt_dpio = (struct fsl_dpio_obj *)malloc(sizeof(struct fsl_dpio_obj)); 566 if (!dflt_dpio) { 567 printf(" No memory: malloc() failed\n"); 568 return -ENOMEM; 569 } 570 571 dflt_dpio->dpio_id = obj_desc.id; 572 573 err = dpio_open(dflt_mc_io, obj_desc.id, &dflt_dpio_handle); 574 if (err) { 575 printf("dpio_open() failed\n"); 576 goto err_open; 577 } 578 579 err = dpio_get_attributes(dflt_mc_io, dflt_dpio_handle, &attr); 580 if (err) { 581 printf("dpio_get_attributes() failed %d\n", err); 582 goto err_get_attr; 583 } 584 585 err = dpio_enable(dflt_mc_io, dflt_dpio_handle); 586 if (err) { 587 printf("dpio_enable() failed %d\n", err); 588 goto err_get_enable; 589 } 590 debug("ce_paddr=0x%llx, ci_paddr=0x%llx, portalid=%d, prios=%d\n", 591 attr.qbman_portal_ce_paddr, 592 attr.qbman_portal_ci_paddr, 593 attr.qbman_portal_id, 594 attr.num_priorities); 595 596 p_des.cena_bar = (void *)attr.qbman_portal_ce_paddr; 597 p_des.cinh_bar = (void *)attr.qbman_portal_ci_paddr; 598 599 dflt_dpio->sw_portal = qbman_swp_init(&p_des); 600 if (dflt_dpio->sw_portal == NULL) { 601 printf("qbman_swp_init() failed\n"); 602 goto err_get_swp_init; 603 } 604 return 0; 605 606 err_get_swp_init: 607 err_get_enable: 608 dpio_disable(dflt_mc_io, dflt_dpio_handle); 609 err_get_attr: 610 dpio_close(dflt_mc_io, dflt_dpio_handle); 611 err_open: 612 free(dflt_dpio); 613 return err; 614 } 615 616 int dpbp_init(struct dprc_obj_desc obj_desc) 617 { 618 dflt_dpbp = (struct fsl_dpbp_obj *)malloc(sizeof(struct fsl_dpbp_obj)); 619 if (!dflt_dpbp) { 620 printf(" No memory: malloc() failed\n"); 621 return -ENOMEM; 622 } 623 dflt_dpbp->dpbp_attr.id = obj_desc.id; 624 625 return 0; 626 } 627 628 int dprc_init_container_obj(struct dprc_obj_desc obj_desc, uint16_t dprc_handle) 629 { 630 int error = 0, state = 0; 631 struct dprc_endpoint dpni_endpoint, dpmac_endpoint; 632 if (!strcmp(obj_desc.type, "dpbp")) { 633 if (!dflt_dpbp) { 634 error = dpbp_init(obj_desc); 635 if (error < 0) 636 printf("dpbp_init failed\n"); 637 } 638 } else if (!strcmp(obj_desc.type, "dpio")) { 639 if (!dflt_dpio) { 640 error = dpio_init(obj_desc); 641 if (error < 0) 642 printf("dpio_init failed\n"); 643 } 644 } else if (!strcmp(obj_desc.type, "dpni")) { 645 strcpy(dpni_endpoint.type, obj_desc.type); 646 dpni_endpoint.id = obj_desc.id; 647 error = dprc_get_connection(dflt_mc_io, dprc_handle, 648 &dpni_endpoint, &dpmac_endpoint, &state); 649 if (!strcmp(dpmac_endpoint.type, "dpmac")) 650 error = ldpaa_eth_init(obj_desc); 651 if (error < 0) 652 printf("ldpaa_eth_init failed\n"); 653 } 654 655 return error; 656 } 657 658 int dprc_scan_container_obj(uint16_t dprc_handle, char *obj_type, int i) 659 { 660 int error = 0; 661 struct dprc_obj_desc obj_desc; 662 663 memset((void *)&obj_desc, 0x00, sizeof(struct dprc_obj_desc)); 664 665 error = dprc_get_obj(dflt_mc_io, dprc_handle, 666 i, &obj_desc); 667 if (error < 0) { 668 printf("dprc_get_obj(i=%d) failed: %d\n", 669 i, error); 670 return error; 671 } 672 673 if (!strcmp(obj_desc.type, obj_type)) { 674 debug("Discovered object: type %s, id %d, req %s\n", 675 obj_desc.type, obj_desc.id, obj_type); 676 677 error = dprc_init_container_obj(obj_desc, dprc_handle); 678 if (error < 0) { 679 printf("dprc_init_container_obj(i=%d) failed: %d\n", 680 i, error); 681 return error; 682 } 683 } 684 685 return error; 686 } 687 688 int fsl_mc_ldpaa_init(bd_t *bis) 689 { 690 int i, error = 0; 691 int dprc_opened = 0, container_id; 692 int num_child_objects = 0; 693 694 error = mc_init(); 695 if (error < 0) 696 goto error; 697 698 error = dprc_get_container_id(dflt_mc_io, &container_id); 699 if (error < 0) { 700 printf("dprc_get_container_id() failed: %d\n", error); 701 goto error; 702 } 703 704 debug("fsl-mc: Container id=0x%x\n", container_id); 705 706 error = dprc_open(dflt_mc_io, container_id, &dflt_dprc_handle); 707 if (error < 0) { 708 printf("dprc_open() failed: %d\n", error); 709 goto error; 710 } 711 dprc_opened = true; 712 713 error = dprc_get_obj_count(dflt_mc_io, 714 dflt_dprc_handle, 715 &num_child_objects); 716 if (error < 0) { 717 printf("dprc_get_obj_count() failed: %d\n", error); 718 goto error; 719 } 720 debug("Total child in container %d = %d\n", container_id, 721 num_child_objects); 722 723 if (num_child_objects != 0) { 724 /* 725 * Discover objects currently in the DPRC container in the MC: 726 */ 727 for (i = 0; i < num_child_objects; i++) 728 error = dprc_scan_container_obj(dflt_dprc_handle, 729 "dpbp", i); 730 731 for (i = 0; i < num_child_objects; i++) 732 error = dprc_scan_container_obj(dflt_dprc_handle, 733 "dpio", i); 734 735 for (i = 0; i < num_child_objects; i++) 736 error = dprc_scan_container_obj(dflt_dprc_handle, 737 "dpni", i); 738 } 739 error: 740 if (dprc_opened) 741 dprc_close(dflt_mc_io, dflt_dprc_handle); 742 743 return error; 744 } 745 746 void fsl_mc_ldpaa_exit(bd_t *bis) 747 { 748 int err; 749 750 if (get_mc_boot_status() == 0) { 751 err = dpio_disable(dflt_mc_io, dflt_dpio_handle); 752 if (err < 0) { 753 printf("dpio_disable() failed: %d\n", err); 754 return; 755 } 756 err = dpio_reset(dflt_mc_io, dflt_dpio_handle); 757 if (err < 0) { 758 printf("dpio_reset() failed: %d\n", err); 759 return; 760 } 761 err = dpio_close(dflt_mc_io, dflt_dpio_handle); 762 if (err < 0) { 763 printf("dpio_close() failed: %d\n", err); 764 return; 765 } 766 767 free(dflt_dpio); 768 free(dflt_dpbp); 769 } 770 771 if (dflt_mc_io) 772 free(dflt_mc_io); 773 } 774