17d436078SPrabhakar Kushwaha /* 27d436078SPrabhakar Kushwaha * Copyright 2013 Freescale Semiconductor, Inc. 37d436078SPrabhakar Kushwaha * 47d436078SPrabhakar Kushwaha * SPDX-License-Identifier: GPL-2.0+ 57d436078SPrabhakar Kushwaha */ 67d436078SPrabhakar Kushwaha #include <common.h> 77d436078SPrabhakar Kushwaha #include <phy.h> 87d436078SPrabhakar Kushwaha #include <fm_eth.h> 97d436078SPrabhakar Kushwaha #include <asm/io.h> 107d436078SPrabhakar Kushwaha #include <asm/immap_85xx.h> 117d436078SPrabhakar Kushwaha #include <asm/fsl_serdes.h> 127d436078SPrabhakar Kushwaha fman_port_enet_if(enum fm_port port)137d436078SPrabhakar Kushwahaphy_interface_t fman_port_enet_if(enum fm_port port) 147d436078SPrabhakar Kushwaha { 155b7672fcSPrabhakar Kushwaha ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 165b7672fcSPrabhakar Kushwaha u32 rcwsr13 = in_be32(&gur->rcwsr[13]); 175b7672fcSPrabhakar Kushwaha 185b7672fcSPrabhakar Kushwaha /* handle RGMII first */ 195b7672fcSPrabhakar Kushwaha if ((port == FM1_DTSEC2) && 205b7672fcSPrabhakar Kushwaha ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) == 215b7672fcSPrabhakar Kushwaha FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT)) { 225b7672fcSPrabhakar Kushwaha if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == 235b7672fcSPrabhakar Kushwaha FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII) 245b7672fcSPrabhakar Kushwaha return PHY_INTERFACE_MODE_RGMII; 255b7672fcSPrabhakar Kushwaha else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == 265b7672fcSPrabhakar Kushwaha FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII) 275b7672fcSPrabhakar Kushwaha return PHY_INTERFACE_MODE_MII; 285b7672fcSPrabhakar Kushwaha } 295b7672fcSPrabhakar Kushwaha 305b7672fcSPrabhakar Kushwaha if ((port == FM1_DTSEC4) && 315b7672fcSPrabhakar Kushwaha ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) == 325b7672fcSPrabhakar Kushwaha FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH)) { 335b7672fcSPrabhakar Kushwaha if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == 345b7672fcSPrabhakar Kushwaha FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII) 355b7672fcSPrabhakar Kushwaha return PHY_INTERFACE_MODE_RGMII; 365b7672fcSPrabhakar Kushwaha else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == 375b7672fcSPrabhakar Kushwaha FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII) 385b7672fcSPrabhakar Kushwaha return PHY_INTERFACE_MODE_MII; 395b7672fcSPrabhakar Kushwaha } 405b7672fcSPrabhakar Kushwaha 415b7672fcSPrabhakar Kushwaha if (port == FM1_DTSEC5) { 425b7672fcSPrabhakar Kushwaha if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == 435b7672fcSPrabhakar Kushwaha FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII) 445b7672fcSPrabhakar Kushwaha return PHY_INTERFACE_MODE_RGMII; 455b7672fcSPrabhakar Kushwaha else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == 465b7672fcSPrabhakar Kushwaha FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII) 475b7672fcSPrabhakar Kushwaha return PHY_INTERFACE_MODE_MII; 485b7672fcSPrabhakar Kushwaha } 495b7672fcSPrabhakar Kushwaha 505b7672fcSPrabhakar Kushwaha switch (port) { 515b7672fcSPrabhakar Kushwaha case FM1_DTSEC1: 525b7672fcSPrabhakar Kushwaha case FM1_DTSEC2: 53*27b57569SCodrin Ciubotariu if (is_serdes_configured(QSGMII_SW1_A + port - FM1_DTSEC1) || 54*27b57569SCodrin Ciubotariu is_serdes_configured(SGMII_SW1_MAC1 + port - FM1_DTSEC1)) 555b7672fcSPrabhakar Kushwaha return PHY_INTERFACE_MODE_QSGMII; 565b7672fcSPrabhakar Kushwaha case FM1_DTSEC3: 575b7672fcSPrabhakar Kushwaha case FM1_DTSEC4: 585b7672fcSPrabhakar Kushwaha case FM1_DTSEC5: 595b7672fcSPrabhakar Kushwaha if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) 605b7672fcSPrabhakar Kushwaha return PHY_INTERFACE_MODE_SGMII; 615b7672fcSPrabhakar Kushwaha break; 625b7672fcSPrabhakar Kushwaha default: 635b7672fcSPrabhakar Kushwaha return PHY_INTERFACE_MODE_NONE; 645b7672fcSPrabhakar Kushwaha } 655b7672fcSPrabhakar Kushwaha 667d436078SPrabhakar Kushwaha return PHY_INTERFACE_MODE_NONE; 677d436078SPrabhakar Kushwaha } 68