1e394ceb1SPoonam Aggrwal /* 2e394ceb1SPoonam Aggrwal * Copyright 2012 Freescale Semiconductor, Inc. 3e394ceb1SPoonam Aggrwal * Roy Zang <tie-fei.zang@freescale.com> 4e394ceb1SPoonam Aggrwal * 51a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6e394ceb1SPoonam Aggrwal */ 7e394ceb1SPoonam Aggrwal #include <common.h> 8e394ceb1SPoonam Aggrwal #include <phy.h> 9e394ceb1SPoonam Aggrwal #include <fm_eth.h> 10e394ceb1SPoonam Aggrwal #include <asm/io.h> 11e394ceb1SPoonam Aggrwal #include <asm/immap_85xx.h> 12e394ceb1SPoonam Aggrwal #include <asm/fsl_serdes.h> 13e394ceb1SPoonam Aggrwal 14e394ceb1SPoonam Aggrwal u32 port_to_devdisr[] = { 15e394ceb1SPoonam Aggrwal [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, 16e394ceb1SPoonam Aggrwal [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, 17e394ceb1SPoonam Aggrwal [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, 18e394ceb1SPoonam Aggrwal [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, 19e394ceb1SPoonam Aggrwal [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5, 20e394ceb1SPoonam Aggrwal [FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6, 21e394ceb1SPoonam Aggrwal [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1, 22e394ceb1SPoonam Aggrwal [FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2, 23e394ceb1SPoonam Aggrwal }; 24e394ceb1SPoonam Aggrwal 25e394ceb1SPoonam Aggrwal static int is_device_disabled(enum fm_port port) 26e394ceb1SPoonam Aggrwal { 27e394ceb1SPoonam Aggrwal ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 28e394ceb1SPoonam Aggrwal u32 devdisr2 = in_be32(&gur->devdisr2); 29e394ceb1SPoonam Aggrwal 30e394ceb1SPoonam Aggrwal return port_to_devdisr[port] & devdisr2; 31e394ceb1SPoonam Aggrwal } 32e394ceb1SPoonam Aggrwal 33e394ceb1SPoonam Aggrwal void fman_disable_port(enum fm_port port) 34e394ceb1SPoonam Aggrwal { 35e394ceb1SPoonam Aggrwal ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 36e394ceb1SPoonam Aggrwal 37e394ceb1SPoonam Aggrwal setbits_be32(&gur->devdisr2, port_to_devdisr[port]); 38e394ceb1SPoonam Aggrwal } 39e394ceb1SPoonam Aggrwal 40*f51d3b71SValentin Longchamp void fman_enable_port(enum fm_port port) 41*f51d3b71SValentin Longchamp { 42*f51d3b71SValentin Longchamp ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 43*f51d3b71SValentin Longchamp 44*f51d3b71SValentin Longchamp clrbits_be32(&gur->devdisr2, port_to_devdisr[port]); 45*f51d3b71SValentin Longchamp } 46*f51d3b71SValentin Longchamp 47e394ceb1SPoonam Aggrwal phy_interface_t fman_port_enet_if(enum fm_port port) 48e394ceb1SPoonam Aggrwal { 49e394ceb1SPoonam Aggrwal if (is_device_disabled(port)) 50e394ceb1SPoonam Aggrwal return PHY_INTERFACE_MODE_NONE; 51e394ceb1SPoonam Aggrwal 5216d88f41SSuresh Gupta /*B4860 has two 10Gig Mac*/ 5316d88f41SSuresh Gupta if ((port == FM1_10GEC1 || port == FM1_10GEC2) && 5416d88f41SSuresh Gupta ((is_serdes_configured(XAUI_FM1_MAC9)) || 5516d88f41SSuresh Gupta (is_serdes_configured(XAUI_FM1_MAC10)))) 56e394ceb1SPoonam Aggrwal return PHY_INTERFACE_MODE_XGMII; 57e394ceb1SPoonam Aggrwal 58e394ceb1SPoonam Aggrwal /* Fix me need to handle RGMII here first */ 59e394ceb1SPoonam Aggrwal 60e394ceb1SPoonam Aggrwal switch (port) { 61e394ceb1SPoonam Aggrwal case FM1_DTSEC1: 62e394ceb1SPoonam Aggrwal case FM1_DTSEC2: 63e394ceb1SPoonam Aggrwal case FM1_DTSEC3: 64e394ceb1SPoonam Aggrwal case FM1_DTSEC4: 65e394ceb1SPoonam Aggrwal case FM1_DTSEC5: 66e394ceb1SPoonam Aggrwal case FM1_DTSEC6: 67e394ceb1SPoonam Aggrwal if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) 68e394ceb1SPoonam Aggrwal return PHY_INTERFACE_MODE_SGMII; 69e394ceb1SPoonam Aggrwal break; 70e394ceb1SPoonam Aggrwal default: 71e394ceb1SPoonam Aggrwal return PHY_INTERFACE_MODE_NONE; 72e394ceb1SPoonam Aggrwal } 73e394ceb1SPoonam Aggrwal 74e394ceb1SPoonam Aggrwal return PHY_INTERFACE_MODE_NONE; 75e394ceb1SPoonam Aggrwal } 76