1*e394ceb1SPoonam Aggrwal /* 2*e394ceb1SPoonam Aggrwal * Copyright 2012 Freescale Semiconductor, Inc. 3*e394ceb1SPoonam Aggrwal * Roy Zang <tie-fei.zang@freescale.com> 4*e394ceb1SPoonam Aggrwal * 5*e394ceb1SPoonam Aggrwal * This program is free software; you can redistribute it and/or 6*e394ceb1SPoonam Aggrwal * modify it under the terms of the GNU General Public License as 7*e394ceb1SPoonam Aggrwal * published by the Free Software Foundation; either version 2 of 8*e394ceb1SPoonam Aggrwal * the License, or (at your option) any later version. 9*e394ceb1SPoonam Aggrwal * 10*e394ceb1SPoonam Aggrwal * This program is distributed in the hope that it will be useful, 11*e394ceb1SPoonam Aggrwal * but WITHOUT ANY WARRANTY; without even the implied warranty of 12*e394ceb1SPoonam Aggrwal * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13*e394ceb1SPoonam Aggrwal * GNU General Public License for more details. 14*e394ceb1SPoonam Aggrwal * 15*e394ceb1SPoonam Aggrwal * You should have received a copy of the GNU General Public License 16*e394ceb1SPoonam Aggrwal * along with this program; if not, write to the Free Software 17*e394ceb1SPoonam Aggrwal * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 18*e394ceb1SPoonam Aggrwal * MA 02111-1307 USA 19*e394ceb1SPoonam Aggrwal */ 20*e394ceb1SPoonam Aggrwal #include <common.h> 21*e394ceb1SPoonam Aggrwal #include <phy.h> 22*e394ceb1SPoonam Aggrwal #include <fm_eth.h> 23*e394ceb1SPoonam Aggrwal #include <asm/io.h> 24*e394ceb1SPoonam Aggrwal #include <asm/immap_85xx.h> 25*e394ceb1SPoonam Aggrwal #include <asm/fsl_serdes.h> 26*e394ceb1SPoonam Aggrwal 27*e394ceb1SPoonam Aggrwal u32 port_to_devdisr[] = { 28*e394ceb1SPoonam Aggrwal [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, 29*e394ceb1SPoonam Aggrwal [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, 30*e394ceb1SPoonam Aggrwal [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, 31*e394ceb1SPoonam Aggrwal [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, 32*e394ceb1SPoonam Aggrwal [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5, 33*e394ceb1SPoonam Aggrwal [FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6, 34*e394ceb1SPoonam Aggrwal [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1, 35*e394ceb1SPoonam Aggrwal [FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2, 36*e394ceb1SPoonam Aggrwal }; 37*e394ceb1SPoonam Aggrwal 38*e394ceb1SPoonam Aggrwal static int is_device_disabled(enum fm_port port) 39*e394ceb1SPoonam Aggrwal { 40*e394ceb1SPoonam Aggrwal ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 41*e394ceb1SPoonam Aggrwal u32 devdisr2 = in_be32(&gur->devdisr2); 42*e394ceb1SPoonam Aggrwal 43*e394ceb1SPoonam Aggrwal return port_to_devdisr[port] & devdisr2; 44*e394ceb1SPoonam Aggrwal } 45*e394ceb1SPoonam Aggrwal 46*e394ceb1SPoonam Aggrwal void fman_disable_port(enum fm_port port) 47*e394ceb1SPoonam Aggrwal { 48*e394ceb1SPoonam Aggrwal ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 49*e394ceb1SPoonam Aggrwal 50*e394ceb1SPoonam Aggrwal setbits_be32(&gur->devdisr2, port_to_devdisr[port]); 51*e394ceb1SPoonam Aggrwal } 52*e394ceb1SPoonam Aggrwal 53*e394ceb1SPoonam Aggrwal phy_interface_t fman_port_enet_if(enum fm_port port) 54*e394ceb1SPoonam Aggrwal { 55*e394ceb1SPoonam Aggrwal if (is_device_disabled(port)) 56*e394ceb1SPoonam Aggrwal return PHY_INTERFACE_MODE_NONE; 57*e394ceb1SPoonam Aggrwal 58*e394ceb1SPoonam Aggrwal if ((port == FM1_10GEC1 || port == FM1_10GEC2) 59*e394ceb1SPoonam Aggrwal && (is_serdes_configured(XAUI_FM1))) 60*e394ceb1SPoonam Aggrwal return PHY_INTERFACE_MODE_XGMII; 61*e394ceb1SPoonam Aggrwal 62*e394ceb1SPoonam Aggrwal /* Fix me need to handle RGMII here first */ 63*e394ceb1SPoonam Aggrwal 64*e394ceb1SPoonam Aggrwal switch (port) { 65*e394ceb1SPoonam Aggrwal case FM1_DTSEC1: 66*e394ceb1SPoonam Aggrwal case FM1_DTSEC2: 67*e394ceb1SPoonam Aggrwal case FM1_DTSEC3: 68*e394ceb1SPoonam Aggrwal case FM1_DTSEC4: 69*e394ceb1SPoonam Aggrwal case FM1_DTSEC5: 70*e394ceb1SPoonam Aggrwal case FM1_DTSEC6: 71*e394ceb1SPoonam Aggrwal if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) 72*e394ceb1SPoonam Aggrwal return PHY_INTERFACE_MODE_SGMII; 73*e394ceb1SPoonam Aggrwal break; 74*e394ceb1SPoonam Aggrwal default: 75*e394ceb1SPoonam Aggrwal return PHY_INTERFACE_MODE_NONE; 76*e394ceb1SPoonam Aggrwal } 77*e394ceb1SPoonam Aggrwal 78*e394ceb1SPoonam Aggrwal return PHY_INTERFACE_MODE_NONE; 79*e394ceb1SPoonam Aggrwal } 80