1e394ceb1SPoonam Aggrwal /* 2e394ceb1SPoonam Aggrwal * Copyright 2012 Freescale Semiconductor, Inc. 3e394ceb1SPoonam Aggrwal * Roy Zang <tie-fei.zang@freescale.com> 4e394ceb1SPoonam Aggrwal * 5e394ceb1SPoonam Aggrwal * This program is free software; you can redistribute it and/or 6e394ceb1SPoonam Aggrwal * modify it under the terms of the GNU General Public License as 7e394ceb1SPoonam Aggrwal * published by the Free Software Foundation; either version 2 of 8e394ceb1SPoonam Aggrwal * the License, or (at your option) any later version. 9e394ceb1SPoonam Aggrwal * 10e394ceb1SPoonam Aggrwal * This program is distributed in the hope that it will be useful, 11e394ceb1SPoonam Aggrwal * but WITHOUT ANY WARRANTY; without even the implied warranty of 12e394ceb1SPoonam Aggrwal * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13e394ceb1SPoonam Aggrwal * GNU General Public License for more details. 14e394ceb1SPoonam Aggrwal * 15e394ceb1SPoonam Aggrwal * You should have received a copy of the GNU General Public License 16e394ceb1SPoonam Aggrwal * along with this program; if not, write to the Free Software 17e394ceb1SPoonam Aggrwal * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 18e394ceb1SPoonam Aggrwal * MA 02111-1307 USA 19e394ceb1SPoonam Aggrwal */ 20e394ceb1SPoonam Aggrwal #include <common.h> 21e394ceb1SPoonam Aggrwal #include <phy.h> 22e394ceb1SPoonam Aggrwal #include <fm_eth.h> 23e394ceb1SPoonam Aggrwal #include <asm/io.h> 24e394ceb1SPoonam Aggrwal #include <asm/immap_85xx.h> 25e394ceb1SPoonam Aggrwal #include <asm/fsl_serdes.h> 26e394ceb1SPoonam Aggrwal 27e394ceb1SPoonam Aggrwal u32 port_to_devdisr[] = { 28e394ceb1SPoonam Aggrwal [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, 29e394ceb1SPoonam Aggrwal [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, 30e394ceb1SPoonam Aggrwal [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, 31e394ceb1SPoonam Aggrwal [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, 32e394ceb1SPoonam Aggrwal [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5, 33e394ceb1SPoonam Aggrwal [FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6, 34e394ceb1SPoonam Aggrwal [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1, 35e394ceb1SPoonam Aggrwal [FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2, 36e394ceb1SPoonam Aggrwal }; 37e394ceb1SPoonam Aggrwal 38e394ceb1SPoonam Aggrwal static int is_device_disabled(enum fm_port port) 39e394ceb1SPoonam Aggrwal { 40e394ceb1SPoonam Aggrwal ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 41e394ceb1SPoonam Aggrwal u32 devdisr2 = in_be32(&gur->devdisr2); 42e394ceb1SPoonam Aggrwal 43e394ceb1SPoonam Aggrwal return port_to_devdisr[port] & devdisr2; 44e394ceb1SPoonam Aggrwal } 45e394ceb1SPoonam Aggrwal 46e394ceb1SPoonam Aggrwal void fman_disable_port(enum fm_port port) 47e394ceb1SPoonam Aggrwal { 48e394ceb1SPoonam Aggrwal ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 49e394ceb1SPoonam Aggrwal 50e394ceb1SPoonam Aggrwal setbits_be32(&gur->devdisr2, port_to_devdisr[port]); 51e394ceb1SPoonam Aggrwal } 52e394ceb1SPoonam Aggrwal 53e394ceb1SPoonam Aggrwal phy_interface_t fman_port_enet_if(enum fm_port port) 54e394ceb1SPoonam Aggrwal { 55e394ceb1SPoonam Aggrwal if (is_device_disabled(port)) 56e394ceb1SPoonam Aggrwal return PHY_INTERFACE_MODE_NONE; 57e394ceb1SPoonam Aggrwal 58*16d88f41SSuresh Gupta /*B4860 has two 10Gig Mac*/ 59*16d88f41SSuresh Gupta if ((port == FM1_10GEC1 || port == FM1_10GEC2) && 60*16d88f41SSuresh Gupta ((is_serdes_configured(XAUI_FM1_MAC9)) || 61*16d88f41SSuresh Gupta (is_serdes_configured(XAUI_FM1_MAC10)))) 62e394ceb1SPoonam Aggrwal return PHY_INTERFACE_MODE_XGMII; 63e394ceb1SPoonam Aggrwal 64e394ceb1SPoonam Aggrwal /* Fix me need to handle RGMII here first */ 65e394ceb1SPoonam Aggrwal 66e394ceb1SPoonam Aggrwal switch (port) { 67e394ceb1SPoonam Aggrwal case FM1_DTSEC1: 68e394ceb1SPoonam Aggrwal case FM1_DTSEC2: 69e394ceb1SPoonam Aggrwal case FM1_DTSEC3: 70e394ceb1SPoonam Aggrwal case FM1_DTSEC4: 71e394ceb1SPoonam Aggrwal case FM1_DTSEC5: 72e394ceb1SPoonam Aggrwal case FM1_DTSEC6: 73e394ceb1SPoonam Aggrwal if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) 74e394ceb1SPoonam Aggrwal return PHY_INTERFACE_MODE_SGMII; 75e394ceb1SPoonam Aggrwal break; 76e394ceb1SPoonam Aggrwal default: 77e394ceb1SPoonam Aggrwal return PHY_INTERFACE_MODE_NONE; 78e394ceb1SPoonam Aggrwal } 79e394ceb1SPoonam Aggrwal 80e394ceb1SPoonam Aggrwal return PHY_INTERFACE_MODE_NONE; 81e394ceb1SPoonam Aggrwal } 82