1 /* 2 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com> 3 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org> 4 * (C) Copyright 2008 Armadeus Systems nc 5 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 6 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <malloc.h> 26 #include <net.h> 27 #include <miiphy.h> 28 #include "fec_mxc.h" 29 30 #include <asm/arch/clock.h> 31 #include <asm/arch/imx-regs.h> 32 #include <asm/io.h> 33 #include <asm/errno.h> 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 #ifndef CONFIG_MII 38 #error "CONFIG_MII has to be defined!" 39 #endif 40 41 #undef DEBUG 42 43 struct nbuf { 44 uint8_t data[1500]; /**< actual data */ 45 int length; /**< actual length */ 46 int used; /**< buffer in use or not */ 47 uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */ 48 }; 49 50 struct fec_priv gfec = { 51 .eth = (struct ethernet_regs *)IMX_FEC_BASE, 52 .xcv_type = MII100, 53 .rbd_base = NULL, 54 .rbd_index = 0, 55 .tbd_base = NULL, 56 .tbd_index = 0, 57 .bd = NULL, 58 }; 59 60 /* 61 * MII-interface related functions 62 */ 63 static int fec_miiphy_read(char *dev, uint8_t phyAddr, uint8_t regAddr, 64 uint16_t *retVal) 65 { 66 struct eth_device *edev = eth_get_dev_by_name(dev); 67 struct fec_priv *fec = (struct fec_priv *)edev->priv; 68 69 uint32_t reg; /* convenient holder for the PHY register */ 70 uint32_t phy; /* convenient holder for the PHY */ 71 uint32_t start; 72 73 /* 74 * reading from any PHY's register is done by properly 75 * programming the FEC's MII data register. 76 */ 77 writel(FEC_IEVENT_MII, &fec->eth->ievent); 78 reg = regAddr << FEC_MII_DATA_RA_SHIFT; 79 phy = phyAddr << FEC_MII_DATA_PA_SHIFT; 80 81 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | 82 phy | reg, &fec->eth->mii_data); 83 84 /* 85 * wait for the related interrupt 86 */ 87 start = get_timer_masked(); 88 while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) { 89 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { 90 printf("Read MDIO failed...\n"); 91 return -1; 92 } 93 } 94 95 /* 96 * clear mii interrupt bit 97 */ 98 writel(FEC_IEVENT_MII, &fec->eth->ievent); 99 100 /* 101 * it's now safe to read the PHY's register 102 */ 103 *retVal = readl(&fec->eth->mii_data); 104 debug("fec_miiphy_read: phy: %02x reg:%02x val:%#x\n", phyAddr, 105 regAddr, *retVal); 106 return 0; 107 } 108 109 static int fec_miiphy_write(char *dev, uint8_t phyAddr, uint8_t regAddr, 110 uint16_t data) 111 { 112 struct eth_device *edev = eth_get_dev_by_name(dev); 113 struct fec_priv *fec = (struct fec_priv *)edev->priv; 114 115 uint32_t reg; /* convenient holder for the PHY register */ 116 uint32_t phy; /* convenient holder for the PHY */ 117 uint32_t start; 118 119 reg = regAddr << FEC_MII_DATA_RA_SHIFT; 120 phy = phyAddr << FEC_MII_DATA_PA_SHIFT; 121 122 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | 123 FEC_MII_DATA_TA | phy | reg | data, &fec->eth->mii_data); 124 125 /* 126 * wait for the MII interrupt 127 */ 128 start = get_timer_masked(); 129 while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) { 130 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { 131 printf("Write MDIO failed...\n"); 132 return -1; 133 } 134 } 135 136 /* 137 * clear MII interrupt bit 138 */ 139 writel(FEC_IEVENT_MII, &fec->eth->ievent); 140 debug("fec_miiphy_write: phy: %02x reg:%02x val:%#x\n", phyAddr, 141 regAddr, data); 142 143 return 0; 144 } 145 146 static int miiphy_restart_aneg(struct eth_device *dev) 147 { 148 /* 149 * Wake up from sleep if necessary 150 * Reset PHY, then delay 300ns 151 */ 152 miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_MIPGSR, 0x00FF); 153 miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR, 154 PHY_BMCR_RESET); 155 udelay(1000); 156 157 /* 158 * Set the auto-negotiation advertisement register bits 159 */ 160 miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_ANAR, 161 PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD | 162 PHY_ANLPAR_10 | PHY_ANLPAR_PSB_802_3); 163 miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR, 164 PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); 165 166 return 0; 167 } 168 169 static int miiphy_wait_aneg(struct eth_device *dev) 170 { 171 uint32_t start; 172 uint16_t status; 173 174 /* 175 * Wait for AN completion 176 */ 177 start = get_timer_masked(); 178 do { 179 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { 180 printf("%s: Autonegotiation timeout\n", dev->name); 181 return -1; 182 } 183 184 if (miiphy_read(dev->name, CONFIG_FEC_MXC_PHYADDR, 185 PHY_BMSR, &status)) { 186 printf("%s: Autonegotiation failed. status: 0x%04x\n", 187 dev->name, status); 188 return -1; 189 } 190 } while (!(status & PHY_BMSR_LS)); 191 192 return 0; 193 } 194 static int fec_rx_task_enable(struct fec_priv *fec) 195 { 196 writel(1 << 24, &fec->eth->r_des_active); 197 return 0; 198 } 199 200 static int fec_rx_task_disable(struct fec_priv *fec) 201 { 202 return 0; 203 } 204 205 static int fec_tx_task_enable(struct fec_priv *fec) 206 { 207 writel(1 << 24, &fec->eth->x_des_active); 208 return 0; 209 } 210 211 static int fec_tx_task_disable(struct fec_priv *fec) 212 { 213 return 0; 214 } 215 216 /** 217 * Initialize receive task's buffer descriptors 218 * @param[in] fec all we know about the device yet 219 * @param[in] count receive buffer count to be allocated 220 * @param[in] size size of each receive buffer 221 * @return 0 on success 222 * 223 * For this task we need additional memory for the data buffers. And each 224 * data buffer requires some alignment. Thy must be aligned to a specific 225 * boundary each (DB_DATA_ALIGNMENT). 226 */ 227 static int fec_rbd_init(struct fec_priv *fec, int count, int size) 228 { 229 int ix; 230 uint32_t p = 0; 231 232 /* reserve data memory and consider alignment */ 233 fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT); 234 p = (uint32_t)fec->rdb_ptr; 235 if (!p) { 236 puts("fec_imx27: not enough malloc memory!\n"); 237 return -ENOMEM; 238 } 239 memset((void *)p, 0, size * count + DB_DATA_ALIGNMENT); 240 p += DB_DATA_ALIGNMENT-1; 241 p &= ~(DB_DATA_ALIGNMENT-1); 242 243 for (ix = 0; ix < count; ix++) { 244 writel(p, &fec->rbd_base[ix].data_pointer); 245 p += size; 246 writew(FEC_RBD_EMPTY, &fec->rbd_base[ix].status); 247 writew(0, &fec->rbd_base[ix].data_length); 248 } 249 /* 250 * mark the last RBD to close the ring 251 */ 252 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[ix - 1].status); 253 fec->rbd_index = 0; 254 255 return 0; 256 } 257 258 /** 259 * Initialize transmit task's buffer descriptors 260 * @param[in] fec all we know about the device yet 261 * 262 * Transmit buffers are created externally. We only have to init the BDs here.\n 263 * Note: There is a race condition in the hardware. When only one BD is in 264 * use it must be marked with the WRAP bit to use it for every transmitt. 265 * This bit in combination with the READY bit results into double transmit 266 * of each data buffer. It seems the state machine checks READY earlier then 267 * resetting it after the first transfer. 268 * Using two BDs solves this issue. 269 */ 270 static void fec_tbd_init(struct fec_priv *fec) 271 { 272 writew(0x0000, &fec->tbd_base[0].status); 273 writew(FEC_TBD_WRAP, &fec->tbd_base[1].status); 274 fec->tbd_index = 0; 275 } 276 277 /** 278 * Mark the given read buffer descriptor as free 279 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0 280 * @param[in] pRbd buffer descriptor to mark free again 281 */ 282 static void fec_rbd_clean(int last, struct fec_bd *pRbd) 283 { 284 /* 285 * Reset buffer descriptor as empty 286 */ 287 if (last) 288 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &pRbd->status); 289 else 290 writew(FEC_RBD_EMPTY, &pRbd->status); 291 /* 292 * no data in it 293 */ 294 writew(0, &pRbd->data_length); 295 } 296 297 static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac) 298 { 299 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; 300 int i; 301 302 for (i = 0; i < 6; i++) 303 mac[6-1-i] = readl(&iim->iim_bank_area0[IIM0_MAC + i]); 304 305 return is_valid_ether_addr(mac); 306 } 307 308 static int fec_set_hwaddr(struct eth_device *dev, unsigned char *mac) 309 { 310 struct fec_priv *fec = (struct fec_priv *)dev->priv; 311 312 writel(0, &fec->eth->iaddr1); 313 writel(0, &fec->eth->iaddr2); 314 writel(0, &fec->eth->gaddr1); 315 writel(0, &fec->eth->gaddr2); 316 317 /* 318 * Set physical address 319 */ 320 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3], 321 &fec->eth->paddr1); 322 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2); 323 324 return 0; 325 } 326 327 /** 328 * Start the FEC engine 329 * @param[in] dev Our device to handle 330 */ 331 static int fec_open(struct eth_device *edev) 332 { 333 struct fec_priv *fec = (struct fec_priv *)edev->priv; 334 335 debug("fec_open: fec_open(dev)\n"); 336 /* full-duplex, heartbeat disabled */ 337 writel(1 << 2, &fec->eth->x_cntrl); 338 fec->rbd_index = 0; 339 340 /* 341 * Enable FEC-Lite controller 342 */ 343 writel(FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl); 344 345 miiphy_wait_aneg(edev); 346 miiphy_speed(edev->name, CONFIG_FEC_MXC_PHYADDR); 347 miiphy_duplex(edev->name, CONFIG_FEC_MXC_PHYADDR); 348 349 /* 350 * Enable SmartDMA receive task 351 */ 352 fec_rx_task_enable(fec); 353 354 udelay(100000); 355 return 0; 356 } 357 358 static int fec_init(struct eth_device *dev, bd_t* bd) 359 { 360 uint32_t base; 361 struct fec_priv *fec = (struct fec_priv *)dev->priv; 362 363 /* 364 * reserve memory for both buffer descriptor chains at once 365 * Datasheet forces the startaddress of each chain is 16 byte 366 * aligned 367 */ 368 fec->base_ptr = malloc((2 + FEC_RBD_NUM) * 369 sizeof(struct fec_bd) + DB_ALIGNMENT); 370 base = (uint32_t)fec->base_ptr; 371 if (!base) { 372 puts("fec_imx27: not enough malloc memory!\n"); 373 return -ENOMEM; 374 } 375 memset((void *)base, 0, (2 + FEC_RBD_NUM) * 376 sizeof(struct fec_bd) + DB_ALIGNMENT); 377 base += (DB_ALIGNMENT-1); 378 base &= ~(DB_ALIGNMENT-1); 379 380 fec->rbd_base = (struct fec_bd *)base; 381 382 base += FEC_RBD_NUM * sizeof(struct fec_bd); 383 384 fec->tbd_base = (struct fec_bd *)base; 385 386 /* 387 * Set interrupt mask register 388 */ 389 writel(0x00000000, &fec->eth->imask); 390 391 /* 392 * Clear FEC-Lite interrupt event register(IEVENT) 393 */ 394 writel(0xffffffff, &fec->eth->ievent); 395 396 397 /* 398 * Set FEC-Lite receive control register(R_CNTRL): 399 */ 400 if (fec->xcv_type == SEVENWIRE) { 401 /* 402 * Frame length=1518; 7-wire mode 403 */ 404 writel(0x05ee0020, &fec->eth->r_cntrl); /* FIXME 0x05ee0000 */ 405 } else { 406 /* 407 * Frame length=1518; MII mode; 408 */ 409 writel(0x05ee0024, &fec->eth->r_cntrl); /* FIXME 0x05ee0004 */ 410 /* 411 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock 412 * and do not drop the Preamble. 413 */ 414 writel((((imx_get_ahbclk() / 1000000) + 2) / 5) << 1, 415 &fec->eth->mii_speed); 416 debug("fec_init: mii_speed %#lx\n", 417 (((imx_get_ahbclk() / 1000000) + 2) / 5) << 1); 418 } 419 /* 420 * Set Opcode/Pause Duration Register 421 */ 422 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */ 423 writel(0x2, &fec->eth->x_wmrk); 424 /* 425 * Set multicast address filter 426 */ 427 writel(0x00000000, &fec->eth->gaddr1); 428 writel(0x00000000, &fec->eth->gaddr2); 429 430 431 /* clear MIB RAM */ 432 long *mib_ptr = (long *)(IMX_FEC_BASE + 0x200); 433 while (mib_ptr <= (long *)(IMX_FEC_BASE + 0x2FC)) 434 *mib_ptr++ = 0; 435 436 /* FIFO receive start register */ 437 writel(0x520, &fec->eth->r_fstart); 438 439 /* size and address of each buffer */ 440 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr); 441 writel((uint32_t)fec->tbd_base, &fec->eth->etdsr); 442 writel((uint32_t)fec->rbd_base, &fec->eth->erdsr); 443 444 /* 445 * Initialize RxBD/TxBD rings 446 */ 447 if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) { 448 free(fec->base_ptr); 449 return -ENOMEM; 450 } 451 fec_tbd_init(fec); 452 453 454 if (fec->xcv_type != SEVENWIRE) 455 miiphy_restart_aneg(dev); 456 457 fec_open(dev); 458 return 0; 459 } 460 461 /** 462 * Halt the FEC engine 463 * @param[in] dev Our device to handle 464 */ 465 static void fec_halt(struct eth_device *dev) 466 { 467 struct fec_priv *fec = &gfec; 468 int counter = 0xffff; 469 470 /* 471 * issue graceful stop command to the FEC transmitter if necessary 472 */ 473 writel(FEC_ECNTRL_RESET | readl(&fec->eth->x_cntrl), 474 &fec->eth->x_cntrl); 475 476 debug("eth_halt: wait for stop regs\n"); 477 /* 478 * wait for graceful stop to register 479 */ 480 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA))) 481 ; /* FIXME ensure time */ 482 483 /* 484 * Disable SmartDMA tasks 485 */ 486 fec_tx_task_disable(fec); 487 fec_rx_task_disable(fec); 488 489 /* 490 * Disable the Ethernet Controller 491 * Note: this will also reset the BD index counter! 492 */ 493 writel(0, &fec->eth->ecntrl); 494 fec->rbd_index = 0; 495 fec->tbd_index = 0; 496 free(fec->rdb_ptr); 497 free(fec->base_ptr); 498 debug("eth_halt: done\n"); 499 } 500 501 /** 502 * Transmit one frame 503 * @param[in] dev Our ethernet device to handle 504 * @param[in] packet Pointer to the data to be transmitted 505 * @param[in] length Data count in bytes 506 * @return 0 on success 507 */ 508 static int fec_send(struct eth_device *dev, volatile void* packet, int length) 509 { 510 unsigned int status; 511 512 /* 513 * This routine transmits one frame. This routine only accepts 514 * 6-byte Ethernet addresses. 515 */ 516 struct fec_priv *fec = (struct fec_priv *)dev->priv; 517 518 /* 519 * Check for valid length of data. 520 */ 521 if ((length > 1500) || (length <= 0)) { 522 printf("Payload (%d) to large!\n", length); 523 return -1; 524 } 525 526 /* 527 * Setup the transmit buffer 528 * Note: We are always using the first buffer for transmission, 529 * the second will be empty and only used to stop the DMA engine 530 */ 531 writew(length, &fec->tbd_base[fec->tbd_index].data_length); 532 writel((uint32_t)packet, &fec->tbd_base[fec->tbd_index].data_pointer); 533 /* 534 * update BD's status now 535 * This block: 536 * - is always the last in a chain (means no chain) 537 * - should transmitt the CRC 538 * - might be the last BD in the list, so the address counter should 539 * wrap (-> keep the WRAP flag) 540 */ 541 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP; 542 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; 543 writew(status, &fec->tbd_base[fec->tbd_index].status); 544 545 /* 546 * Enable SmartDMA transmit task 547 */ 548 fec_tx_task_enable(fec); 549 550 /* 551 * wait until frame is sent . 552 */ 553 while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) { 554 /* FIXME: Timeout */ 555 } 556 debug("fec_send: status 0x%x index %d\n", 557 readw(&fec->tbd_base[fec->tbd_index].status), 558 fec->tbd_index); 559 /* for next transmission use the other buffer */ 560 if (fec->tbd_index) 561 fec->tbd_index = 0; 562 else 563 fec->tbd_index = 1; 564 565 return 0; 566 } 567 568 /** 569 * Pull one frame from the card 570 * @param[in] dev Our ethernet device to handle 571 * @return Length of packet read 572 */ 573 static int fec_recv(struct eth_device *dev) 574 { 575 struct fec_priv *fec = (struct fec_priv *)dev->priv; 576 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index]; 577 unsigned long ievent; 578 int frame_length, len = 0; 579 struct nbuf *frame; 580 uint16_t bd_status; 581 uchar buff[FEC_MAX_PKT_SIZE]; 582 583 /* 584 * Check if any critical events have happened 585 */ 586 ievent = readl(&fec->eth->ievent); 587 writel(ievent, &fec->eth->ievent); 588 debug("fec_recv: ievent 0x%x\n", ievent); 589 if (ievent & FEC_IEVENT_BABR) { 590 fec_halt(dev); 591 fec_init(dev, fec->bd); 592 printf("some error: 0x%08lx\n", ievent); 593 return 0; 594 } 595 if (ievent & FEC_IEVENT_HBERR) { 596 /* Heartbeat error */ 597 writel(0x00000001 | readl(&fec->eth->x_cntrl), 598 &fec->eth->x_cntrl); 599 } 600 if (ievent & FEC_IEVENT_GRA) { 601 /* Graceful stop complete */ 602 if (readl(&fec->eth->x_cntrl) & 0x00000001) { 603 fec_halt(dev); 604 writel(~0x00000001 & readl(&fec->eth->x_cntrl), 605 &fec->eth->x_cntrl); 606 fec_init(dev, fec->bd); 607 } 608 } 609 610 /* 611 * ensure reading the right buffer status 612 */ 613 bd_status = readw(&rbd->status); 614 debug("fec_recv: status 0x%x\n", bd_status); 615 616 if (!(bd_status & FEC_RBD_EMPTY)) { 617 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) && 618 ((readw(&rbd->data_length) - 4) > 14)) { 619 /* 620 * Get buffer address and size 621 */ 622 frame = (struct nbuf *)readl(&rbd->data_pointer); 623 frame_length = readw(&rbd->data_length) - 4; 624 /* 625 * Fill the buffer and pass it to upper layers 626 */ 627 memcpy(buff, frame->data, frame_length); 628 NetReceive(buff, frame_length); 629 len = frame_length; 630 } else { 631 if (bd_status & FEC_RBD_ERR) 632 printf("error frame: 0x%08lx 0x%08x\n", 633 (ulong)rbd->data_pointer, 634 bd_status); 635 } 636 /* 637 * free the current buffer, restart the engine 638 * and move forward to the next buffer 639 */ 640 fec_rbd_clean(fec->rbd_index == (FEC_RBD_NUM - 1) ? 1 : 0, rbd); 641 fec_rx_task_enable(fec); 642 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM; 643 } 644 debug("fec_recv: stop\n"); 645 646 return len; 647 } 648 649 static int fec_probe(bd_t *bd) 650 { 651 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; 652 struct eth_device *edev; 653 struct fec_priv *fec = &gfec; 654 unsigned char ethaddr_str[20]; 655 unsigned char ethaddr[6]; 656 char *tmp = getenv("ethaddr"); 657 char *end; 658 659 /* enable FEC clock */ 660 writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1); 661 writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0); 662 663 /* create and fill edev struct */ 664 edev = (struct eth_device *)malloc(sizeof(struct eth_device)); 665 if (!edev) { 666 puts("fec_imx27: not enough malloc memory!\n"); 667 return -ENOMEM; 668 } 669 edev->priv = fec; 670 edev->init = fec_init; 671 edev->send = fec_send; 672 edev->recv = fec_recv; 673 edev->halt = fec_halt; 674 675 fec->eth = (struct ethernet_regs *)IMX_FEC_BASE; 676 fec->bd = bd; 677 678 fec->xcv_type = MII100; 679 680 /* Reset chip. */ 681 writel(FEC_ECNTRL_RESET, &fec->eth->ecntrl); 682 while (readl(&fec->eth->ecntrl) & 1) 683 udelay(10); 684 685 /* 686 * Set interrupt mask register 687 */ 688 writel(0x00000000, &fec->eth->imask); 689 690 /* 691 * Clear FEC-Lite interrupt event register(IEVENT) 692 */ 693 writel(0xffffffff, &fec->eth->ievent); 694 695 /* 696 * Set FEC-Lite receive control register(R_CNTRL): 697 */ 698 /* 699 * Frame length=1518; MII mode; 700 */ 701 writel(0x05ee0024, &fec->eth->r_cntrl); /* FIXME 0x05ee0004 */ 702 /* 703 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock 704 * and do not drop the Preamble. 705 */ 706 writel((((imx_get_ahbclk() / 1000000) + 2) / 5) << 1, 707 &fec->eth->mii_speed); 708 debug("fec_init: mii_speed %#lx\n", 709 (((imx_get_ahbclk() / 1000000) + 2) / 5) << 1); 710 711 sprintf(edev->name, "FEC_MXC"); 712 713 miiphy_register(edev->name, fec_miiphy_read, fec_miiphy_write); 714 715 eth_register(edev); 716 717 if ((NULL != tmp) && (12 <= strlen(tmp))) { 718 int i; 719 /* convert MAC from string to int */ 720 for (i = 0; i < 6; i++) { 721 ethaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; 722 if (tmp) 723 tmp = (*end) ? end + 1 : end; 724 } 725 } else if (fec_get_hwaddr(edev, ethaddr) == 0) { 726 printf("got MAC address from EEPROM: %pM\n", ethaddr); 727 setenv("ethaddr", (char *)ethaddr_str); 728 } 729 memcpy(edev->enetaddr, ethaddr, 6); 730 fec_set_hwaddr(edev, ethaddr); 731 732 return 0; 733 } 734 735 int fecmxc_initialize(bd_t *bd) 736 { 737 int lout = 1; 738 739 debug("eth_init: fec_probe(bd)\n"); 740 lout = fec_probe(bd); 741 742 return lout; 743 } 744