1 /* 2 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com> 3 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org> 4 * (C) Copyright 2008 Armadeus Systems nc 5 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 6 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <malloc.h> 26 #include <net.h> 27 #include <miiphy.h> 28 #include "fec_mxc.h" 29 30 #include <asm/arch/clock.h> 31 #include <asm/arch/imx-regs.h> 32 #include <asm/io.h> 33 #include <asm/errno.h> 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 #ifndef CONFIG_MII 38 #error "CONFIG_MII has to be defined!" 39 #endif 40 41 #ifndef CONFIG_FEC_XCV_TYPE 42 #define CONFIG_FEC_XCV_TYPE MII100 43 #endif 44 45 #undef DEBUG 46 47 struct nbuf { 48 uint8_t data[1500]; /**< actual data */ 49 int length; /**< actual length */ 50 int used; /**< buffer in use or not */ 51 uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */ 52 }; 53 54 /* 55 * MII-interface related functions 56 */ 57 static int fec_miiphy_read(const char *dev, uint8_t phyAddr, uint8_t regAddr, 58 uint16_t *retVal) 59 { 60 struct eth_device *edev = eth_get_dev_by_name(dev); 61 struct fec_priv *fec = (struct fec_priv *)edev->priv; 62 struct ethernet_regs *eth = fec->eth; 63 64 uint32_t reg; /* convenient holder for the PHY register */ 65 uint32_t phy; /* convenient holder for the PHY */ 66 uint32_t start; 67 68 /* 69 * reading from any PHY's register is done by properly 70 * programming the FEC's MII data register. 71 */ 72 writel(FEC_IEVENT_MII, ð->ievent); 73 reg = regAddr << FEC_MII_DATA_RA_SHIFT; 74 phy = phyAddr << FEC_MII_DATA_PA_SHIFT; 75 76 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | 77 phy | reg, ð->mii_data); 78 79 /* 80 * wait for the related interrupt 81 */ 82 start = get_timer(0); 83 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { 84 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { 85 printf("Read MDIO failed...\n"); 86 return -1; 87 } 88 } 89 90 /* 91 * clear mii interrupt bit 92 */ 93 writel(FEC_IEVENT_MII, ð->ievent); 94 95 /* 96 * it's now safe to read the PHY's register 97 */ 98 *retVal = readl(ð->mii_data); 99 debug("fec_miiphy_read: phy: %02x reg:%02x val:%#x\n", phyAddr, 100 regAddr, *retVal); 101 return 0; 102 } 103 104 static void fec_mii_setspeed(struct fec_priv *fec) 105 { 106 /* 107 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock 108 * and do not drop the Preamble. 109 */ 110 writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1, 111 &fec->eth->mii_speed); 112 debug("fec_init: mii_speed %#lx\n", 113 readl(&fec->eth->mii_speed)); 114 } 115 static int fec_miiphy_write(const char *dev, uint8_t phyAddr, uint8_t regAddr, 116 uint16_t data) 117 { 118 struct eth_device *edev = eth_get_dev_by_name(dev); 119 struct fec_priv *fec = (struct fec_priv *)edev->priv; 120 struct ethernet_regs *eth = fec->eth; 121 122 uint32_t reg; /* convenient holder for the PHY register */ 123 uint32_t phy; /* convenient holder for the PHY */ 124 uint32_t start; 125 126 reg = regAddr << FEC_MII_DATA_RA_SHIFT; 127 phy = phyAddr << FEC_MII_DATA_PA_SHIFT; 128 129 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | 130 FEC_MII_DATA_TA | phy | reg | data, ð->mii_data); 131 132 /* 133 * wait for the MII interrupt 134 */ 135 start = get_timer(0); 136 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { 137 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { 138 printf("Write MDIO failed...\n"); 139 return -1; 140 } 141 } 142 143 /* 144 * clear MII interrupt bit 145 */ 146 writel(FEC_IEVENT_MII, ð->ievent); 147 debug("fec_miiphy_write: phy: %02x reg:%02x val:%#x\n", phyAddr, 148 regAddr, data); 149 150 return 0; 151 } 152 153 static int miiphy_restart_aneg(struct eth_device *dev) 154 { 155 struct fec_priv *fec = (struct fec_priv *)dev->priv; 156 157 /* 158 * Wake up from sleep if necessary 159 * Reset PHY, then delay 300ns 160 */ 161 #ifdef CONFIG_MX27 162 miiphy_write(dev->name, fec->phy_id, MII_DCOUNTER, 0x00FF); 163 #endif 164 miiphy_write(dev->name, fec->phy_id, MII_BMCR, 165 BMCR_RESET); 166 udelay(1000); 167 168 /* 169 * Set the auto-negotiation advertisement register bits 170 */ 171 miiphy_write(dev->name, fec->phy_id, MII_ADVERTISE, 172 LPA_100FULL | LPA_100HALF | LPA_10FULL | 173 LPA_10HALF | PHY_ANLPAR_PSB_802_3); 174 miiphy_write(dev->name, fec->phy_id, MII_BMCR, 175 BMCR_ANENABLE | BMCR_ANRESTART); 176 return 0; 177 } 178 179 static int miiphy_wait_aneg(struct eth_device *dev) 180 { 181 uint32_t start; 182 uint16_t status; 183 struct fec_priv *fec = (struct fec_priv *)dev->priv; 184 185 /* 186 * Wait for AN completion 187 */ 188 start = get_timer(0); 189 do { 190 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { 191 printf("%s: Autonegotiation timeout\n", dev->name); 192 return -1; 193 } 194 195 if (miiphy_read(dev->name, fec->phy_id, 196 MII_BMSR, &status)) { 197 printf("%s: Autonegotiation failed. status: 0x%04x\n", 198 dev->name, status); 199 return -1; 200 } 201 } while (!(status & BMSR_LSTATUS)); 202 203 return 0; 204 } 205 static int fec_rx_task_enable(struct fec_priv *fec) 206 { 207 writel(1 << 24, &fec->eth->r_des_active); 208 return 0; 209 } 210 211 static int fec_rx_task_disable(struct fec_priv *fec) 212 { 213 return 0; 214 } 215 216 static int fec_tx_task_enable(struct fec_priv *fec) 217 { 218 writel(1 << 24, &fec->eth->x_des_active); 219 return 0; 220 } 221 222 static int fec_tx_task_disable(struct fec_priv *fec) 223 { 224 return 0; 225 } 226 227 /** 228 * Initialize receive task's buffer descriptors 229 * @param[in] fec all we know about the device yet 230 * @param[in] count receive buffer count to be allocated 231 * @param[in] size size of each receive buffer 232 * @return 0 on success 233 * 234 * For this task we need additional memory for the data buffers. And each 235 * data buffer requires some alignment. Thy must be aligned to a specific 236 * boundary each (DB_DATA_ALIGNMENT). 237 */ 238 static int fec_rbd_init(struct fec_priv *fec, int count, int size) 239 { 240 int ix; 241 uint32_t p = 0; 242 243 /* reserve data memory and consider alignment */ 244 if (fec->rdb_ptr == NULL) 245 fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT); 246 p = (uint32_t)fec->rdb_ptr; 247 if (!p) { 248 puts("fec_mxc: not enough malloc memory\n"); 249 return -ENOMEM; 250 } 251 memset((void *)p, 0, size * count + DB_DATA_ALIGNMENT); 252 p += DB_DATA_ALIGNMENT-1; 253 p &= ~(DB_DATA_ALIGNMENT-1); 254 255 for (ix = 0; ix < count; ix++) { 256 writel(p, &fec->rbd_base[ix].data_pointer); 257 p += size; 258 writew(FEC_RBD_EMPTY, &fec->rbd_base[ix].status); 259 writew(0, &fec->rbd_base[ix].data_length); 260 } 261 /* 262 * mark the last RBD to close the ring 263 */ 264 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[ix - 1].status); 265 fec->rbd_index = 0; 266 267 return 0; 268 } 269 270 /** 271 * Initialize transmit task's buffer descriptors 272 * @param[in] fec all we know about the device yet 273 * 274 * Transmit buffers are created externally. We only have to init the BDs here.\n 275 * Note: There is a race condition in the hardware. When only one BD is in 276 * use it must be marked with the WRAP bit to use it for every transmitt. 277 * This bit in combination with the READY bit results into double transmit 278 * of each data buffer. It seems the state machine checks READY earlier then 279 * resetting it after the first transfer. 280 * Using two BDs solves this issue. 281 */ 282 static void fec_tbd_init(struct fec_priv *fec) 283 { 284 writew(0x0000, &fec->tbd_base[0].status); 285 writew(FEC_TBD_WRAP, &fec->tbd_base[1].status); 286 fec->tbd_index = 0; 287 } 288 289 /** 290 * Mark the given read buffer descriptor as free 291 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0 292 * @param[in] pRbd buffer descriptor to mark free again 293 */ 294 static void fec_rbd_clean(int last, struct fec_bd *pRbd) 295 { 296 /* 297 * Reset buffer descriptor as empty 298 */ 299 if (last) 300 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &pRbd->status); 301 else 302 writew(FEC_RBD_EMPTY, &pRbd->status); 303 /* 304 * no data in it 305 */ 306 writew(0, &pRbd->data_length); 307 } 308 309 static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac) 310 { 311 imx_get_mac_from_fuse(mac); 312 return !is_valid_ether_addr(mac); 313 } 314 315 static int fec_set_hwaddr(struct eth_device *dev) 316 { 317 uchar *mac = dev->enetaddr; 318 struct fec_priv *fec = (struct fec_priv *)dev->priv; 319 320 writel(0, &fec->eth->iaddr1); 321 writel(0, &fec->eth->iaddr2); 322 writel(0, &fec->eth->gaddr1); 323 writel(0, &fec->eth->gaddr2); 324 325 /* 326 * Set physical address 327 */ 328 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3], 329 &fec->eth->paddr1); 330 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2); 331 332 return 0; 333 } 334 335 /** 336 * Start the FEC engine 337 * @param[in] dev Our device to handle 338 */ 339 static int fec_open(struct eth_device *edev) 340 { 341 struct fec_priv *fec = (struct fec_priv *)edev->priv; 342 343 debug("fec_open: fec_open(dev)\n"); 344 /* full-duplex, heartbeat disabled */ 345 writel(1 << 2, &fec->eth->x_cntrl); 346 fec->rbd_index = 0; 347 348 /* 349 * Enable FEC-Lite controller 350 */ 351 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, 352 &fec->eth->ecntrl); 353 #if defined(CONFIG_MX25) || defined(CONFIG_MX53) 354 udelay(100); 355 /* 356 * setup the MII gasket for RMII mode 357 */ 358 359 /* disable the gasket */ 360 writew(0, &fec->eth->miigsk_enr); 361 362 /* wait for the gasket to be disabled */ 363 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) 364 udelay(2); 365 366 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */ 367 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr); 368 369 /* re-enable the gasket */ 370 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr); 371 372 /* wait until MII gasket is ready */ 373 int max_loops = 10; 374 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) { 375 if (--max_loops <= 0) { 376 printf("WAIT for MII Gasket ready timed out\n"); 377 break; 378 } 379 } 380 #endif 381 382 miiphy_wait_aneg(edev); 383 miiphy_speed(edev->name, fec->phy_id); 384 miiphy_duplex(edev->name, fec->phy_id); 385 386 /* 387 * Enable SmartDMA receive task 388 */ 389 fec_rx_task_enable(fec); 390 391 udelay(100000); 392 return 0; 393 } 394 395 static int fec_init(struct eth_device *dev, bd_t* bd) 396 { 397 uint32_t base; 398 struct fec_priv *fec = (struct fec_priv *)dev->priv; 399 uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop; 400 uint32_t rcntrl; 401 int i; 402 403 /* Initialize MAC address */ 404 fec_set_hwaddr(dev); 405 406 /* 407 * reserve memory for both buffer descriptor chains at once 408 * Datasheet forces the startaddress of each chain is 16 byte 409 * aligned 410 */ 411 if (fec->base_ptr == NULL) 412 fec->base_ptr = malloc((2 + FEC_RBD_NUM) * 413 sizeof(struct fec_bd) + DB_ALIGNMENT); 414 base = (uint32_t)fec->base_ptr; 415 if (!base) { 416 puts("fec_mxc: not enough malloc memory\n"); 417 return -ENOMEM; 418 } 419 memset((void *)base, 0, (2 + FEC_RBD_NUM) * 420 sizeof(struct fec_bd) + DB_ALIGNMENT); 421 base += (DB_ALIGNMENT-1); 422 base &= ~(DB_ALIGNMENT-1); 423 424 fec->rbd_base = (struct fec_bd *)base; 425 426 base += FEC_RBD_NUM * sizeof(struct fec_bd); 427 428 fec->tbd_base = (struct fec_bd *)base; 429 430 /* 431 * Set interrupt mask register 432 */ 433 writel(0x00000000, &fec->eth->imask); 434 435 /* 436 * Clear FEC-Lite interrupt event register(IEVENT) 437 */ 438 writel(0xffffffff, &fec->eth->ievent); 439 440 441 /* 442 * Set FEC-Lite receive control register(R_CNTRL): 443 */ 444 445 /* Start with frame length = 1518, common for all modes. */ 446 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT; 447 if (fec->xcv_type == SEVENWIRE) 448 rcntrl |= FEC_RCNTRL_FCE; 449 else if (fec->xcv_type == RMII) 450 rcntrl |= FEC_RCNTRL_RMII; 451 else /* MII mode */ 452 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE; 453 454 writel(rcntrl, &fec->eth->r_cntrl); 455 456 if (fec->xcv_type == MII10 || fec->xcv_type == MII100) 457 fec_mii_setspeed(fec); 458 459 /* 460 * Set Opcode/Pause Duration Register 461 */ 462 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */ 463 writel(0x2, &fec->eth->x_wmrk); 464 /* 465 * Set multicast address filter 466 */ 467 writel(0x00000000, &fec->eth->gaddr1); 468 writel(0x00000000, &fec->eth->gaddr2); 469 470 471 /* clear MIB RAM */ 472 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) 473 writel(0, i); 474 475 /* FIFO receive start register */ 476 writel(0x520, &fec->eth->r_fstart); 477 478 /* size and address of each buffer */ 479 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr); 480 writel((uint32_t)fec->tbd_base, &fec->eth->etdsr); 481 writel((uint32_t)fec->rbd_base, &fec->eth->erdsr); 482 483 /* 484 * Initialize RxBD/TxBD rings 485 */ 486 if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) { 487 free(fec->base_ptr); 488 fec->base_ptr = NULL; 489 return -ENOMEM; 490 } 491 fec_tbd_init(fec); 492 493 494 if (fec->xcv_type != SEVENWIRE) 495 miiphy_restart_aneg(dev); 496 497 fec_open(dev); 498 return 0; 499 } 500 501 /** 502 * Halt the FEC engine 503 * @param[in] dev Our device to handle 504 */ 505 static void fec_halt(struct eth_device *dev) 506 { 507 struct fec_priv *fec = (struct fec_priv *)dev->priv; 508 int counter = 0xffff; 509 510 /* 511 * issue graceful stop command to the FEC transmitter if necessary 512 */ 513 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl), 514 &fec->eth->x_cntrl); 515 516 debug("eth_halt: wait for stop regs\n"); 517 /* 518 * wait for graceful stop to register 519 */ 520 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA))) 521 udelay(1); 522 523 /* 524 * Disable SmartDMA tasks 525 */ 526 fec_tx_task_disable(fec); 527 fec_rx_task_disable(fec); 528 529 /* 530 * Disable the Ethernet Controller 531 * Note: this will also reset the BD index counter! 532 */ 533 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN, 534 &fec->eth->ecntrl); 535 fec->rbd_index = 0; 536 fec->tbd_index = 0; 537 debug("eth_halt: done\n"); 538 } 539 540 /** 541 * Transmit one frame 542 * @param[in] dev Our ethernet device to handle 543 * @param[in] packet Pointer to the data to be transmitted 544 * @param[in] length Data count in bytes 545 * @return 0 on success 546 */ 547 static int fec_send(struct eth_device *dev, volatile void* packet, int length) 548 { 549 unsigned int status; 550 551 /* 552 * This routine transmits one frame. This routine only accepts 553 * 6-byte Ethernet addresses. 554 */ 555 struct fec_priv *fec = (struct fec_priv *)dev->priv; 556 557 /* 558 * Check for valid length of data. 559 */ 560 if ((length > 1500) || (length <= 0)) { 561 printf("Payload (%d) too large\n", length); 562 return -1; 563 } 564 565 /* 566 * Setup the transmit buffer 567 * Note: We are always using the first buffer for transmission, 568 * the second will be empty and only used to stop the DMA engine 569 */ 570 writew(length, &fec->tbd_base[fec->tbd_index].data_length); 571 writel((uint32_t)packet, &fec->tbd_base[fec->tbd_index].data_pointer); 572 /* 573 * update BD's status now 574 * This block: 575 * - is always the last in a chain (means no chain) 576 * - should transmitt the CRC 577 * - might be the last BD in the list, so the address counter should 578 * wrap (-> keep the WRAP flag) 579 */ 580 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP; 581 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; 582 writew(status, &fec->tbd_base[fec->tbd_index].status); 583 584 /* 585 * Enable SmartDMA transmit task 586 */ 587 fec_tx_task_enable(fec); 588 589 /* 590 * wait until frame is sent . 591 */ 592 while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) { 593 udelay(1); 594 } 595 debug("fec_send: status 0x%x index %d\n", 596 readw(&fec->tbd_base[fec->tbd_index].status), 597 fec->tbd_index); 598 /* for next transmission use the other buffer */ 599 if (fec->tbd_index) 600 fec->tbd_index = 0; 601 else 602 fec->tbd_index = 1; 603 604 return 0; 605 } 606 607 /** 608 * Pull one frame from the card 609 * @param[in] dev Our ethernet device to handle 610 * @return Length of packet read 611 */ 612 static int fec_recv(struct eth_device *dev) 613 { 614 struct fec_priv *fec = (struct fec_priv *)dev->priv; 615 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index]; 616 unsigned long ievent; 617 int frame_length, len = 0; 618 struct nbuf *frame; 619 uint16_t bd_status; 620 uchar buff[FEC_MAX_PKT_SIZE]; 621 622 /* 623 * Check if any critical events have happened 624 */ 625 ievent = readl(&fec->eth->ievent); 626 writel(ievent, &fec->eth->ievent); 627 debug("fec_recv: ievent 0x%x\n", ievent); 628 if (ievent & FEC_IEVENT_BABR) { 629 fec_halt(dev); 630 fec_init(dev, fec->bd); 631 printf("some error: 0x%08lx\n", ievent); 632 return 0; 633 } 634 if (ievent & FEC_IEVENT_HBERR) { 635 /* Heartbeat error */ 636 writel(0x00000001 | readl(&fec->eth->x_cntrl), 637 &fec->eth->x_cntrl); 638 } 639 if (ievent & FEC_IEVENT_GRA) { 640 /* Graceful stop complete */ 641 if (readl(&fec->eth->x_cntrl) & 0x00000001) { 642 fec_halt(dev); 643 writel(~0x00000001 & readl(&fec->eth->x_cntrl), 644 &fec->eth->x_cntrl); 645 fec_init(dev, fec->bd); 646 } 647 } 648 649 /* 650 * ensure reading the right buffer status 651 */ 652 bd_status = readw(&rbd->status); 653 debug("fec_recv: status 0x%x\n", bd_status); 654 655 if (!(bd_status & FEC_RBD_EMPTY)) { 656 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) && 657 ((readw(&rbd->data_length) - 4) > 14)) { 658 /* 659 * Get buffer address and size 660 */ 661 frame = (struct nbuf *)readl(&rbd->data_pointer); 662 frame_length = readw(&rbd->data_length) - 4; 663 /* 664 * Fill the buffer and pass it to upper layers 665 */ 666 memcpy(buff, frame->data, frame_length); 667 NetReceive(buff, frame_length); 668 len = frame_length; 669 } else { 670 if (bd_status & FEC_RBD_ERR) 671 printf("error frame: 0x%08lx 0x%08x\n", 672 (ulong)rbd->data_pointer, 673 bd_status); 674 } 675 /* 676 * free the current buffer, restart the engine 677 * and move forward to the next buffer 678 */ 679 fec_rbd_clean(fec->rbd_index == (FEC_RBD_NUM - 1) ? 1 : 0, rbd); 680 fec_rx_task_enable(fec); 681 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM; 682 } 683 debug("fec_recv: stop\n"); 684 685 return len; 686 } 687 688 static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr) 689 { 690 struct eth_device *edev; 691 struct fec_priv *fec; 692 unsigned char ethaddr[6]; 693 694 /* create and fill edev struct */ 695 edev = (struct eth_device *)malloc(sizeof(struct eth_device)); 696 if (!edev) { 697 puts("fec_mxc: not enough malloc memory for eth_device\n"); 698 return -ENOMEM; 699 } 700 701 fec = (struct fec_priv *)malloc(sizeof(struct fec_priv)); 702 if (!fec) { 703 puts("fec_mxc: not enough malloc memory for fec_priv\n"); 704 return -ENOMEM; 705 } 706 707 memset(edev, 0, sizeof(*edev)); 708 memset(fec, 0, sizeof(*fec)); 709 710 edev->priv = fec; 711 edev->init = fec_init; 712 edev->send = fec_send; 713 edev->recv = fec_recv; 714 edev->halt = fec_halt; 715 edev->write_hwaddr = fec_set_hwaddr; 716 717 fec->eth = (struct ethernet_regs *)base_addr; 718 fec->bd = bd; 719 720 fec->xcv_type = CONFIG_FEC_XCV_TYPE; 721 722 /* Reset chip. */ 723 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl); 724 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) 725 udelay(10); 726 727 /* 728 * Set interrupt mask register 729 */ 730 writel(0x00000000, &fec->eth->imask); 731 732 /* 733 * Clear FEC-Lite interrupt event register(IEVENT) 734 */ 735 writel(0xffffffff, &fec->eth->ievent); 736 737 /* 738 * Set FEC-Lite receive control register(R_CNTRL): 739 */ 740 /* 741 * Frame length=1518; MII mode; 742 */ 743 writel((PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT) | FEC_RCNTRL_FCE | 744 FEC_RCNTRL_MII_MODE, &fec->eth->r_cntrl); 745 fec_mii_setspeed(fec); 746 747 if (dev_id == -1) { 748 sprintf(edev->name, "FEC"); 749 fec->dev_id = 0; 750 } else { 751 sprintf(edev->name, "FEC%i", dev_id); 752 fec->dev_id = dev_id; 753 } 754 fec->phy_id = phy_id; 755 756 miiphy_register(edev->name, fec_miiphy_read, fec_miiphy_write); 757 758 eth_register(edev); 759 760 if (fec_get_hwaddr(edev, ethaddr) == 0) { 761 printf("got MAC address from fuse: %pM\n", ethaddr); 762 memcpy(edev->enetaddr, ethaddr, 6); 763 } 764 765 return 0; 766 } 767 768 #ifndef CONFIG_FEC_MXC_MULTI 769 int fecmxc_initialize(bd_t *bd) 770 { 771 int lout = 1; 772 773 debug("eth_init: fec_probe(bd)\n"); 774 lout = fec_probe(bd, -1, CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); 775 776 return lout; 777 } 778 #endif 779 780 int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr) 781 { 782 int lout = 1; 783 784 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr); 785 lout = fec_probe(bd, dev_id, phy_id, addr); 786 787 return lout; 788 } 789