1 /* 2 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com> 3 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org> 4 * (C) Copyright 2008 Armadeus Systems nc 5 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 6 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <malloc.h> 26 #include <net.h> 27 #include <miiphy.h> 28 #include "fec_mxc.h" 29 30 #include <asm/arch/clock.h> 31 #include <asm/arch/imx-regs.h> 32 #include <asm/io.h> 33 #include <asm/errno.h> 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 #ifndef CONFIG_MII 38 #error "CONFIG_MII has to be defined!" 39 #endif 40 41 #ifndef CONFIG_FEC_XCV_TYPE 42 #define CONFIG_FEC_XCV_TYPE MII100 43 #endif 44 45 #undef DEBUG 46 47 struct nbuf { 48 uint8_t data[1500]; /**< actual data */ 49 int length; /**< actual length */ 50 int used; /**< buffer in use or not */ 51 uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */ 52 }; 53 54 struct fec_priv gfec = { 55 .eth = (struct ethernet_regs *)IMX_FEC_BASE, 56 .xcv_type = MII100, 57 .rbd_base = NULL, 58 .rbd_index = 0, 59 .tbd_base = NULL, 60 .tbd_index = 0, 61 .bd = NULL, 62 .rdb_ptr = NULL, 63 .base_ptr = NULL, 64 }; 65 66 /* 67 * MII-interface related functions 68 */ 69 static int fec_miiphy_read(const char *dev, uint8_t phyAddr, uint8_t regAddr, 70 uint16_t *retVal) 71 { 72 struct eth_device *edev = eth_get_dev_by_name(dev); 73 struct fec_priv *fec = (struct fec_priv *)edev->priv; 74 75 uint32_t reg; /* convenient holder for the PHY register */ 76 uint32_t phy; /* convenient holder for the PHY */ 77 uint32_t start; 78 79 /* 80 * reading from any PHY's register is done by properly 81 * programming the FEC's MII data register. 82 */ 83 writel(FEC_IEVENT_MII, &fec->eth->ievent); 84 reg = regAddr << FEC_MII_DATA_RA_SHIFT; 85 phy = phyAddr << FEC_MII_DATA_PA_SHIFT; 86 87 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | 88 phy | reg, &fec->eth->mii_data); 89 90 /* 91 * wait for the related interrupt 92 */ 93 start = get_timer(0); 94 while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) { 95 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { 96 printf("Read MDIO failed...\n"); 97 return -1; 98 } 99 } 100 101 /* 102 * clear mii interrupt bit 103 */ 104 writel(FEC_IEVENT_MII, &fec->eth->ievent); 105 106 /* 107 * it's now safe to read the PHY's register 108 */ 109 *retVal = readl(&fec->eth->mii_data); 110 debug("fec_miiphy_read: phy: %02x reg:%02x val:%#x\n", phyAddr, 111 regAddr, *retVal); 112 return 0; 113 } 114 115 static void fec_mii_setspeed(struct fec_priv *fec) 116 { 117 /* 118 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock 119 * and do not drop the Preamble. 120 */ 121 writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1, 122 &fec->eth->mii_speed); 123 debug("fec_init: mii_speed %#lx\n", 124 readl(&fec->eth->mii_speed)); 125 } 126 static int fec_miiphy_write(const char *dev, uint8_t phyAddr, uint8_t regAddr, 127 uint16_t data) 128 { 129 struct eth_device *edev = eth_get_dev_by_name(dev); 130 struct fec_priv *fec = (struct fec_priv *)edev->priv; 131 132 uint32_t reg; /* convenient holder for the PHY register */ 133 uint32_t phy; /* convenient holder for the PHY */ 134 uint32_t start; 135 136 reg = regAddr << FEC_MII_DATA_RA_SHIFT; 137 phy = phyAddr << FEC_MII_DATA_PA_SHIFT; 138 139 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | 140 FEC_MII_DATA_TA | phy | reg | data, &fec->eth->mii_data); 141 142 /* 143 * wait for the MII interrupt 144 */ 145 start = get_timer(0); 146 while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) { 147 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { 148 printf("Write MDIO failed...\n"); 149 return -1; 150 } 151 } 152 153 /* 154 * clear MII interrupt bit 155 */ 156 writel(FEC_IEVENT_MII, &fec->eth->ievent); 157 debug("fec_miiphy_write: phy: %02x reg:%02x val:%#x\n", phyAddr, 158 regAddr, data); 159 160 return 0; 161 } 162 163 static int miiphy_restart_aneg(struct eth_device *dev) 164 { 165 /* 166 * Wake up from sleep if necessary 167 * Reset PHY, then delay 300ns 168 */ 169 #ifdef CONFIG_MX27 170 miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, MII_DCOUNTER, 0x00FF); 171 #endif 172 miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, MII_BMCR, 173 BMCR_RESET); 174 udelay(1000); 175 176 /* 177 * Set the auto-negotiation advertisement register bits 178 */ 179 miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, MII_ADVERTISE, 180 LPA_100FULL | LPA_100HALF | LPA_10FULL | 181 LPA_10HALF | PHY_ANLPAR_PSB_802_3); 182 miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, MII_BMCR, 183 BMCR_ANENABLE | BMCR_ANRESTART); 184 185 return 0; 186 } 187 188 static int miiphy_wait_aneg(struct eth_device *dev) 189 { 190 uint32_t start; 191 uint16_t status; 192 193 /* 194 * Wait for AN completion 195 */ 196 start = get_timer(0); 197 do { 198 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { 199 printf("%s: Autonegotiation timeout\n", dev->name); 200 return -1; 201 } 202 203 if (miiphy_read(dev->name, CONFIG_FEC_MXC_PHYADDR, 204 MII_BMSR, &status)) { 205 printf("%s: Autonegotiation failed. status: 0x%04x\n", 206 dev->name, status); 207 return -1; 208 } 209 } while (!(status & BMSR_LSTATUS)); 210 211 return 0; 212 } 213 static int fec_rx_task_enable(struct fec_priv *fec) 214 { 215 writel(1 << 24, &fec->eth->r_des_active); 216 return 0; 217 } 218 219 static int fec_rx_task_disable(struct fec_priv *fec) 220 { 221 return 0; 222 } 223 224 static int fec_tx_task_enable(struct fec_priv *fec) 225 { 226 writel(1 << 24, &fec->eth->x_des_active); 227 return 0; 228 } 229 230 static int fec_tx_task_disable(struct fec_priv *fec) 231 { 232 return 0; 233 } 234 235 /** 236 * Initialize receive task's buffer descriptors 237 * @param[in] fec all we know about the device yet 238 * @param[in] count receive buffer count to be allocated 239 * @param[in] size size of each receive buffer 240 * @return 0 on success 241 * 242 * For this task we need additional memory for the data buffers. And each 243 * data buffer requires some alignment. Thy must be aligned to a specific 244 * boundary each (DB_DATA_ALIGNMENT). 245 */ 246 static int fec_rbd_init(struct fec_priv *fec, int count, int size) 247 { 248 int ix; 249 uint32_t p = 0; 250 251 /* reserve data memory and consider alignment */ 252 if (fec->rdb_ptr == NULL) 253 fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT); 254 p = (uint32_t)fec->rdb_ptr; 255 if (!p) { 256 puts("fec_mxc: not enough malloc memory\n"); 257 return -ENOMEM; 258 } 259 memset((void *)p, 0, size * count + DB_DATA_ALIGNMENT); 260 p += DB_DATA_ALIGNMENT-1; 261 p &= ~(DB_DATA_ALIGNMENT-1); 262 263 for (ix = 0; ix < count; ix++) { 264 writel(p, &fec->rbd_base[ix].data_pointer); 265 p += size; 266 writew(FEC_RBD_EMPTY, &fec->rbd_base[ix].status); 267 writew(0, &fec->rbd_base[ix].data_length); 268 } 269 /* 270 * mark the last RBD to close the ring 271 */ 272 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[ix - 1].status); 273 fec->rbd_index = 0; 274 275 return 0; 276 } 277 278 /** 279 * Initialize transmit task's buffer descriptors 280 * @param[in] fec all we know about the device yet 281 * 282 * Transmit buffers are created externally. We only have to init the BDs here.\n 283 * Note: There is a race condition in the hardware. When only one BD is in 284 * use it must be marked with the WRAP bit to use it for every transmitt. 285 * This bit in combination with the READY bit results into double transmit 286 * of each data buffer. It seems the state machine checks READY earlier then 287 * resetting it after the first transfer. 288 * Using two BDs solves this issue. 289 */ 290 static void fec_tbd_init(struct fec_priv *fec) 291 { 292 writew(0x0000, &fec->tbd_base[0].status); 293 writew(FEC_TBD_WRAP, &fec->tbd_base[1].status); 294 fec->tbd_index = 0; 295 } 296 297 /** 298 * Mark the given read buffer descriptor as free 299 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0 300 * @param[in] pRbd buffer descriptor to mark free again 301 */ 302 static void fec_rbd_clean(int last, struct fec_bd *pRbd) 303 { 304 /* 305 * Reset buffer descriptor as empty 306 */ 307 if (last) 308 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &pRbd->status); 309 else 310 writew(FEC_RBD_EMPTY, &pRbd->status); 311 /* 312 * no data in it 313 */ 314 writew(0, &pRbd->data_length); 315 } 316 317 static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac) 318 { 319 imx_get_mac_from_fuse(mac); 320 return !is_valid_ether_addr(mac); 321 } 322 323 static int fec_set_hwaddr(struct eth_device *dev) 324 { 325 uchar *mac = dev->enetaddr; 326 struct fec_priv *fec = (struct fec_priv *)dev->priv; 327 328 writel(0, &fec->eth->iaddr1); 329 writel(0, &fec->eth->iaddr2); 330 writel(0, &fec->eth->gaddr1); 331 writel(0, &fec->eth->gaddr2); 332 333 /* 334 * Set physical address 335 */ 336 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3], 337 &fec->eth->paddr1); 338 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2); 339 340 return 0; 341 } 342 343 /** 344 * Start the FEC engine 345 * @param[in] dev Our device to handle 346 */ 347 static int fec_open(struct eth_device *edev) 348 { 349 struct fec_priv *fec = (struct fec_priv *)edev->priv; 350 351 debug("fec_open: fec_open(dev)\n"); 352 /* full-duplex, heartbeat disabled */ 353 writel(1 << 2, &fec->eth->x_cntrl); 354 fec->rbd_index = 0; 355 356 /* 357 * Enable FEC-Lite controller 358 */ 359 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, 360 &fec->eth->ecntrl); 361 #if defined(CONFIG_MX25) || defined(CONFIG_MX53) 362 udelay(100); 363 /* 364 * setup the MII gasket for RMII mode 365 */ 366 367 /* disable the gasket */ 368 writew(0, &fec->eth->miigsk_enr); 369 370 /* wait for the gasket to be disabled */ 371 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) 372 udelay(2); 373 374 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */ 375 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr); 376 377 /* re-enable the gasket */ 378 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr); 379 380 /* wait until MII gasket is ready */ 381 int max_loops = 10; 382 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) { 383 if (--max_loops <= 0) { 384 printf("WAIT for MII Gasket ready timed out\n"); 385 break; 386 } 387 } 388 #endif 389 390 miiphy_wait_aneg(edev); 391 miiphy_speed(edev->name, CONFIG_FEC_MXC_PHYADDR); 392 miiphy_duplex(edev->name, CONFIG_FEC_MXC_PHYADDR); 393 394 /* 395 * Enable SmartDMA receive task 396 */ 397 fec_rx_task_enable(fec); 398 399 udelay(100000); 400 return 0; 401 } 402 403 static int fec_init(struct eth_device *dev, bd_t* bd) 404 { 405 uint32_t base; 406 struct fec_priv *fec = (struct fec_priv *)dev->priv; 407 uint32_t rcntrl; 408 409 /* Initialize MAC address */ 410 fec_set_hwaddr(dev); 411 412 /* 413 * reserve memory for both buffer descriptor chains at once 414 * Datasheet forces the startaddress of each chain is 16 byte 415 * aligned 416 */ 417 if (fec->base_ptr == NULL) 418 fec->base_ptr = malloc((2 + FEC_RBD_NUM) * 419 sizeof(struct fec_bd) + DB_ALIGNMENT); 420 base = (uint32_t)fec->base_ptr; 421 if (!base) { 422 puts("fec_mxc: not enough malloc memory\n"); 423 return -ENOMEM; 424 } 425 memset((void *)base, 0, (2 + FEC_RBD_NUM) * 426 sizeof(struct fec_bd) + DB_ALIGNMENT); 427 base += (DB_ALIGNMENT-1); 428 base &= ~(DB_ALIGNMENT-1); 429 430 fec->rbd_base = (struct fec_bd *)base; 431 432 base += FEC_RBD_NUM * sizeof(struct fec_bd); 433 434 fec->tbd_base = (struct fec_bd *)base; 435 436 /* 437 * Set interrupt mask register 438 */ 439 writel(0x00000000, &fec->eth->imask); 440 441 /* 442 * Clear FEC-Lite interrupt event register(IEVENT) 443 */ 444 writel(0xffffffff, &fec->eth->ievent); 445 446 447 /* 448 * Set FEC-Lite receive control register(R_CNTRL): 449 */ 450 451 /* Start with frame length = 1518, common for all modes. */ 452 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT; 453 if (fec->xcv_type == SEVENWIRE) 454 rcntrl |= FEC_RCNTRL_FCE; 455 else if (fec->xcv_type == RMII) 456 rcntrl |= FEC_RCNTRL_RMII; 457 else /* MII mode */ 458 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE; 459 460 writel(rcntrl, &fec->eth->r_cntrl); 461 462 if (fec->xcv_type == MII10 || fec->xcv_type == MII100) 463 fec_mii_setspeed(fec); 464 465 /* 466 * Set Opcode/Pause Duration Register 467 */ 468 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */ 469 writel(0x2, &fec->eth->x_wmrk); 470 /* 471 * Set multicast address filter 472 */ 473 writel(0x00000000, &fec->eth->gaddr1); 474 writel(0x00000000, &fec->eth->gaddr2); 475 476 477 /* clear MIB RAM */ 478 long *mib_ptr = (long *)(IMX_FEC_BASE + 0x200); 479 while (mib_ptr <= (long *)(IMX_FEC_BASE + 0x2FC)) 480 *mib_ptr++ = 0; 481 482 /* FIFO receive start register */ 483 writel(0x520, &fec->eth->r_fstart); 484 485 /* size and address of each buffer */ 486 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr); 487 writel((uint32_t)fec->tbd_base, &fec->eth->etdsr); 488 writel((uint32_t)fec->rbd_base, &fec->eth->erdsr); 489 490 /* 491 * Initialize RxBD/TxBD rings 492 */ 493 if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) { 494 free(fec->base_ptr); 495 fec->base_ptr = NULL; 496 return -ENOMEM; 497 } 498 fec_tbd_init(fec); 499 500 501 if (fec->xcv_type != SEVENWIRE) 502 miiphy_restart_aneg(dev); 503 504 fec_open(dev); 505 return 0; 506 } 507 508 /** 509 * Halt the FEC engine 510 * @param[in] dev Our device to handle 511 */ 512 static void fec_halt(struct eth_device *dev) 513 { 514 struct fec_priv *fec = &gfec; 515 int counter = 0xffff; 516 517 /* 518 * issue graceful stop command to the FEC transmitter if necessary 519 */ 520 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl), 521 &fec->eth->x_cntrl); 522 523 debug("eth_halt: wait for stop regs\n"); 524 /* 525 * wait for graceful stop to register 526 */ 527 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA))) 528 udelay(1); 529 530 /* 531 * Disable SmartDMA tasks 532 */ 533 fec_tx_task_disable(fec); 534 fec_rx_task_disable(fec); 535 536 /* 537 * Disable the Ethernet Controller 538 * Note: this will also reset the BD index counter! 539 */ 540 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN, 541 &fec->eth->ecntrl); 542 fec->rbd_index = 0; 543 fec->tbd_index = 0; 544 debug("eth_halt: done\n"); 545 } 546 547 /** 548 * Transmit one frame 549 * @param[in] dev Our ethernet device to handle 550 * @param[in] packet Pointer to the data to be transmitted 551 * @param[in] length Data count in bytes 552 * @return 0 on success 553 */ 554 static int fec_send(struct eth_device *dev, volatile void* packet, int length) 555 { 556 unsigned int status; 557 558 /* 559 * This routine transmits one frame. This routine only accepts 560 * 6-byte Ethernet addresses. 561 */ 562 struct fec_priv *fec = (struct fec_priv *)dev->priv; 563 564 /* 565 * Check for valid length of data. 566 */ 567 if ((length > 1500) || (length <= 0)) { 568 printf("Payload (%d) too large\n", length); 569 return -1; 570 } 571 572 /* 573 * Setup the transmit buffer 574 * Note: We are always using the first buffer for transmission, 575 * the second will be empty and only used to stop the DMA engine 576 */ 577 writew(length, &fec->tbd_base[fec->tbd_index].data_length); 578 writel((uint32_t)packet, &fec->tbd_base[fec->tbd_index].data_pointer); 579 /* 580 * update BD's status now 581 * This block: 582 * - is always the last in a chain (means no chain) 583 * - should transmitt the CRC 584 * - might be the last BD in the list, so the address counter should 585 * wrap (-> keep the WRAP flag) 586 */ 587 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP; 588 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; 589 writew(status, &fec->tbd_base[fec->tbd_index].status); 590 591 /* 592 * Enable SmartDMA transmit task 593 */ 594 fec_tx_task_enable(fec); 595 596 /* 597 * wait until frame is sent . 598 */ 599 while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) { 600 udelay(1); 601 } 602 debug("fec_send: status 0x%x index %d\n", 603 readw(&fec->tbd_base[fec->tbd_index].status), 604 fec->tbd_index); 605 /* for next transmission use the other buffer */ 606 if (fec->tbd_index) 607 fec->tbd_index = 0; 608 else 609 fec->tbd_index = 1; 610 611 return 0; 612 } 613 614 /** 615 * Pull one frame from the card 616 * @param[in] dev Our ethernet device to handle 617 * @return Length of packet read 618 */ 619 static int fec_recv(struct eth_device *dev) 620 { 621 struct fec_priv *fec = (struct fec_priv *)dev->priv; 622 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index]; 623 unsigned long ievent; 624 int frame_length, len = 0; 625 struct nbuf *frame; 626 uint16_t bd_status; 627 uchar buff[FEC_MAX_PKT_SIZE]; 628 629 /* 630 * Check if any critical events have happened 631 */ 632 ievent = readl(&fec->eth->ievent); 633 writel(ievent, &fec->eth->ievent); 634 debug("fec_recv: ievent 0x%x\n", ievent); 635 if (ievent & FEC_IEVENT_BABR) { 636 fec_halt(dev); 637 fec_init(dev, fec->bd); 638 printf("some error: 0x%08lx\n", ievent); 639 return 0; 640 } 641 if (ievent & FEC_IEVENT_HBERR) { 642 /* Heartbeat error */ 643 writel(0x00000001 | readl(&fec->eth->x_cntrl), 644 &fec->eth->x_cntrl); 645 } 646 if (ievent & FEC_IEVENT_GRA) { 647 /* Graceful stop complete */ 648 if (readl(&fec->eth->x_cntrl) & 0x00000001) { 649 fec_halt(dev); 650 writel(~0x00000001 & readl(&fec->eth->x_cntrl), 651 &fec->eth->x_cntrl); 652 fec_init(dev, fec->bd); 653 } 654 } 655 656 /* 657 * ensure reading the right buffer status 658 */ 659 bd_status = readw(&rbd->status); 660 debug("fec_recv: status 0x%x\n", bd_status); 661 662 if (!(bd_status & FEC_RBD_EMPTY)) { 663 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) && 664 ((readw(&rbd->data_length) - 4) > 14)) { 665 /* 666 * Get buffer address and size 667 */ 668 frame = (struct nbuf *)readl(&rbd->data_pointer); 669 frame_length = readw(&rbd->data_length) - 4; 670 /* 671 * Fill the buffer and pass it to upper layers 672 */ 673 memcpy(buff, frame->data, frame_length); 674 NetReceive(buff, frame_length); 675 len = frame_length; 676 } else { 677 if (bd_status & FEC_RBD_ERR) 678 printf("error frame: 0x%08lx 0x%08x\n", 679 (ulong)rbd->data_pointer, 680 bd_status); 681 } 682 /* 683 * free the current buffer, restart the engine 684 * and move forward to the next buffer 685 */ 686 fec_rbd_clean(fec->rbd_index == (FEC_RBD_NUM - 1) ? 1 : 0, rbd); 687 fec_rx_task_enable(fec); 688 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM; 689 } 690 debug("fec_recv: stop\n"); 691 692 return len; 693 } 694 695 static int fec_probe(bd_t *bd) 696 { 697 struct eth_device *edev; 698 struct fec_priv *fec = &gfec; 699 unsigned char ethaddr[6]; 700 701 /* create and fill edev struct */ 702 edev = (struct eth_device *)malloc(sizeof(struct eth_device)); 703 if (!edev) { 704 puts("fec_mxc: not enough malloc memory\n"); 705 return -ENOMEM; 706 } 707 memset(edev, 0, sizeof(*edev)); 708 edev->priv = fec; 709 edev->init = fec_init; 710 edev->send = fec_send; 711 edev->recv = fec_recv; 712 edev->halt = fec_halt; 713 edev->write_hwaddr = fec_set_hwaddr; 714 715 fec->eth = (struct ethernet_regs *)IMX_FEC_BASE; 716 fec->bd = bd; 717 718 fec->xcv_type = CONFIG_FEC_XCV_TYPE; 719 720 /* Reset chip. */ 721 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl); 722 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) 723 udelay(10); 724 725 /* 726 * Set interrupt mask register 727 */ 728 writel(0x00000000, &fec->eth->imask); 729 730 /* 731 * Clear FEC-Lite interrupt event register(IEVENT) 732 */ 733 writel(0xffffffff, &fec->eth->ievent); 734 735 /* 736 * Set FEC-Lite receive control register(R_CNTRL): 737 */ 738 /* 739 * Frame length=1518; MII mode; 740 */ 741 writel((PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT) | FEC_RCNTRL_FCE | 742 FEC_RCNTRL_MII_MODE, &fec->eth->r_cntrl); 743 fec_mii_setspeed(fec); 744 745 sprintf(edev->name, "FEC"); 746 747 miiphy_register(edev->name, fec_miiphy_read, fec_miiphy_write); 748 749 eth_register(edev); 750 751 if (fec_get_hwaddr(edev, ethaddr) == 0) { 752 printf("got MAC address from fuse: %pM\n", ethaddr); 753 memcpy(edev->enetaddr, ethaddr, 6); 754 } 755 756 return 0; 757 } 758 759 int fecmxc_initialize(bd_t *bd) 760 { 761 int lout = 1; 762 763 debug("eth_init: fec_probe(bd)\n"); 764 lout = fec_probe(bd); 765 766 return lout; 767 } 768