1*594d57d0SMatthias Kaehlcke /* 2*594d57d0SMatthias Kaehlcke * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> 3*594d57d0SMatthias Kaehlcke * 4*594d57d0SMatthias Kaehlcke * Copyright (C) 2004, 2005 5*594d57d0SMatthias Kaehlcke * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com> 6*594d57d0SMatthias Kaehlcke * 7*594d57d0SMatthias Kaehlcke * See file CREDITS for list of people who contributed to this 8*594d57d0SMatthias Kaehlcke * project. 9*594d57d0SMatthias Kaehlcke * 10*594d57d0SMatthias Kaehlcke * This program is free software; you can redistribute it and/or 11*594d57d0SMatthias Kaehlcke * modify it under the terms of the GNU General Public License as 12*594d57d0SMatthias Kaehlcke * published by the Free Software Foundation; either version 2 of 13*594d57d0SMatthias Kaehlcke * the License, or (at your option) any later version. 14*594d57d0SMatthias Kaehlcke * 15*594d57d0SMatthias Kaehlcke * This program is distributed in the hope that it will be useful, 16*594d57d0SMatthias Kaehlcke * but WITHOUT ANY WARRANTY; without even the implied warranty of 17*594d57d0SMatthias Kaehlcke * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18*594d57d0SMatthias Kaehlcke * GNU General Public License for more details. 19*594d57d0SMatthias Kaehlcke * 20*594d57d0SMatthias Kaehlcke * You should have received a copy of the GNU General Public License 21*594d57d0SMatthias Kaehlcke * along with this program; if not, write to the Free Software 22*594d57d0SMatthias Kaehlcke * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23*594d57d0SMatthias Kaehlcke * MA 02111-1307 USA 24*594d57d0SMatthias Kaehlcke * 25*594d57d0SMatthias Kaehlcke */ 26*594d57d0SMatthias Kaehlcke 27*594d57d0SMatthias Kaehlcke #ifndef _EP93XX_ETH_H 28*594d57d0SMatthias Kaehlcke #define _EP93XX_ETH_H 29*594d57d0SMatthias Kaehlcke 30*594d57d0SMatthias Kaehlcke #include <net.h> 31*594d57d0SMatthias Kaehlcke 32*594d57d0SMatthias Kaehlcke /** 33*594d57d0SMatthias Kaehlcke * #define this to dump device status and queue info during initialization and 34*594d57d0SMatthias Kaehlcke * following errors. 35*594d57d0SMatthias Kaehlcke */ 36*594d57d0SMatthias Kaehlcke #undef EP93XX_MAC_DEBUG 37*594d57d0SMatthias Kaehlcke 38*594d57d0SMatthias Kaehlcke /** 39*594d57d0SMatthias Kaehlcke * Number of descriptor and status entries in our RX queues. 40*594d57d0SMatthias Kaehlcke * It must be power of 2 ! 41*594d57d0SMatthias Kaehlcke */ 42*594d57d0SMatthias Kaehlcke #define NUMRXDESC PKTBUFSRX 43*594d57d0SMatthias Kaehlcke 44*594d57d0SMatthias Kaehlcke /** 45*594d57d0SMatthias Kaehlcke * Number of descriptor and status entries in our TX queues. 46*594d57d0SMatthias Kaehlcke */ 47*594d57d0SMatthias Kaehlcke #define NUMTXDESC 1 48*594d57d0SMatthias Kaehlcke 49*594d57d0SMatthias Kaehlcke /** 50*594d57d0SMatthias Kaehlcke * 944 = (1024 - 64) - 16, Fifo size - Minframesize - 16 (Chip FACT) 51*594d57d0SMatthias Kaehlcke */ 52*594d57d0SMatthias Kaehlcke #define TXSTARTMAX 944 53*594d57d0SMatthias Kaehlcke 54*594d57d0SMatthias Kaehlcke /** 55*594d57d0SMatthias Kaehlcke * Receive descriptor queue entry 56*594d57d0SMatthias Kaehlcke */ 57*594d57d0SMatthias Kaehlcke struct rx_descriptor { 58*594d57d0SMatthias Kaehlcke uint32_t word1; 59*594d57d0SMatthias Kaehlcke uint32_t word2; 60*594d57d0SMatthias Kaehlcke }; 61*594d57d0SMatthias Kaehlcke 62*594d57d0SMatthias Kaehlcke /** 63*594d57d0SMatthias Kaehlcke * Receive status queue entry 64*594d57d0SMatthias Kaehlcke */ 65*594d57d0SMatthias Kaehlcke struct rx_status { 66*594d57d0SMatthias Kaehlcke uint32_t word1; 67*594d57d0SMatthias Kaehlcke uint32_t word2; 68*594d57d0SMatthias Kaehlcke }; 69*594d57d0SMatthias Kaehlcke 70*594d57d0SMatthias Kaehlcke #define RX_STATUS_RWE(rx_status) ((rx_status->word1 >> 30) & 0x01) 71*594d57d0SMatthias Kaehlcke #define RX_STATUS_RFP(rx_status) ((rx_status->word1 >> 31) & 0x01) 72*594d57d0SMatthias Kaehlcke #define RX_STATUS_FRAME_LEN(rx_status) (rx_status->word2 & 0xFFFF) 73*594d57d0SMatthias Kaehlcke 74*594d57d0SMatthias Kaehlcke /** 75*594d57d0SMatthias Kaehlcke * Transmit descriptor queue entry 76*594d57d0SMatthias Kaehlcke */ 77*594d57d0SMatthias Kaehlcke struct tx_descriptor { 78*594d57d0SMatthias Kaehlcke uint32_t word1; 79*594d57d0SMatthias Kaehlcke uint32_t word2; 80*594d57d0SMatthias Kaehlcke }; 81*594d57d0SMatthias Kaehlcke 82*594d57d0SMatthias Kaehlcke #define TX_DESC_EOF (1 << 31) 83*594d57d0SMatthias Kaehlcke 84*594d57d0SMatthias Kaehlcke /** 85*594d57d0SMatthias Kaehlcke * Transmit status queue entry 86*594d57d0SMatthias Kaehlcke */ 87*594d57d0SMatthias Kaehlcke struct tx_status { 88*594d57d0SMatthias Kaehlcke uint32_t word1; 89*594d57d0SMatthias Kaehlcke }; 90*594d57d0SMatthias Kaehlcke 91*594d57d0SMatthias Kaehlcke #define TX_STATUS_TXWE(tx_status) (((tx_status)->word1 >> 30) & 0x01) 92*594d57d0SMatthias Kaehlcke #define TX_STATUS_TXFP(tx_status) (((tx_status)->word1 >> 31) & 0x01) 93*594d57d0SMatthias Kaehlcke 94*594d57d0SMatthias Kaehlcke /** 95*594d57d0SMatthias Kaehlcke * Transmit descriptor queue 96*594d57d0SMatthias Kaehlcke */ 97*594d57d0SMatthias Kaehlcke struct tx_descriptor_queue { 98*594d57d0SMatthias Kaehlcke struct tx_descriptor *base; 99*594d57d0SMatthias Kaehlcke struct tx_descriptor *current; 100*594d57d0SMatthias Kaehlcke struct tx_descriptor *end; 101*594d57d0SMatthias Kaehlcke }; 102*594d57d0SMatthias Kaehlcke 103*594d57d0SMatthias Kaehlcke /** 104*594d57d0SMatthias Kaehlcke * Transmit status queue 105*594d57d0SMatthias Kaehlcke */ 106*594d57d0SMatthias Kaehlcke struct tx_status_queue { 107*594d57d0SMatthias Kaehlcke struct tx_status *base; 108*594d57d0SMatthias Kaehlcke volatile struct tx_status *current; 109*594d57d0SMatthias Kaehlcke struct tx_status *end; 110*594d57d0SMatthias Kaehlcke }; 111*594d57d0SMatthias Kaehlcke 112*594d57d0SMatthias Kaehlcke /** 113*594d57d0SMatthias Kaehlcke * Receive descriptor queue 114*594d57d0SMatthias Kaehlcke */ 115*594d57d0SMatthias Kaehlcke struct rx_descriptor_queue { 116*594d57d0SMatthias Kaehlcke struct rx_descriptor *base; 117*594d57d0SMatthias Kaehlcke struct rx_descriptor *current; 118*594d57d0SMatthias Kaehlcke struct rx_descriptor *end; 119*594d57d0SMatthias Kaehlcke }; 120*594d57d0SMatthias Kaehlcke 121*594d57d0SMatthias Kaehlcke /** 122*594d57d0SMatthias Kaehlcke * Receive status queue 123*594d57d0SMatthias Kaehlcke */ 124*594d57d0SMatthias Kaehlcke struct rx_status_queue { 125*594d57d0SMatthias Kaehlcke struct rx_status *base; 126*594d57d0SMatthias Kaehlcke volatile struct rx_status *current; 127*594d57d0SMatthias Kaehlcke struct rx_status *end; 128*594d57d0SMatthias Kaehlcke }; 129*594d57d0SMatthias Kaehlcke 130*594d57d0SMatthias Kaehlcke /** 131*594d57d0SMatthias Kaehlcke * EP93xx MAC private data structure 132*594d57d0SMatthias Kaehlcke */ 133*594d57d0SMatthias Kaehlcke struct ep93xx_priv { 134*594d57d0SMatthias Kaehlcke struct rx_descriptor_queue rx_dq; 135*594d57d0SMatthias Kaehlcke struct rx_status_queue rx_sq; 136*594d57d0SMatthias Kaehlcke void *rx_buffer[NUMRXDESC]; 137*594d57d0SMatthias Kaehlcke 138*594d57d0SMatthias Kaehlcke struct tx_descriptor_queue tx_dq; 139*594d57d0SMatthias Kaehlcke struct tx_status_queue tx_sq; 140*594d57d0SMatthias Kaehlcke 141*594d57d0SMatthias Kaehlcke struct mac_regs *regs; 142*594d57d0SMatthias Kaehlcke }; 143*594d57d0SMatthias Kaehlcke 144*594d57d0SMatthias Kaehlcke #endif 145