1 /* 2 * This program is free software; you can redistribute it and/or 3 * modify it under the terms of the GNU General Public License as 4 * published by the Free Software Foundation; either version 2 of 5 * the License, or (at your option) any later version. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 * 12 * You should have received a copy of the GNU General Public License 13 * along with this program; if not, write to the Free Software 14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 15 * MA 02111-1307 USA 16 */ 17 18 #include <config.h> 19 #include <common.h> 20 #ifdef CONFIG_ENC28J60 21 #include <net.h> 22 #include <asm/arch/hardware.h> 23 #include <asm/arch/spi.h> 24 25 /* 26 * Control Registers in Bank 0 27 */ 28 29 #define CTL_REG_ERDPTL 0x00 30 #define CTL_REG_ERDPTH 0x01 31 #define CTL_REG_EWRPTL 0x02 32 #define CTL_REG_EWRPTH 0x03 33 #define CTL_REG_ETXSTL 0x04 34 #define CTL_REG_ETXSTH 0x05 35 #define CTL_REG_ETXNDL 0x06 36 #define CTL_REG_ETXNDH 0x07 37 #define CTL_REG_ERXSTL 0x08 38 #define CTL_REG_ERXSTH 0x09 39 #define CTL_REG_ERXNDL 0x0A 40 #define CTL_REG_ERXNDH 0x0B 41 #define CTL_REG_ERXRDPTL 0x0C 42 #define CTL_REG_ERXRDPTH 0x0D 43 #define CTL_REG_ERXWRPTL 0x0E 44 #define CTL_REG_ERXWRPTH 0x0F 45 #define CTL_REG_EDMASTL 0x10 46 #define CTL_REG_EDMASTH 0x11 47 #define CTL_REG_EDMANDL 0x12 48 #define CTL_REG_EDMANDH 0x13 49 #define CTL_REG_EDMADSTL 0x14 50 #define CTL_REG_EDMADSTH 0x15 51 #define CTL_REG_EDMACSL 0x16 52 #define CTL_REG_EDMACSH 0x17 53 /* these are common in all banks */ 54 #define CTL_REG_EIE 0x1B 55 #define CTL_REG_EIR 0x1C 56 #define CTL_REG_ESTAT 0x1D 57 #define CTL_REG_ECON2 0x1E 58 #define CTL_REG_ECON1 0x1F 59 60 /* 61 * Control Registers in Bank 1 62 */ 63 64 #define CTL_REG_EHT0 0x00 65 #define CTL_REG_EHT1 0x01 66 #define CTL_REG_EHT2 0x02 67 #define CTL_REG_EHT3 0x03 68 #define CTL_REG_EHT4 0x04 69 #define CTL_REG_EHT5 0x05 70 #define CTL_REG_EHT6 0x06 71 #define CTL_REG_EHT7 0x07 72 #define CTL_REG_EPMM0 0x08 73 #define CTL_REG_EPMM1 0x09 74 #define CTL_REG_EPMM2 0x0A 75 #define CTL_REG_EPMM3 0x0B 76 #define CTL_REG_EPMM4 0x0C 77 #define CTL_REG_EPMM5 0x0D 78 #define CTL_REG_EPMM6 0x0E 79 #define CTL_REG_EPMM7 0x0F 80 #define CTL_REG_EPMCSL 0x10 81 #define CTL_REG_EPMCSH 0x11 82 #define CTL_REG_EPMOL 0x14 83 #define CTL_REG_EPMOH 0x15 84 #define CTL_REG_EWOLIE 0x16 85 #define CTL_REG_EWOLIR 0x17 86 #define CTL_REG_ERXFCON 0x18 87 #define CTL_REG_EPKTCNT 0x19 88 89 /* 90 * Control Registers in Bank 2 91 */ 92 93 #define CTL_REG_MACON1 0x00 94 #define CTL_REG_MACON2 0x01 95 #define CTL_REG_MACON3 0x02 96 #define CTL_REG_MACON4 0x03 97 #define CTL_REG_MABBIPG 0x04 98 #define CTL_REG_MAIPGL 0x06 99 #define CTL_REG_MAIPGH 0x07 100 #define CTL_REG_MACLCON1 0x08 101 #define CTL_REG_MACLCON2 0x09 102 #define CTL_REG_MAMXFLL 0x0A 103 #define CTL_REG_MAMXFLH 0x0B 104 #define CTL_REG_MAPHSUP 0x0D 105 #define CTL_REG_MICON 0x11 106 #define CTL_REG_MICMD 0x12 107 #define CTL_REG_MIREGADR 0x14 108 #define CTL_REG_MIWRL 0x16 109 #define CTL_REG_MIWRH 0x17 110 #define CTL_REG_MIRDL 0x18 111 #define CTL_REG_MIRDH 0x19 112 113 /* 114 * Control Registers in Bank 3 115 */ 116 117 #define CTL_REG_MAADR1 0x00 118 #define CTL_REG_MAADR0 0x01 119 #define CTL_REG_MAADR3 0x02 120 #define CTL_REG_MAADR2 0x03 121 #define CTL_REG_MAADR5 0x04 122 #define CTL_REG_MAADR4 0x05 123 #define CTL_REG_EBSTSD 0x06 124 #define CTL_REG_EBSTCON 0x07 125 #define CTL_REG_EBSTCSL 0x08 126 #define CTL_REG_EBSTCSH 0x09 127 #define CTL_REG_MISTAT 0x0A 128 #define CTL_REG_EREVID 0x12 129 #define CTL_REG_ECOCON 0x15 130 #define CTL_REG_EFLOCON 0x17 131 #define CTL_REG_EPAUSL 0x18 132 #define CTL_REG_EPAUSH 0x19 133 134 135 /* 136 * PHY Register 137 */ 138 139 #define PHY_REG_PHID1 0x02 140 #define PHY_REG_PHID2 0x03 141 /* taken from the Linux driver */ 142 #define PHY_REG_PHCON1 0x00 143 #define PHY_REG_PHCON2 0x10 144 #define PHY_REG_PHLCON 0x14 145 146 /* 147 * Receive Filter Register (ERXFCON) bits 148 */ 149 150 #define ENC_RFR_UCEN 0x80 151 #define ENC_RFR_ANDOR 0x40 152 #define ENC_RFR_CRCEN 0x20 153 #define ENC_RFR_PMEN 0x10 154 #define ENC_RFR_MPEN 0x08 155 #define ENC_RFR_HTEN 0x04 156 #define ENC_RFR_MCEN 0x02 157 #define ENC_RFR_BCEN 0x01 158 159 /* 160 * ECON1 Register Bits 161 */ 162 163 #define ENC_ECON1_TXRST 0x80 164 #define ENC_ECON1_RXRST 0x40 165 #define ENC_ECON1_DMAST 0x20 166 #define ENC_ECON1_CSUMEN 0x10 167 #define ENC_ECON1_TXRTS 0x08 168 #define ENC_ECON1_RXEN 0x04 169 #define ENC_ECON1_BSEL1 0x02 170 #define ENC_ECON1_BSEL0 0x01 171 172 /* 173 * ECON2 Register Bits 174 */ 175 #define ENC_ECON2_AUTOINC 0x80 176 #define ENC_ECON2_PKTDEC 0x40 177 #define ENC_ECON2_PWRSV 0x20 178 #define ENC_ECON2_VRPS 0x08 179 180 /* 181 * EIR Register Bits 182 */ 183 #define ENC_EIR_PKTIF 0x40 184 #define ENC_EIR_DMAIF 0x20 185 #define ENC_EIR_LINKIF 0x10 186 #define ENC_EIR_TXIF 0x08 187 #define ENC_EIR_WOLIF 0x04 188 #define ENC_EIR_TXERIF 0x02 189 #define ENC_EIR_RXERIF 0x01 190 191 /* 192 * ESTAT Register Bits 193 */ 194 195 #define ENC_ESTAT_INT 0x80 196 #define ENC_ESTAT_LATECOL 0x10 197 #define ENC_ESTAT_RXBUSY 0x04 198 #define ENC_ESTAT_TXABRT 0x02 199 #define ENC_ESTAT_CLKRDY 0x01 200 201 /* 202 * EIE Register Bits 203 */ 204 205 #define ENC_EIE_INTIE 0x80 206 #define ENC_EIE_PKTIE 0x40 207 #define ENC_EIE_DMAIE 0x20 208 #define ENC_EIE_LINKIE 0x10 209 #define ENC_EIE_TXIE 0x08 210 #define ENC_EIE_WOLIE 0x04 211 #define ENC_EIE_TXERIE 0x02 212 #define ENC_EIE_RXERIE 0x01 213 214 /* 215 * MACON1 Register Bits 216 */ 217 #define ENC_MACON1_LOOPBK 0x10 218 #define ENC_MACON1_TXPAUS 0x08 219 #define ENC_MACON1_RXPAUS 0x04 220 #define ENC_MACON1_PASSALL 0x02 221 #define ENC_MACON1_MARXEN 0x01 222 223 224 /* 225 * MACON2 Register Bits 226 */ 227 #define ENC_MACON2_MARST 0x80 228 #define ENC_MACON2_RNDRST 0x40 229 #define ENC_MACON2_MARXRST 0x08 230 #define ENC_MACON2_RFUNRST 0x04 231 #define ENC_MACON2_MATXRST 0x02 232 #define ENC_MACON2_TFUNRST 0x01 233 234 /* 235 * MACON3 Register Bits 236 */ 237 #define ENC_MACON3_PADCFG2 0x80 238 #define ENC_MACON3_PADCFG1 0x40 239 #define ENC_MACON3_PADCFG0 0x20 240 #define ENC_MACON3_TXCRCEN 0x10 241 #define ENC_MACON3_PHDRLEN 0x08 242 #define ENC_MACON3_HFRMEN 0x04 243 #define ENC_MACON3_FRMLNEN 0x02 244 #define ENC_MACON3_FULDPX 0x01 245 246 /* 247 * MICMD Register Bits 248 */ 249 #define ENC_MICMD_MIISCAN 0x02 250 #define ENC_MICMD_MIIRD 0x01 251 252 /* 253 * MISTAT Register Bits 254 */ 255 #define ENC_MISTAT_NVALID 0x04 256 #define ENC_MISTAT_SCAN 0x02 257 #define ENC_MISTAT_BUSY 0x01 258 259 /* 260 * PHID1 and PHID2 values 261 */ 262 #define ENC_PHID1_VALUE 0x0083 263 #define ENC_PHID2_VALUE 0x1400 264 #define ENC_PHID2_MASK 0xFC00 265 266 267 #define ENC_SPI_SLAVE_CS 0x00010000 /* pin P1.16 */ 268 #define ENC_RESET 0x00020000 /* pin P1.17 */ 269 270 #define FAILSAFE_VALUE 5000 271 272 /* 273 * Controller memory layout: 274 * 275 * 0x0000 - 0x17ff 6k bytes receive buffer 276 * 0x1800 - 0x1fff 2k bytes transmit buffer 277 */ 278 /* Use the lower memory for receiver buffer. See errata pt. 5 */ 279 #define ENC_RX_BUF_START 0x0000 280 #define ENC_TX_BUF_START 0x1800 281 /* taken from the Linux driver */ 282 #define ENC_RX_BUF_END 0x17ff 283 #define ENC_TX_BUF_END 0x1fff 284 285 /* maximum frame length */ 286 #define ENC_MAX_FRM_LEN 1518 287 288 #define enc_enable() PUT32(IO1CLR, ENC_SPI_SLAVE_CS) 289 #define enc_disable() PUT32(IO1SET, ENC_SPI_SLAVE_CS) 290 #define enc_cfg_spi() spi_set_cfg(0, 0, 0); spi_set_clock(8); 291 292 293 static unsigned char encReadReg (unsigned char regNo); 294 static void encWriteReg (unsigned char regNo, unsigned char data); 295 static void encWriteRegRetry (unsigned char regNo, unsigned char data, int c); 296 static void encReadBuff (unsigned short length, unsigned char *pBuff); 297 static void encWriteBuff (unsigned short length, unsigned char *pBuff); 298 static void encBitSet (unsigned char regNo, unsigned char data); 299 static void encBitClr (unsigned char regNo, unsigned char data); 300 static void encReset (void); 301 static void encInit (unsigned char *pEthAddr); 302 static unsigned short phyRead (unsigned char addr); 303 static void phyWrite(unsigned char, unsigned short); 304 static void encPoll (void); 305 static void encRx (void); 306 307 #define m_nic_read(reg) encReadReg(reg) 308 #define m_nic_write(reg, data) encWriteReg(reg, data) 309 #define m_nic_write_retry(reg, data, count) encWriteRegRetry(reg, data, count) 310 #define m_nic_read_data(len, buf) encReadBuff((len), (buf)) 311 #define m_nic_write_data(len, buf) encWriteBuff((len), (buf)) 312 313 /* bit field set */ 314 #define m_nic_bfs(reg, data) encBitSet(reg, data) 315 316 /* bit field clear */ 317 #define m_nic_bfc(reg, data) encBitClr(reg, data) 318 319 static unsigned char bank = 0; /* current bank in enc28j60 */ 320 static unsigned char next_pointer_lsb; 321 static unsigned char next_pointer_msb; 322 323 static unsigned char buffer[ENC_MAX_FRM_LEN]; 324 static int rxResetCounter = 0; 325 326 #define RX_RESET_COUNTER 1000; 327 328 /*----------------------------------------------------------------------------- 329 * Always returns 0 330 */ 331 int eth_init (bd_t * bis) 332 { 333 unsigned char estatVal; 334 335 /* configure GPIO */ 336 (*((volatile unsigned long *) IO1DIR)) |= ENC_SPI_SLAVE_CS; 337 (*((volatile unsigned long *) IO1DIR)) |= ENC_RESET; 338 339 /* CS and RESET active low */ 340 PUT32 (IO1SET, ENC_SPI_SLAVE_CS); 341 PUT32 (IO1SET, ENC_RESET); 342 343 spi_init (); 344 345 /* taken from the Linux driver - dangerous stuff here! */ 346 /* Wait for CLKRDY to become set (i.e., check that we can communicate with 347 the ENC) */ 348 do 349 { 350 estatVal = m_nic_read(CTL_REG_ESTAT); 351 } while ((estatVal & 0x08) || (~estatVal & ENC_ESTAT_CLKRDY)); 352 353 /* initialize controller */ 354 encReset (); 355 encInit (bis->bi_enetaddr); 356 357 m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXEN); /* enable receive */ 358 359 return 0; 360 } 361 362 int eth_send (volatile void *packet, int length) 363 { 364 /* check frame length, etc. */ 365 /* TODO: */ 366 367 /* switch to bank 0 */ 368 m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0)); 369 370 /* set EWRPT */ 371 m_nic_write (CTL_REG_EWRPTL, (ENC_TX_BUF_START & 0xff)); 372 m_nic_write (CTL_REG_EWRPTH, (ENC_TX_BUF_START >> 8)); 373 374 /* set ETXND */ 375 m_nic_write (CTL_REG_ETXNDL, (length + ENC_TX_BUF_START) & 0xFF); 376 m_nic_write (CTL_REG_ETXNDH, (length + ENC_TX_BUF_START) >> 8); 377 378 /* set ETXST */ 379 m_nic_write (CTL_REG_ETXSTL, ENC_TX_BUF_START & 0xFF); 380 m_nic_write (CTL_REG_ETXSTH, ENC_TX_BUF_START >> 8); 381 382 /* write packet */ 383 m_nic_write_data (length, (unsigned char *) packet); 384 385 /* taken from the Linux driver */ 386 /* Verify that the internal transmit logic has not been altered by excessive 387 collisions. See Errata B4 12 and 14. 388 */ 389 if (m_nic_read(CTL_REG_EIR) & ENC_EIR_TXERIF) { 390 m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_TXRST); 391 m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_TXRST); 392 } 393 m_nic_bfc(CTL_REG_EIR, (ENC_EIR_TXERIF | ENC_EIR_TXIF)); 394 395 /* set ECON1.TXRTS */ 396 m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_TXRTS); 397 398 return 0; 399 } 400 401 402 /***************************************************************************** 403 * This function resets the receiver only. This function may be called from 404 * interrupt-context. 405 */ 406 static void encReceiverReset (void) 407 { 408 unsigned char econ1; 409 410 econ1 = m_nic_read (CTL_REG_ECON1); 411 if ((econ1 & ENC_ECON1_RXRST) == 0) { 412 m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXRST); 413 rxResetCounter = RX_RESET_COUNTER; 414 } 415 } 416 417 /***************************************************************************** 418 * receiver reset timer 419 */ 420 static void encReceiverResetCallback (void) 421 { 422 m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_RXRST); 423 m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXEN); /* enable receive */ 424 } 425 426 /*----------------------------------------------------------------------------- 427 * Check for received packets. Call NetReceive for each packet. The return 428 * value is ignored by the caller. 429 */ 430 int eth_rx (void) 431 { 432 if (rxResetCounter > 0 && --rxResetCounter == 0) { 433 encReceiverResetCallback (); 434 } 435 436 encPoll (); 437 438 return 0; 439 } 440 441 void eth_halt (void) 442 { 443 m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_RXEN); /* disable receive */ 444 } 445 446 /*****************************************************************************/ 447 448 static void encPoll (void) 449 { 450 unsigned char eir_reg; 451 volatile unsigned char estat_reg; 452 unsigned char pkt_cnt; 453 454 #ifdef CONFIG_USE_IRQ 455 /* clear global interrupt enable bit in enc28j60 */ 456 m_nic_bfc (CTL_REG_EIE, ENC_EIE_INTIE); 457 #endif 458 estat_reg = m_nic_read (CTL_REG_ESTAT); 459 460 eir_reg = m_nic_read (CTL_REG_EIR); 461 462 if (eir_reg & ENC_EIR_TXIF) { 463 /* clear TXIF bit in EIR */ 464 m_nic_bfc (CTL_REG_EIR, ENC_EIR_TXIF); 465 } 466 467 /* We have to use pktcnt and not pktif bit, see errata pt. 6 */ 468 469 /* move to bank 1 */ 470 m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1); 471 m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0); 472 473 /* read pktcnt */ 474 pkt_cnt = m_nic_read (CTL_REG_EPKTCNT); 475 476 if (pkt_cnt > 0) { 477 if ((eir_reg & ENC_EIR_PKTIF) == 0) { 478 /*printf("encPoll: pkt cnt > 0, but pktif not set\n"); */ 479 } 480 encRx (); 481 /* clear PKTIF bit in EIR, this should not need to be done but it 482 seems like we get problems if we do not */ 483 m_nic_bfc (CTL_REG_EIR, ENC_EIR_PKTIF); 484 } 485 486 if (eir_reg & ENC_EIR_RXERIF) { 487 printf ("encPoll: rx error\n"); 488 m_nic_bfc (CTL_REG_EIR, ENC_EIR_RXERIF); 489 } 490 if (eir_reg & ENC_EIR_TXERIF) { 491 printf ("encPoll: tx error\n"); 492 m_nic_bfc (CTL_REG_EIR, ENC_EIR_TXERIF); 493 } 494 495 #ifdef CONFIG_USE_IRQ 496 /* set global interrupt enable bit in enc28j60 */ 497 m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE); 498 #endif 499 } 500 501 static void encRx (void) 502 { 503 unsigned short pkt_len; 504 unsigned short copy_len; 505 unsigned short status; 506 unsigned char eir_reg; 507 unsigned char pkt_cnt = 0; 508 unsigned short rxbuf_rdpt; 509 510 /* switch to bank 0 */ 511 m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0)); 512 513 m_nic_write (CTL_REG_ERDPTL, next_pointer_lsb); 514 m_nic_write (CTL_REG_ERDPTH, next_pointer_msb); 515 516 do { 517 m_nic_read_data (6, buffer); 518 next_pointer_lsb = buffer[0]; 519 next_pointer_msb = buffer[1]; 520 pkt_len = buffer[2]; 521 pkt_len |= (unsigned short) buffer[3] << 8; 522 status = buffer[4]; 523 status |= (unsigned short) buffer[5] << 8; 524 525 if (pkt_len <= ENC_MAX_FRM_LEN) 526 copy_len = pkt_len; 527 else 528 copy_len = 0; 529 530 if ((status & (1L << 7)) == 0) /* check Received Ok bit */ 531 copy_len = 0; 532 533 /* taken from the Linux driver */ 534 /* check if next pointer is resonable */ 535 if ((((unsigned int)next_pointer_msb << 8) | 536 (unsigned int)next_pointer_lsb) >= ENC_TX_BUF_START) 537 copy_len = 0; 538 539 if (copy_len > 0) { 540 m_nic_read_data (copy_len, buffer); 541 } 542 543 /* advance read pointer to next pointer */ 544 m_nic_write (CTL_REG_ERDPTL, next_pointer_lsb); 545 m_nic_write (CTL_REG_ERDPTH, next_pointer_msb); 546 547 /* decrease packet counter */ 548 m_nic_bfs (CTL_REG_ECON2, ENC_ECON2_PKTDEC); 549 550 /* taken from the Linux driver */ 551 /* Only odd values should be written to ERXRDPTL, 552 * see errata B4 pt.13 553 */ 554 rxbuf_rdpt = (next_pointer_msb << 8 | next_pointer_lsb) - 1; 555 if ((rxbuf_rdpt < (m_nic_read(CTL_REG_ERXSTH) << 8 | 556 m_nic_read(CTL_REG_ERXSTL))) || (rxbuf_rdpt > 557 (m_nic_read(CTL_REG_ERXNDH) << 8 | 558 m_nic_read(CTL_REG_ERXNDL)))) { 559 m_nic_write(CTL_REG_ERXRDPTL, m_nic_read(CTL_REG_ERXNDL)); 560 m_nic_write(CTL_REG_ERXRDPTH, m_nic_read(CTL_REG_ERXNDH)); 561 } else { 562 m_nic_write(CTL_REG_ERXRDPTL, rxbuf_rdpt & 0xFF); 563 m_nic_write(CTL_REG_ERXRDPTH, rxbuf_rdpt >> 8); 564 } 565 566 /* move to bank 1 */ 567 m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1); 568 m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0); 569 570 /* read pktcnt */ 571 pkt_cnt = m_nic_read (CTL_REG_EPKTCNT); 572 573 /* switch to bank 0 */ 574 m_nic_bfc (CTL_REG_ECON1, 575 (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0)); 576 577 if (copy_len == 0) { 578 eir_reg = m_nic_read (CTL_REG_EIR); 579 encReceiverReset (); 580 printf ("eth_rx: copy_len=0\n"); 581 continue; 582 } 583 584 NetReceive ((unsigned char *) buffer, pkt_len); 585 586 eir_reg = m_nic_read (CTL_REG_EIR); 587 } while (pkt_cnt); /* Use EPKTCNT not EIR.PKTIF flag, see errata pt. 6 */ 588 } 589 590 static void encWriteReg (unsigned char regNo, unsigned char data) 591 { 592 spi_lock (); 593 enc_cfg_spi (); 594 enc_enable (); 595 596 spi_write (0x40 | regNo); /* write in regNo */ 597 spi_write (data); 598 599 enc_disable (); 600 enc_enable (); 601 602 spi_write (0x1f); /* write reg 0x1f */ 603 604 enc_disable (); 605 spi_unlock (); 606 } 607 608 static void encWriteRegRetry (unsigned char regNo, unsigned char data, int c) 609 { 610 unsigned char readback; 611 int i; 612 613 spi_lock (); 614 615 for (i = 0; i < c; i++) { 616 enc_cfg_spi (); 617 enc_enable (); 618 619 spi_write (0x40 | regNo); /* write in regNo */ 620 spi_write (data); 621 622 enc_disable (); 623 enc_enable (); 624 625 spi_write (0x1f); /* write reg 0x1f */ 626 627 enc_disable (); 628 629 spi_unlock (); /* we must unlock spi first */ 630 631 readback = encReadReg (regNo); 632 633 spi_lock (); 634 635 if (readback == data) 636 break; 637 } 638 spi_unlock (); 639 640 if (i == c) { 641 printf ("enc28j60: write reg %d failed\n", regNo); 642 } 643 } 644 645 static unsigned char encReadReg (unsigned char regNo) 646 { 647 unsigned char rxByte; 648 649 spi_lock (); 650 enc_cfg_spi (); 651 enc_enable (); 652 653 spi_write (0x1f); /* read reg 0x1f */ 654 655 bank = spi_read () & 0x3; 656 657 enc_disable (); 658 enc_enable (); 659 660 spi_write (regNo); 661 rxByte = spi_read (); 662 663 /* check if MAC or MII register */ 664 if (((bank == 2) && (regNo <= 0x1a)) || 665 ((bank == 3) && (regNo <= 0x05 || regNo == 0x0a))) { 666 /* ignore first byte and read another byte */ 667 rxByte = spi_read (); 668 } 669 670 enc_disable (); 671 spi_unlock (); 672 673 return rxByte; 674 } 675 676 static void encReadBuff (unsigned short length, unsigned char *pBuff) 677 { 678 spi_lock (); 679 enc_cfg_spi (); 680 enc_enable (); 681 682 spi_write (0x20 | 0x1a); /* read buffer memory */ 683 684 while (length--) { 685 if (pBuff != NULL) 686 *pBuff++ = spi_read (); 687 else 688 spi_write (0); 689 } 690 691 enc_disable (); 692 spi_unlock (); 693 } 694 695 static void encWriteBuff (unsigned short length, unsigned char *pBuff) 696 { 697 spi_lock (); 698 enc_cfg_spi (); 699 enc_enable (); 700 701 spi_write (0x60 | 0x1a); /* write buffer memory */ 702 703 spi_write (0x00); /* control byte */ 704 705 while (length--) 706 spi_write (*pBuff++); 707 708 enc_disable (); 709 spi_unlock (); 710 } 711 712 static void encBitSet (unsigned char regNo, unsigned char data) 713 { 714 spi_lock (); 715 enc_cfg_spi (); 716 enc_enable (); 717 718 spi_write (0x80 | regNo); /* bit field set */ 719 spi_write (data); 720 721 enc_disable (); 722 spi_unlock (); 723 } 724 725 static void encBitClr (unsigned char regNo, unsigned char data) 726 { 727 spi_lock (); 728 enc_cfg_spi (); 729 enc_enable (); 730 731 spi_write (0xA0 | regNo); /* bit field clear */ 732 spi_write (data); 733 734 enc_disable (); 735 spi_unlock (); 736 } 737 738 static void encReset (void) 739 { 740 spi_lock (); 741 enc_cfg_spi (); 742 enc_enable (); 743 744 spi_write (0xff); /* soft reset */ 745 746 enc_disable (); 747 spi_unlock (); 748 749 /* sleep 1 ms. See errata pt. 2 */ 750 udelay (1000); 751 } 752 753 static void encInit (unsigned char *pEthAddr) 754 { 755 unsigned short phid1 = 0; 756 unsigned short phid2 = 0; 757 758 /* switch to bank 0 */ 759 m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0)); 760 761 /* 762 * Setup the buffer space. The reset values are valid for the 763 * other pointers. 764 */ 765 /* We shall not write to ERXST, see errata pt. 5. Instead we 766 have to make sure that ENC_RX_BUS_START is 0. */ 767 m_nic_write_retry (CTL_REG_ERXSTL, (ENC_RX_BUF_START & 0xFF), 1); 768 m_nic_write_retry (CTL_REG_ERXSTH, (ENC_RX_BUF_START >> 8), 1); 769 770 /* taken from the Linux driver */ 771 m_nic_write_retry (CTL_REG_ERXNDL, (ENC_RX_BUF_END & 0xFF), 1); 772 m_nic_write_retry (CTL_REG_ERXNDH, (ENC_RX_BUF_END >> 8), 1); 773 774 m_nic_write_retry (CTL_REG_ERDPTL, (ENC_RX_BUF_START & 0xFF), 1); 775 m_nic_write_retry (CTL_REG_ERDPTH, (ENC_RX_BUF_START >> 8), 1); 776 777 next_pointer_lsb = (ENC_RX_BUF_START & 0xFF); 778 next_pointer_msb = (ENC_RX_BUF_START >> 8); 779 780 /* verify identification */ 781 phid1 = phyRead (PHY_REG_PHID1); 782 phid2 = phyRead (PHY_REG_PHID2); 783 784 if (phid1 != ENC_PHID1_VALUE 785 || (phid2 & ENC_PHID2_MASK) != ENC_PHID2_VALUE) { 786 printf ("ERROR: failed to identify controller\n"); 787 printf ("phid1 = %x, phid2 = %x\n", 788 phid1, (phid2 & ENC_PHID2_MASK)); 789 printf ("should be phid1 = %x, phid2 = %x\n", 790 ENC_PHID1_VALUE, ENC_PHID2_VALUE); 791 } 792 793 /* 794 * --- MAC Initialization --- 795 */ 796 797 /* Pull MAC out of Reset */ 798 799 /* switch to bank 2 */ 800 m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL0); 801 m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL1); 802 803 /* enable MAC to receive frames */ 804 /* added some bits from the Linux driver */ 805 m_nic_write_retry (CTL_REG_MACON1 806 ,(ENC_MACON1_MARXEN | ENC_MACON1_TXPAUS | ENC_MACON1_RXPAUS) 807 ,10); 808 809 /* configure pad, tx-crc and duplex */ 810 /* added a bit from the Linux driver */ 811 m_nic_write_retry (CTL_REG_MACON3 812 ,(ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN | ENC_MACON3_FRMLNEN) 813 ,10); 814 815 /* added 4 new lines from the Linux driver */ 816 /* Allow infinite deferals if the medium is continously busy */ 817 m_nic_write_retry(CTL_REG_MACON4, (1<<6) /*ENC_MACON4_DEFER*/, 10); 818 819 /* Late collisions occur beyond 63 bytes */ 820 m_nic_write_retry(CTL_REG_MACLCON2, 63, 10); 821 822 /* Set (low byte) Non-Back-to_Back Inter-Packet Gap. Recommended 0x12 */ 823 m_nic_write_retry(CTL_REG_MAIPGL, 0x12, 10); 824 825 /* 826 * Set (high byte) Non-Back-to_Back Inter-Packet Gap. Recommended 827 * 0x0c for half-duplex. Nothing for full-duplex 828 */ 829 m_nic_write_retry(CTL_REG_MAIPGH, 0x0C, 10); 830 831 /* set maximum frame length */ 832 m_nic_write_retry (CTL_REG_MAMXFLL, (ENC_MAX_FRM_LEN & 0xff), 10); 833 m_nic_write_retry (CTL_REG_MAMXFLH, (ENC_MAX_FRM_LEN >> 8), 10); 834 835 /* 836 * Set MAC back-to-back inter-packet gap. Recommended 0x12 for half duplex 837 * and 0x15 for full duplex. 838 */ 839 m_nic_write_retry (CTL_REG_MABBIPG, 0x12, 10); 840 841 /* set MAC address */ 842 843 /* switch to bank 3 */ 844 m_nic_bfs (CTL_REG_ECON1, (ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1)); 845 846 m_nic_write_retry (CTL_REG_MAADR0, pEthAddr[5], 1); 847 m_nic_write_retry (CTL_REG_MAADR1, pEthAddr[4], 1); 848 m_nic_write_retry (CTL_REG_MAADR2, pEthAddr[3], 1); 849 m_nic_write_retry (CTL_REG_MAADR3, pEthAddr[2], 1); 850 m_nic_write_retry (CTL_REG_MAADR4, pEthAddr[1], 1); 851 m_nic_write_retry (CTL_REG_MAADR5, pEthAddr[0], 1); 852 853 /* 854 * PHY Initialization taken from the Linux driver 855 */ 856 857 /* Prevent automatic loopback of data beeing transmitted by setting 858 ENC_PHCON2_HDLDIS */ 859 phyWrite(PHY_REG_PHCON2, (1<<8)); 860 861 /* LEDs configuration 862 * LEDA: LACFG = 0100 -> display link status 863 * LEDB: LBCFG = 0111 -> display TX & RX activity 864 * STRCH = 1 -> LED pulses 865 */ 866 phyWrite(PHY_REG_PHLCON, 0x0472); 867 868 /* Reset PDPXMD-bit => half duplex */ 869 phyWrite(PHY_REG_PHCON1, 0); 870 871 /* 872 * Receive settings 873 */ 874 875 #ifdef CONFIG_USE_IRQ 876 /* enable interrupts */ 877 m_nic_bfs (CTL_REG_EIE, ENC_EIE_PKTIE); 878 m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXIE); 879 m_nic_bfs (CTL_REG_EIE, ENC_EIE_RXERIE); 880 m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXERIE); 881 m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE); 882 #endif 883 } 884 885 /***************************************************************************** 886 * 887 * Description: 888 * Read PHY registers. 889 * 890 * NOTE! This function will change to Bank 2. 891 * 892 * Params: 893 * [in] addr address of the register to read 894 * 895 * Returns: 896 * The value in the register 897 */ 898 static unsigned short phyRead (unsigned char addr) 899 { 900 unsigned short ret = 0; 901 902 /* move to bank 2 */ 903 m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL0); 904 m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL1); 905 906 /* write address to MIREGADR */ 907 m_nic_write (CTL_REG_MIREGADR, addr); 908 909 /* set MICMD.MIIRD */ 910 m_nic_write (CTL_REG_MICMD, ENC_MICMD_MIIRD); 911 912 /* taken from the Linux driver */ 913 /* move to bank 3 */ 914 m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL0); 915 m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1); 916 917 /* poll MISTAT.BUSY bit until operation is complete */ 918 while ((m_nic_read (CTL_REG_MISTAT) & ENC_MISTAT_BUSY) != 0) { 919 static int cnt = 0; 920 921 if (cnt++ >= 1000) { 922 /* GJ - this seems extremely dangerous! */ 923 /* printf("#"); */ 924 cnt = 0; 925 } 926 } 927 928 /* taken from the Linux driver */ 929 /* move to bank 2 */ 930 m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_BSEL0); 931 m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1); 932 933 /* clear MICMD.MIIRD */ 934 m_nic_write (CTL_REG_MICMD, 0); 935 936 ret = (m_nic_read (CTL_REG_MIRDH) << 8); 937 ret |= (m_nic_read (CTL_REG_MIRDL) & 0xFF); 938 939 return ret; 940 } 941 942 /***************************************************************************** 943 * 944 * Taken from the Linux driver. 945 * Description: 946 * Write PHY registers. 947 * 948 * NOTE! This function will change to Bank 3. 949 * 950 * Params: 951 * [in] addr address of the register to write to 952 * [in] data to be written 953 * 954 * Returns: 955 * None 956 */ 957 static void phyWrite(unsigned char addr, unsigned short data) 958 { 959 /* move to bank 2 */ 960 m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_BSEL0); 961 m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1); 962 963 /* write address to MIREGADR */ 964 m_nic_write(CTL_REG_MIREGADR, addr); 965 966 m_nic_write(CTL_REG_MIWRL, data & 0xff); 967 m_nic_write(CTL_REG_MIWRH, data >> 8); 968 969 /* move to bank 3 */ 970 m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL0); 971 m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1); 972 973 /* poll MISTAT.BUSY bit until operation is complete */ 974 while((m_nic_read(CTL_REG_MISTAT) & ENC_MISTAT_BUSY) != 0) { 975 static int cnt = 0; 976 977 if(cnt++ >= 1000) { 978 cnt = 0; 979 } 980 } 981 } 982 983 #endif /* CONFIG_ENC28J60 */ 984