1 /* 2 * (C) Copyright 2010 3 * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de 4 * Martin Krause, Martin.Krause@tqs.de 5 * reworked original enc28j60.c 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <net.h> 12 #include <spi.h> 13 #include <malloc.h> 14 #include <netdev.h> 15 #include <miiphy.h> 16 #include "enc28j60.h" 17 18 /* 19 * IMPORTANT: spi_claim_bus() and spi_release_bus() 20 * are called at begin and end of each of the following functions: 21 * enc_miiphy_read(), enc_miiphy_write(), enc_write_hwaddr(), 22 * enc_init(), enc_recv(), enc_send(), enc_halt() 23 * ALL other functions assume that the bus has already been claimed! 24 * Since NetReceive() might call enc_send() in return, the bus must be 25 * released, NetReceive() called and claimed again. 26 */ 27 28 /* 29 * Controller memory layout. 30 * We only allow 1 frame for transmission and reserve the rest 31 * for reception to handle as many broadcast packets as possible. 32 * Also use the memory from 0x0000 for receiver buffer. See errata pt. 5 33 * 0x0000 - 0x19ff 6656 bytes receive buffer 34 * 0x1a00 - 0x1fff 1536 bytes transmit buffer = 35 * control(1)+frame(1518)+status(7)+reserve(10). 36 */ 37 #define ENC_RX_BUF_START 0x0000 38 #define ENC_RX_BUF_END 0x19ff 39 #define ENC_TX_BUF_START 0x1a00 40 #define ENC_TX_BUF_END 0x1fff 41 #define ENC_MAX_FRM_LEN 1518 42 #define RX_RESET_COUNTER 1000 43 44 /* 45 * For non data transfer functions, like phy read/write, set hwaddr, init 46 * we do not need a full, time consuming init including link ready wait. 47 * This enum helps to bring the chip through the minimum necessary inits. 48 */ 49 enum enc_initstate {none=0, setupdone, linkready}; 50 typedef struct enc_device { 51 struct eth_device *dev; /* back pointer */ 52 struct spi_slave *slave; 53 int rx_reset_counter; 54 u16 next_pointer; 55 u8 bank; /* current bank in enc28j60 */ 56 enum enc_initstate initstate; 57 } enc_dev_t; 58 59 /* 60 * enc_bset: set bits in a common register 61 * enc_bclr: clear bits in a common register 62 * 63 * making the reg parameter u8 will give a compile time warning if the 64 * functions are called with a register not accessible in all Banks 65 */ 66 static void enc_bset(enc_dev_t *enc, const u8 reg, const u8 data) 67 { 68 u8 dout[2]; 69 70 dout[0] = CMD_BFS(reg); 71 dout[1] = data; 72 spi_xfer(enc->slave, 2 * 8, dout, NULL, 73 SPI_XFER_BEGIN | SPI_XFER_END); 74 } 75 76 static void enc_bclr(enc_dev_t *enc, const u8 reg, const u8 data) 77 { 78 u8 dout[2]; 79 80 dout[0] = CMD_BFC(reg); 81 dout[1] = data; 82 spi_xfer(enc->slave, 2 * 8, dout, NULL, 83 SPI_XFER_BEGIN | SPI_XFER_END); 84 } 85 86 /* 87 * high byte of the register contains bank number: 88 * 0: no bank switch necessary 89 * 1: switch to bank 0 90 * 2: switch to bank 1 91 * 3: switch to bank 2 92 * 4: switch to bank 3 93 */ 94 static void enc_set_bank(enc_dev_t *enc, const u16 reg) 95 { 96 u8 newbank = reg >> 8; 97 98 if (newbank == 0 || newbank == enc->bank) 99 return; 100 switch (newbank) { 101 case 1: 102 enc_bclr(enc, CTL_REG_ECON1, 103 ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1); 104 break; 105 case 2: 106 enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_BSEL0); 107 enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_BSEL1); 108 break; 109 case 3: 110 enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_BSEL0); 111 enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_BSEL1); 112 break; 113 case 4: 114 enc_bset(enc, CTL_REG_ECON1, 115 ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1); 116 break; 117 } 118 enc->bank = newbank; 119 } 120 121 /* 122 * local functions to access SPI 123 * 124 * reg: register inside ENC28J60 125 * data: 8/16 bits to write 126 * c: number of retries 127 * 128 * enc_r8: read 8 bits 129 * enc_r16: read 16 bits 130 * enc_w8: write 8 bits 131 * enc_w16: write 16 bits 132 * enc_w8_retry: write 8 bits, verify and retry 133 * enc_rbuf: read from ENC28J60 into buffer 134 * enc_wbuf: write from buffer into ENC28J60 135 */ 136 137 /* 138 * MAC and MII registers need a 3 byte SPI transfer to read, 139 * all other registers need a 2 byte SPI transfer. 140 */ 141 static int enc_reg2nbytes(const u16 reg) 142 { 143 /* check if MAC or MII register */ 144 return ((reg >= CTL_REG_MACON1 && reg <= CTL_REG_MIRDH) || 145 (reg >= CTL_REG_MAADR1 && reg <= CTL_REG_MAADR4) || 146 (reg == CTL_REG_MISTAT)) ? 3 : 2; 147 } 148 149 /* 150 * Read a byte register 151 */ 152 static u8 enc_r8(enc_dev_t *enc, const u16 reg) 153 { 154 u8 dout[3]; 155 u8 din[3]; 156 int nbytes = enc_reg2nbytes(reg); 157 158 enc_set_bank(enc, reg); 159 dout[0] = CMD_RCR(reg); 160 spi_xfer(enc->slave, nbytes * 8, dout, din, 161 SPI_XFER_BEGIN | SPI_XFER_END); 162 return din[nbytes-1]; 163 } 164 165 /* 166 * Read a L/H register pair and return a word. 167 * Must be called with the L register's address. 168 */ 169 static u16 enc_r16(enc_dev_t *enc, const u16 reg) 170 { 171 u8 dout[3]; 172 u8 din[3]; 173 u16 result; 174 int nbytes = enc_reg2nbytes(reg); 175 176 enc_set_bank(enc, reg); 177 dout[0] = CMD_RCR(reg); 178 spi_xfer(enc->slave, nbytes * 8, dout, din, 179 SPI_XFER_BEGIN | SPI_XFER_END); 180 result = din[nbytes-1]; 181 dout[0]++; /* next register */ 182 spi_xfer(enc->slave, nbytes * 8, dout, din, 183 SPI_XFER_BEGIN | SPI_XFER_END); 184 result |= din[nbytes-1] << 8; 185 return result; 186 } 187 188 /* 189 * Write a byte register 190 */ 191 static void enc_w8(enc_dev_t *enc, const u16 reg, const u8 data) 192 { 193 u8 dout[2]; 194 195 enc_set_bank(enc, reg); 196 dout[0] = CMD_WCR(reg); 197 dout[1] = data; 198 spi_xfer(enc->slave, 2 * 8, dout, NULL, 199 SPI_XFER_BEGIN | SPI_XFER_END); 200 } 201 202 /* 203 * Write a L/H register pair. 204 * Must be called with the L register's address. 205 */ 206 static void enc_w16(enc_dev_t *enc, const u16 reg, const u16 data) 207 { 208 u8 dout[2]; 209 210 enc_set_bank(enc, reg); 211 dout[0] = CMD_WCR(reg); 212 dout[1] = data; 213 spi_xfer(enc->slave, 2 * 8, dout, NULL, 214 SPI_XFER_BEGIN | SPI_XFER_END); 215 dout[0]++; /* next register */ 216 dout[1] = data >> 8; 217 spi_xfer(enc->slave, 2 * 8, dout, NULL, 218 SPI_XFER_BEGIN | SPI_XFER_END); 219 } 220 221 /* 222 * Write a byte register, verify and retry 223 */ 224 static void enc_w8_retry(enc_dev_t *enc, const u16 reg, const u8 data, const int c) 225 { 226 u8 dout[2]; 227 u8 readback; 228 int i; 229 230 enc_set_bank(enc, reg); 231 for (i = 0; i < c; i++) { 232 dout[0] = CMD_WCR(reg); 233 dout[1] = data; 234 spi_xfer(enc->slave, 2 * 8, dout, NULL, 235 SPI_XFER_BEGIN | SPI_XFER_END); 236 readback = enc_r8(enc, reg); 237 if (readback == data) 238 break; 239 /* wait 1ms */ 240 udelay(1000); 241 } 242 if (i == c) { 243 printf("%s: write reg 0x%03x failed\n", enc->dev->name, reg); 244 } 245 } 246 247 /* 248 * Read ENC RAM into buffer 249 */ 250 static void enc_rbuf(enc_dev_t *enc, const u16 length, u8 *buf) 251 { 252 u8 dout[1]; 253 254 dout[0] = CMD_RBM; 255 spi_xfer(enc->slave, 8, dout, NULL, SPI_XFER_BEGIN); 256 spi_xfer(enc->slave, length * 8, NULL, buf, SPI_XFER_END); 257 #ifdef DEBUG 258 puts("Rx:\n"); 259 print_buffer(0, buf, 1, length, 0); 260 #endif 261 } 262 263 /* 264 * Write buffer into ENC RAM 265 */ 266 static void enc_wbuf(enc_dev_t *enc, const u16 length, const u8 *buf, const u8 control) 267 { 268 u8 dout[2]; 269 dout[0] = CMD_WBM; 270 dout[1] = control; 271 spi_xfer(enc->slave, 2 * 8, dout, NULL, SPI_XFER_BEGIN); 272 spi_xfer(enc->slave, length * 8, buf, NULL, SPI_XFER_END); 273 #ifdef DEBUG 274 puts("Tx:\n"); 275 print_buffer(0, buf, 1, length, 0); 276 #endif 277 } 278 279 /* 280 * Try to claim the SPI bus. 281 * Print error message on failure. 282 */ 283 static int enc_claim_bus(enc_dev_t *enc) 284 { 285 int rc = spi_claim_bus(enc->slave); 286 if (rc) 287 printf("%s: failed to claim SPI bus\n", enc->dev->name); 288 return rc; 289 } 290 291 /* 292 * Release previously claimed SPI bus. 293 * This function is mainly for symmetry to enc_claim_bus(). 294 * Let the toolchain decide to inline it... 295 */ 296 static void enc_release_bus(enc_dev_t *enc) 297 { 298 spi_release_bus(enc->slave); 299 } 300 301 /* 302 * Read PHY register 303 */ 304 static u16 enc_phy_read(enc_dev_t *enc, const u8 addr) 305 { 306 uint64_t etime; 307 u8 status; 308 309 enc_w8(enc, CTL_REG_MIREGADR, addr); 310 enc_w8(enc, CTL_REG_MICMD, ENC_MICMD_MIIRD); 311 /* 1 second timeout - only happens on hardware problem */ 312 etime = get_ticks() + get_tbclk(); 313 /* poll MISTAT.BUSY bit until operation is complete */ 314 do 315 { 316 status = enc_r8(enc, CTL_REG_MISTAT); 317 } while (get_ticks() <= etime && (status & ENC_MISTAT_BUSY)); 318 if (status & ENC_MISTAT_BUSY) { 319 printf("%s: timeout reading phy\n", enc->dev->name); 320 return 0; 321 } 322 enc_w8(enc, CTL_REG_MICMD, 0); 323 return enc_r16(enc, CTL_REG_MIRDL); 324 } 325 326 /* 327 * Write PHY register 328 */ 329 static void enc_phy_write(enc_dev_t *enc, const u8 addr, const u16 data) 330 { 331 uint64_t etime; 332 u8 status; 333 334 enc_w8(enc, CTL_REG_MIREGADR, addr); 335 enc_w16(enc, CTL_REG_MIWRL, data); 336 /* 1 second timeout - only happens on hardware problem */ 337 etime = get_ticks() + get_tbclk(); 338 /* poll MISTAT.BUSY bit until operation is complete */ 339 do 340 { 341 status = enc_r8(enc, CTL_REG_MISTAT); 342 } while (get_ticks() <= etime && (status & ENC_MISTAT_BUSY)); 343 if (status & ENC_MISTAT_BUSY) { 344 printf("%s: timeout writing phy\n", enc->dev->name); 345 return; 346 } 347 } 348 349 /* 350 * Verify link status, wait if necessary 351 * 352 * Note: with a 10 MBit/s only PHY there is no autonegotiation possible, 353 * half/full duplex is a pure setup matter. For the time being, this driver 354 * will setup in half duplex mode only. 355 */ 356 static int enc_phy_link_wait(enc_dev_t *enc) 357 { 358 u16 status; 359 int duplex; 360 uint64_t etime; 361 362 #ifdef CONFIG_ENC_SILENTLINK 363 /* check if we have a link, then just return */ 364 status = enc_phy_read(enc, PHY_REG_PHSTAT1); 365 if (status & ENC_PHSTAT1_LLSTAT) 366 return 0; 367 #endif 368 369 /* wait for link with 1 second timeout */ 370 etime = get_ticks() + get_tbclk(); 371 while (get_ticks() <= etime) { 372 status = enc_phy_read(enc, PHY_REG_PHSTAT1); 373 if (status & ENC_PHSTAT1_LLSTAT) { 374 /* now we have a link */ 375 status = enc_phy_read(enc, PHY_REG_PHSTAT2); 376 duplex = (status & ENC_PHSTAT2_DPXSTAT) ? 1 : 0; 377 printf("%s: link up, 10Mbps %s-duplex\n", 378 enc->dev->name, duplex ? "full" : "half"); 379 return 0; 380 } 381 udelay(1000); 382 } 383 384 /* timeout occured */ 385 printf("%s: link down\n", enc->dev->name); 386 return 1; 387 } 388 389 /* 390 * This function resets the receiver only. 391 */ 392 static void enc_reset_rx(enc_dev_t *enc) 393 { 394 u8 econ1; 395 396 econ1 = enc_r8(enc, CTL_REG_ECON1); 397 if ((econ1 & ENC_ECON1_RXRST) == 0) { 398 enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXRST); 399 enc->rx_reset_counter = RX_RESET_COUNTER; 400 } 401 } 402 403 /* 404 * Reset receiver and reenable it. 405 */ 406 static void enc_reset_rx_call(enc_dev_t *enc) 407 { 408 enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_RXRST); 409 enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXEN); 410 } 411 412 /* 413 * Copy a packet from the receive ring and forward it to 414 * the protocol stack. 415 */ 416 static void enc_receive(enc_dev_t *enc) 417 { 418 u8 *packet = (u8 *)NetRxPackets[0]; 419 u16 pkt_len; 420 u16 copy_len; 421 u16 status; 422 u8 pkt_cnt = 0; 423 u16 rxbuf_rdpt; 424 u8 hbuf[6]; 425 426 enc_w16(enc, CTL_REG_ERDPTL, enc->next_pointer); 427 do { 428 enc_rbuf(enc, 6, hbuf); 429 enc->next_pointer = hbuf[0] | (hbuf[1] << 8); 430 pkt_len = hbuf[2] | (hbuf[3] << 8); 431 status = hbuf[4] | (hbuf[5] << 8); 432 debug("next_pointer=$%04x pkt_len=%u status=$%04x\n", 433 enc->next_pointer, pkt_len, status); 434 if (pkt_len <= ENC_MAX_FRM_LEN) 435 copy_len = pkt_len; 436 else 437 copy_len = 0; 438 if ((status & (1L << 7)) == 0) /* check Received Ok bit */ 439 copy_len = 0; 440 /* check if next pointer is resonable */ 441 if (enc->next_pointer >= ENC_TX_BUF_START) 442 copy_len = 0; 443 if (copy_len > 0) { 444 enc_rbuf(enc, copy_len, packet); 445 } 446 /* advance read pointer to next pointer */ 447 enc_w16(enc, CTL_REG_ERDPTL, enc->next_pointer); 448 /* decrease packet counter */ 449 enc_bset(enc, CTL_REG_ECON2, ENC_ECON2_PKTDEC); 450 /* 451 * Only odd values should be written to ERXRDPTL, 452 * see errata B4 pt.13 453 */ 454 rxbuf_rdpt = enc->next_pointer - 1; 455 if ((rxbuf_rdpt < enc_r16(enc, CTL_REG_ERXSTL)) || 456 (rxbuf_rdpt > enc_r16(enc, CTL_REG_ERXNDL))) { 457 enc_w16(enc, CTL_REG_ERXRDPTL, 458 enc_r16(enc, CTL_REG_ERXNDL)); 459 } else { 460 enc_w16(enc, CTL_REG_ERXRDPTL, rxbuf_rdpt); 461 } 462 /* read pktcnt */ 463 pkt_cnt = enc_r8(enc, CTL_REG_EPKTCNT); 464 if (copy_len == 0) { 465 (void)enc_r8(enc, CTL_REG_EIR); 466 enc_reset_rx(enc); 467 printf("%s: receive copy_len=0\n", enc->dev->name); 468 continue; 469 } 470 /* 471 * Because NetReceive() might call enc_send(), we need to 472 * release the SPI bus, call NetReceive(), reclaim the bus 473 */ 474 enc_release_bus(enc); 475 NetReceive(packet, pkt_len); 476 if (enc_claim_bus(enc)) 477 return; 478 (void)enc_r8(enc, CTL_REG_EIR); 479 } while (pkt_cnt); 480 /* Use EPKTCNT not EIR.PKTIF flag, see errata pt. 6 */ 481 } 482 483 /* 484 * Poll for completely received packets. 485 */ 486 static void enc_poll(enc_dev_t *enc) 487 { 488 u8 eir_reg; 489 u8 pkt_cnt; 490 491 #ifdef CONFIG_USE_IRQ 492 /* clear global interrupt enable bit in enc28j60 */ 493 enc_bclr(enc, CTL_REG_EIE, ENC_EIE_INTIE); 494 #endif 495 (void)enc_r8(enc, CTL_REG_ESTAT); 496 eir_reg = enc_r8(enc, CTL_REG_EIR); 497 if (eir_reg & ENC_EIR_TXIF) { 498 /* clear TXIF bit in EIR */ 499 enc_bclr(enc, CTL_REG_EIR, ENC_EIR_TXIF); 500 } 501 /* We have to use pktcnt and not pktif bit, see errata pt. 6 */ 502 pkt_cnt = enc_r8(enc, CTL_REG_EPKTCNT); 503 if (pkt_cnt > 0) { 504 if ((eir_reg & ENC_EIR_PKTIF) == 0) { 505 debug("enc_poll: pkt cnt > 0, but pktif not set\n"); 506 } 507 enc_receive(enc); 508 /* 509 * clear PKTIF bit in EIR, this should not need to be done 510 * but it seems like we get problems if we do not 511 */ 512 enc_bclr(enc, CTL_REG_EIR, ENC_EIR_PKTIF); 513 } 514 if (eir_reg & ENC_EIR_RXERIF) { 515 printf("%s: rx error\n", enc->dev->name); 516 enc_bclr(enc, CTL_REG_EIR, ENC_EIR_RXERIF); 517 } 518 if (eir_reg & ENC_EIR_TXERIF) { 519 printf("%s: tx error\n", enc->dev->name); 520 enc_bclr(enc, CTL_REG_EIR, ENC_EIR_TXERIF); 521 } 522 #ifdef CONFIG_USE_IRQ 523 /* set global interrupt enable bit in enc28j60 */ 524 enc_bset(enc, CTL_REG_EIE, ENC_EIE_INTIE); 525 #endif 526 } 527 528 /* 529 * Completely Reset the ENC 530 */ 531 static void enc_reset(enc_dev_t *enc) 532 { 533 u8 dout[1]; 534 535 dout[0] = CMD_SRC; 536 spi_xfer(enc->slave, 8, dout, NULL, 537 SPI_XFER_BEGIN | SPI_XFER_END); 538 /* sleep 1 ms. See errata pt. 2 */ 539 udelay(1000); 540 } 541 542 /* 543 * Initialisation data for most of the ENC registers 544 */ 545 static const u16 enc_initdata[] = { 546 /* 547 * Setup the buffer space. The reset values are valid for the 548 * other pointers. 549 * 550 * We shall not write to ERXST, see errata pt. 5. Instead we 551 * have to make sure that ENC_RX_BUS_START is 0. 552 */ 553 CTL_REG_ERXSTL, ENC_RX_BUF_START, 554 CTL_REG_ERXSTH, ENC_RX_BUF_START >> 8, 555 CTL_REG_ERXNDL, ENC_RX_BUF_END, 556 CTL_REG_ERXNDH, ENC_RX_BUF_END >> 8, 557 CTL_REG_ERDPTL, ENC_RX_BUF_START, 558 CTL_REG_ERDPTH, ENC_RX_BUF_START >> 8, 559 /* 560 * Set the filter to receive only good-CRC, unicast and broadcast 561 * frames. 562 * Note: some DHCP servers return their answers as broadcasts! 563 * So its unwise to remove broadcast from this. This driver 564 * might incur receiver overruns with packet loss on a broadcast 565 * flooded network. 566 */ 567 CTL_REG_ERXFCON, ENC_RFR_BCEN | ENC_RFR_UCEN | ENC_RFR_CRCEN, 568 569 /* enable MAC to receive frames */ 570 CTL_REG_MACON1, 571 ENC_MACON1_MARXEN | ENC_MACON1_TXPAUS | ENC_MACON1_RXPAUS, 572 573 /* configure pad, tx-crc and duplex */ 574 CTL_REG_MACON3, 575 ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN | 576 ENC_MACON3_FRMLNEN, 577 578 /* Allow infinite deferals if the medium is continously busy */ 579 CTL_REG_MACON4, ENC_MACON4_DEFER, 580 581 /* Late collisions occur beyond 63 bytes */ 582 CTL_REG_MACLCON2, 63, 583 584 /* 585 * Set (low byte) Non-Back-to_Back Inter-Packet Gap. 586 * Recommended 0x12 587 */ 588 CTL_REG_MAIPGL, 0x12, 589 590 /* 591 * Set (high byte) Non-Back-to_Back Inter-Packet Gap. 592 * Recommended 0x0c for half-duplex. Nothing for full-duplex 593 */ 594 CTL_REG_MAIPGH, 0x0C, 595 596 /* set maximum frame length */ 597 CTL_REG_MAMXFLL, ENC_MAX_FRM_LEN, 598 CTL_REG_MAMXFLH, ENC_MAX_FRM_LEN >> 8, 599 600 /* 601 * Set MAC back-to-back inter-packet gap. 602 * Recommended 0x12 for half duplex 603 * and 0x15 for full duplex. 604 */ 605 CTL_REG_MABBIPG, 0x12, 606 607 /* end of table */ 608 0xffff 609 }; 610 611 /* 612 * Wait for the XTAL oscillator to become ready 613 */ 614 static int enc_clock_wait(enc_dev_t *enc) 615 { 616 uint64_t etime; 617 618 /* one second timeout */ 619 etime = get_ticks() + get_tbclk(); 620 621 /* 622 * Wait for CLKRDY to become set (i.e., check that we can 623 * communicate with the ENC) 624 */ 625 do 626 { 627 if (enc_r8(enc, CTL_REG_ESTAT) & ENC_ESTAT_CLKRDY) 628 return 0; 629 } while (get_ticks() <= etime); 630 631 printf("%s: timeout waiting for CLKRDY\n", enc->dev->name); 632 return -1; 633 } 634 635 /* 636 * Write the MAC address into the ENC 637 */ 638 static int enc_write_macaddr(enc_dev_t *enc) 639 { 640 unsigned char *p = enc->dev->enetaddr; 641 642 enc_w8_retry(enc, CTL_REG_MAADR5, *p++, 5); 643 enc_w8_retry(enc, CTL_REG_MAADR4, *p++, 5); 644 enc_w8_retry(enc, CTL_REG_MAADR3, *p++, 5); 645 enc_w8_retry(enc, CTL_REG_MAADR2, *p++, 5); 646 enc_w8_retry(enc, CTL_REG_MAADR1, *p++, 5); 647 enc_w8_retry(enc, CTL_REG_MAADR0, *p, 5); 648 return 0; 649 } 650 651 /* 652 * Setup most of the ENC registers 653 */ 654 static int enc_setup(enc_dev_t *enc) 655 { 656 u16 phid1 = 0; 657 u16 phid2 = 0; 658 const u16 *tp; 659 660 /* reset enc struct values */ 661 enc->next_pointer = ENC_RX_BUF_START; 662 enc->rx_reset_counter = RX_RESET_COUNTER; 663 enc->bank = 0xff; /* invalidate current bank in enc28j60 */ 664 665 /* verify PHY identification */ 666 phid1 = enc_phy_read(enc, PHY_REG_PHID1); 667 phid2 = enc_phy_read(enc, PHY_REG_PHID2) & ENC_PHID2_MASK; 668 if (phid1 != ENC_PHID1_VALUE || phid2 != ENC_PHID2_VALUE) { 669 printf("%s: failed to identify PHY. Found %04x:%04x\n", 670 enc->dev->name, phid1, phid2); 671 return -1; 672 } 673 674 /* now program registers */ 675 for (tp = enc_initdata; *tp != 0xffff; tp += 2) 676 enc_w8_retry(enc, tp[0], tp[1], 10); 677 678 /* 679 * Prevent automatic loopback of data beeing transmitted by setting 680 * ENC_PHCON2_HDLDIS 681 */ 682 enc_phy_write(enc, PHY_REG_PHCON2, (1<<8)); 683 684 /* 685 * LEDs configuration 686 * LEDA: LACFG = 0100 -> display link status 687 * LEDB: LBCFG = 0111 -> display TX & RX activity 688 * STRCH = 1 -> LED pulses 689 */ 690 enc_phy_write(enc, PHY_REG_PHLCON, 0x0472); 691 692 /* Reset PDPXMD-bit => half duplex */ 693 enc_phy_write(enc, PHY_REG_PHCON1, 0); 694 695 #ifdef CONFIG_USE_IRQ 696 /* enable interrupts */ 697 enc_bset(enc, CTL_REG_EIE, ENC_EIE_PKTIE); 698 enc_bset(enc, CTL_REG_EIE, ENC_EIE_TXIE); 699 enc_bset(enc, CTL_REG_EIE, ENC_EIE_RXERIE); 700 enc_bset(enc, CTL_REG_EIE, ENC_EIE_TXERIE); 701 enc_bset(enc, CTL_REG_EIE, ENC_EIE_INTIE); 702 #endif 703 704 return 0; 705 } 706 707 /* 708 * Check if ENC has been initialized. 709 * If not, try to initialize it. 710 * Remember initialized state in struct. 711 */ 712 static int enc_initcheck(enc_dev_t *enc, const enum enc_initstate requiredstate) 713 { 714 if (enc->initstate >= requiredstate) 715 return 0; 716 717 if (enc->initstate < setupdone) { 718 /* Initialize the ENC only */ 719 enc_reset(enc); 720 /* if any of functions fails, skip the rest and return an error */ 721 if (enc_clock_wait(enc) || enc_setup(enc) || enc_write_macaddr(enc)) { 722 return -1; 723 } 724 enc->initstate = setupdone; 725 } 726 /* if that's all we need, return here */ 727 if (enc->initstate >= requiredstate) 728 return 0; 729 730 /* now wait for link ready condition */ 731 if (enc_phy_link_wait(enc)) { 732 return -1; 733 } 734 enc->initstate = linkready; 735 return 0; 736 } 737 738 #if defined(CONFIG_CMD_MII) 739 /* 740 * Read a PHY register. 741 * 742 * This function is registered with miiphy_register(). 743 */ 744 int enc_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value) 745 { 746 struct eth_device *dev = eth_get_dev_by_name(devname); 747 enc_dev_t *enc; 748 749 if (!dev || phy_adr != 0) 750 return -1; 751 752 enc = dev->priv; 753 if (enc_claim_bus(enc)) 754 return -1; 755 if (enc_initcheck(enc, setupdone)) { 756 enc_release_bus(enc); 757 return -1; 758 } 759 *value = enc_phy_read(enc, reg); 760 enc_release_bus(enc); 761 return 0; 762 } 763 764 /* 765 * Write a PHY register. 766 * 767 * This function is registered with miiphy_register(). 768 */ 769 int enc_miiphy_write(const char *devname, u8 phy_adr, u8 reg, u16 value) 770 { 771 struct eth_device *dev = eth_get_dev_by_name(devname); 772 enc_dev_t *enc; 773 774 if (!dev || phy_adr != 0) 775 return -1; 776 777 enc = dev->priv; 778 if (enc_claim_bus(enc)) 779 return -1; 780 if (enc_initcheck(enc, setupdone)) { 781 enc_release_bus(enc); 782 return -1; 783 } 784 enc_phy_write(enc, reg, value); 785 enc_release_bus(enc); 786 return 0; 787 } 788 #endif 789 790 /* 791 * Write hardware (MAC) address. 792 * 793 * This function entered into eth_device structure. 794 */ 795 static int enc_write_hwaddr(struct eth_device *dev) 796 { 797 enc_dev_t *enc = dev->priv; 798 799 if (enc_claim_bus(enc)) 800 return -1; 801 if (enc_initcheck(enc, setupdone)) { 802 enc_release_bus(enc); 803 return -1; 804 } 805 enc_release_bus(enc); 806 return 0; 807 } 808 809 /* 810 * Initialize ENC28J60 for use. 811 * 812 * This function entered into eth_device structure. 813 */ 814 static int enc_init(struct eth_device *dev, bd_t *bis) 815 { 816 enc_dev_t *enc = dev->priv; 817 818 if (enc_claim_bus(enc)) 819 return -1; 820 if (enc_initcheck(enc, linkready)) { 821 enc_release_bus(enc); 822 return -1; 823 } 824 /* enable receive */ 825 enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXEN); 826 enc_release_bus(enc); 827 return 0; 828 } 829 830 /* 831 * Check for received packets. 832 * 833 * This function entered into eth_device structure. 834 */ 835 static int enc_recv(struct eth_device *dev) 836 { 837 enc_dev_t *enc = dev->priv; 838 839 if (enc_claim_bus(enc)) 840 return -1; 841 if (enc_initcheck(enc, linkready)) { 842 enc_release_bus(enc); 843 return -1; 844 } 845 /* Check for dead receiver */ 846 if (enc->rx_reset_counter > 0) 847 enc->rx_reset_counter--; 848 else 849 enc_reset_rx_call(enc); 850 enc_poll(enc); 851 enc_release_bus(enc); 852 return 0; 853 } 854 855 /* 856 * Send a packet. 857 * 858 * This function entered into eth_device structure. 859 * 860 * Should we wait here until we have a Link? Or shall we leave that to 861 * protocol retries? 862 */ 863 static int enc_send( 864 struct eth_device *dev, 865 void *packet, 866 int length) 867 { 868 enc_dev_t *enc = dev->priv; 869 870 if (enc_claim_bus(enc)) 871 return -1; 872 if (enc_initcheck(enc, linkready)) { 873 enc_release_bus(enc); 874 return -1; 875 } 876 /* setup transmit pointers */ 877 enc_w16(enc, CTL_REG_EWRPTL, ENC_TX_BUF_START); 878 enc_w16(enc, CTL_REG_ETXNDL, length + ENC_TX_BUF_START); 879 enc_w16(enc, CTL_REG_ETXSTL, ENC_TX_BUF_START); 880 /* write packet to ENC */ 881 enc_wbuf(enc, length, (u8 *) packet, 0x00); 882 /* 883 * Check that the internal transmit logic has not been altered 884 * by excessive collisions. Reset transmitter if so. 885 * See Errata B4 12 and 14. 886 */ 887 if (enc_r8(enc, CTL_REG_EIR) & ENC_EIR_TXERIF) { 888 enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_TXRST); 889 enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_TXRST); 890 } 891 enc_bclr(enc, CTL_REG_EIR, (ENC_EIR_TXERIF | ENC_EIR_TXIF)); 892 /* start transmitting */ 893 enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_TXRTS); 894 enc_release_bus(enc); 895 return 0; 896 } 897 898 /* 899 * Finish use of ENC. 900 * 901 * This function entered into eth_device structure. 902 */ 903 static void enc_halt(struct eth_device *dev) 904 { 905 enc_dev_t *enc = dev->priv; 906 907 if (enc_claim_bus(enc)) 908 return; 909 /* Just disable receiver */ 910 enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_RXEN); 911 enc_release_bus(enc); 912 } 913 914 /* 915 * This is the only exported function. 916 * 917 * It may be called several times with different bus:cs combinations. 918 */ 919 int enc28j60_initialize(unsigned int bus, unsigned int cs, 920 unsigned int max_hz, unsigned int mode) 921 { 922 struct eth_device *dev; 923 enc_dev_t *enc; 924 925 /* try to allocate, check and clear eth_device object */ 926 dev = malloc(sizeof(*dev)); 927 if (!dev) { 928 return -1; 929 } 930 memset(dev, 0, sizeof(*dev)); 931 932 /* try to allocate, check and clear enc_dev_t object */ 933 enc = malloc(sizeof(*enc)); 934 if (!enc) { 935 free(dev); 936 return -1; 937 } 938 memset(enc, 0, sizeof(*enc)); 939 940 /* try to setup the SPI slave */ 941 enc->slave = spi_setup_slave(bus, cs, max_hz, mode); 942 if (!enc->slave) { 943 printf("enc28j60: invalid SPI device %i:%i\n", bus, cs); 944 free(enc); 945 free(dev); 946 return -1; 947 } 948 949 enc->dev = dev; 950 /* now fill the eth_device object */ 951 dev->priv = enc; 952 dev->init = enc_init; 953 dev->halt = enc_halt; 954 dev->send = enc_send; 955 dev->recv = enc_recv; 956 dev->write_hwaddr = enc_write_hwaddr; 957 sprintf(dev->name, "enc%i.%i", bus, cs); 958 eth_register(dev); 959 #if defined(CONFIG_CMD_MII) 960 miiphy_register(dev->name, enc_miiphy_read, enc_miiphy_write); 961 #endif 962 return 0; 963 } 964