1 /* 2 * (C) Copyright 2010 3 * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de 4 * Martin Krause, Martin.Krause@tqs.de 5 * reworked original enc28j60.c 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <net.h> 25 #include <spi.h> 26 #include <malloc.h> 27 #include <netdev.h> 28 #include <miiphy.h> 29 #include "enc28j60.h" 30 31 /* 32 * IMPORTANT: spi_claim_bus() and spi_release_bus() 33 * are called at begin and end of each of the following functions: 34 * enc_miiphy_read(), enc_miiphy_write(), enc_write_hwaddr(), 35 * enc_init(), enc_recv(), enc_send(), enc_halt() 36 * ALL other functions assume that the bus has already been claimed! 37 * Since NetReceive() might call enc_send() in return, the bus must be 38 * released, NetReceive() called and claimed again. 39 */ 40 41 /* 42 * Controller memory layout. 43 * We only allow 1 frame for transmission and reserve the rest 44 * for reception to handle as many broadcast packets as possible. 45 * Also use the memory from 0x0000 for receiver buffer. See errata pt. 5 46 * 0x0000 - 0x19ff 6656 bytes receive buffer 47 * 0x1a00 - 0x1fff 1536 bytes transmit buffer = 48 * control(1)+frame(1518)+status(7)+reserve(10). 49 */ 50 #define ENC_RX_BUF_START 0x0000 51 #define ENC_RX_BUF_END 0x19ff 52 #define ENC_TX_BUF_START 0x1a00 53 #define ENC_TX_BUF_END 0x1fff 54 #define ENC_MAX_FRM_LEN 1518 55 #define RX_RESET_COUNTER 1000 56 57 /* 58 * For non data transfer functions, like phy read/write, set hwaddr, init 59 * we do not need a full, time consuming init including link ready wait. 60 * This enum helps to bring the chip through the minimum necessary inits. 61 */ 62 enum enc_initstate {none=0, setupdone, linkready}; 63 typedef struct enc_device { 64 struct eth_device *dev; /* back pointer */ 65 struct spi_slave *slave; 66 int rx_reset_counter; 67 u16 next_pointer; 68 u8 bank; /* current bank in enc28j60 */ 69 enum enc_initstate initstate; 70 } enc_dev_t; 71 72 /* 73 * enc_bset: set bits in a common register 74 * enc_bclr: clear bits in a common register 75 * 76 * making the reg parameter u8 will give a compile time warning if the 77 * functions are called with a register not accessible in all Banks 78 */ 79 static void enc_bset(enc_dev_t *enc, const u8 reg, const u8 data) 80 { 81 u8 dout[2]; 82 83 dout[0] = CMD_BFS(reg); 84 dout[1] = data; 85 spi_xfer(enc->slave, 2 * 8, dout, NULL, 86 SPI_XFER_BEGIN | SPI_XFER_END); 87 } 88 89 static void enc_bclr(enc_dev_t *enc, const u8 reg, const u8 data) 90 { 91 u8 dout[2]; 92 93 dout[0] = CMD_BFC(reg); 94 dout[1] = data; 95 spi_xfer(enc->slave, 2 * 8, dout, NULL, 96 SPI_XFER_BEGIN | SPI_XFER_END); 97 } 98 99 /* 100 * high byte of the register contains bank number: 101 * 0: no bank switch necessary 102 * 1: switch to bank 0 103 * 2: switch to bank 1 104 * 3: switch to bank 2 105 * 4: switch to bank 3 106 */ 107 static void enc_set_bank(enc_dev_t *enc, const u16 reg) 108 { 109 u8 newbank = reg >> 8; 110 111 if (newbank == 0 || newbank == enc->bank) 112 return; 113 switch (newbank) { 114 case 1: 115 enc_bclr(enc, CTL_REG_ECON1, 116 ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1); 117 break; 118 case 2: 119 enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_BSEL0); 120 enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_BSEL1); 121 break; 122 case 3: 123 enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_BSEL0); 124 enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_BSEL1); 125 break; 126 case 4: 127 enc_bset(enc, CTL_REG_ECON1, 128 ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1); 129 break; 130 } 131 enc->bank = newbank; 132 } 133 134 /* 135 * local functions to access SPI 136 * 137 * reg: register inside ENC28J60 138 * data: 8/16 bits to write 139 * c: number of retries 140 * 141 * enc_r8: read 8 bits 142 * enc_r16: read 16 bits 143 * enc_w8: write 8 bits 144 * enc_w16: write 16 bits 145 * enc_w8_retry: write 8 bits, verify and retry 146 * enc_rbuf: read from ENC28J60 into buffer 147 * enc_wbuf: write from buffer into ENC28J60 148 */ 149 150 /* 151 * MAC and MII registers need a 3 byte SPI transfer to read, 152 * all other registers need a 2 byte SPI transfer. 153 */ 154 static int enc_reg2nbytes(const u16 reg) 155 { 156 /* check if MAC or MII register */ 157 return ((reg >= CTL_REG_MACON1 && reg <= CTL_REG_MIRDH) || 158 (reg >= CTL_REG_MAADR1 && reg <= CTL_REG_MAADR4) || 159 (reg == CTL_REG_MISTAT)) ? 3 : 2; 160 } 161 162 /* 163 * Read a byte register 164 */ 165 static u8 enc_r8(enc_dev_t *enc, const u16 reg) 166 { 167 u8 dout[3]; 168 u8 din[3]; 169 int nbytes = enc_reg2nbytes(reg); 170 171 enc_set_bank(enc, reg); 172 dout[0] = CMD_RCR(reg); 173 spi_xfer(enc->slave, nbytes * 8, dout, din, 174 SPI_XFER_BEGIN | SPI_XFER_END); 175 return din[nbytes-1]; 176 } 177 178 /* 179 * Read a L/H register pair and return a word. 180 * Must be called with the L register's address. 181 */ 182 static u16 enc_r16(enc_dev_t *enc, const u16 reg) 183 { 184 u8 dout[3]; 185 u8 din[3]; 186 u16 result; 187 int nbytes = enc_reg2nbytes(reg); 188 189 enc_set_bank(enc, reg); 190 dout[0] = CMD_RCR(reg); 191 spi_xfer(enc->slave, nbytes * 8, dout, din, 192 SPI_XFER_BEGIN | SPI_XFER_END); 193 result = din[nbytes-1]; 194 dout[0]++; /* next register */ 195 spi_xfer(enc->slave, nbytes * 8, dout, din, 196 SPI_XFER_BEGIN | SPI_XFER_END); 197 result |= din[nbytes-1] << 8; 198 return result; 199 } 200 201 /* 202 * Write a byte register 203 */ 204 static void enc_w8(enc_dev_t *enc, const u16 reg, const u8 data) 205 { 206 u8 dout[2]; 207 208 enc_set_bank(enc, reg); 209 dout[0] = CMD_WCR(reg); 210 dout[1] = data; 211 spi_xfer(enc->slave, 2 * 8, dout, NULL, 212 SPI_XFER_BEGIN | SPI_XFER_END); 213 } 214 215 /* 216 * Write a L/H register pair. 217 * Must be called with the L register's address. 218 */ 219 static void enc_w16(enc_dev_t *enc, const u16 reg, const u16 data) 220 { 221 u8 dout[2]; 222 223 enc_set_bank(enc, reg); 224 dout[0] = CMD_WCR(reg); 225 dout[1] = data; 226 spi_xfer(enc->slave, 2 * 8, dout, NULL, 227 SPI_XFER_BEGIN | SPI_XFER_END); 228 dout[0]++; /* next register */ 229 dout[1] = data >> 8; 230 spi_xfer(enc->slave, 2 * 8, dout, NULL, 231 SPI_XFER_BEGIN | SPI_XFER_END); 232 } 233 234 /* 235 * Write a byte register, verify and retry 236 */ 237 static void enc_w8_retry(enc_dev_t *enc, const u16 reg, const u8 data, const int c) 238 { 239 u8 dout[2]; 240 u8 readback; 241 int i; 242 243 enc_set_bank(enc, reg); 244 for (i = 0; i < c; i++) { 245 dout[0] = CMD_WCR(reg); 246 dout[1] = data; 247 spi_xfer(enc->slave, 2 * 8, dout, NULL, 248 SPI_XFER_BEGIN | SPI_XFER_END); 249 readback = enc_r8(enc, reg); 250 if (readback == data) 251 break; 252 /* wait 1ms */ 253 udelay(1000); 254 } 255 if (i == c) { 256 printf("%s: write reg 0x%03x failed\n", enc->dev->name, reg); 257 } 258 } 259 260 /* 261 * Read ENC RAM into buffer 262 */ 263 static void enc_rbuf(enc_dev_t *enc, const u16 length, u8 *buf) 264 { 265 u8 dout[1]; 266 267 dout[0] = CMD_RBM; 268 spi_xfer(enc->slave, 8, dout, NULL, SPI_XFER_BEGIN); 269 spi_xfer(enc->slave, length * 8, NULL, buf, SPI_XFER_END); 270 #ifdef DEBUG 271 puts("Rx:\n"); 272 print_buffer(0, buf, 1, length, 0); 273 #endif 274 } 275 276 /* 277 * Write buffer into ENC RAM 278 */ 279 static void enc_wbuf(enc_dev_t *enc, const u16 length, const u8 *buf, const u8 control) 280 { 281 u8 dout[2]; 282 dout[0] = CMD_WBM; 283 dout[1] = control; 284 spi_xfer(enc->slave, 2 * 8, dout, NULL, SPI_XFER_BEGIN); 285 spi_xfer(enc->slave, length * 8, buf, NULL, SPI_XFER_END); 286 #ifdef DEBUG 287 puts("Tx:\n"); 288 print_buffer(0, buf, 1, length, 0); 289 #endif 290 } 291 292 /* 293 * Try to claim the SPI bus. 294 * Print error message on failure. 295 */ 296 static int enc_claim_bus(enc_dev_t *enc) 297 { 298 int rc = spi_claim_bus(enc->slave); 299 if (rc) 300 printf("%s: failed to claim SPI bus\n", enc->dev->name); 301 return rc; 302 } 303 304 /* 305 * Release previously claimed SPI bus. 306 * This function is mainly for symmetry to enc_claim_bus(). 307 * Let the toolchain decide to inline it... 308 */ 309 static void enc_release_bus(enc_dev_t *enc) 310 { 311 spi_release_bus(enc->slave); 312 } 313 314 /* 315 * Read PHY register 316 */ 317 static u16 enc_phy_read(enc_dev_t *enc, const u8 addr) 318 { 319 uint64_t etime; 320 u8 status; 321 322 enc_w8(enc, CTL_REG_MIREGADR, addr); 323 enc_w8(enc, CTL_REG_MICMD, ENC_MICMD_MIIRD); 324 /* 1 second timeout - only happens on hardware problem */ 325 etime = get_ticks() + get_tbclk(); 326 /* poll MISTAT.BUSY bit until operation is complete */ 327 do 328 { 329 status = enc_r8(enc, CTL_REG_MISTAT); 330 } while (get_ticks() <= etime && (status & ENC_MISTAT_BUSY)); 331 if (status & ENC_MISTAT_BUSY) { 332 printf("%s: timeout reading phy\n", enc->dev->name); 333 return 0; 334 } 335 enc_w8(enc, CTL_REG_MICMD, 0); 336 return enc_r16(enc, CTL_REG_MIRDL); 337 } 338 339 /* 340 * Write PHY register 341 */ 342 static void enc_phy_write(enc_dev_t *enc, const u8 addr, const u16 data) 343 { 344 uint64_t etime; 345 u8 status; 346 347 enc_w8(enc, CTL_REG_MIREGADR, addr); 348 enc_w16(enc, CTL_REG_MIWRL, data); 349 /* 1 second timeout - only happens on hardware problem */ 350 etime = get_ticks() + get_tbclk(); 351 /* poll MISTAT.BUSY bit until operation is complete */ 352 do 353 { 354 status = enc_r8(enc, CTL_REG_MISTAT); 355 } while (get_ticks() <= etime && (status & ENC_MISTAT_BUSY)); 356 if (status & ENC_MISTAT_BUSY) { 357 printf("%s: timeout writing phy\n", enc->dev->name); 358 return; 359 } 360 } 361 362 /* 363 * Verify link status, wait if necessary 364 * 365 * Note: with a 10 MBit/s only PHY there is no autonegotiation possible, 366 * half/full duplex is a pure setup matter. For the time being, this driver 367 * will setup in half duplex mode only. 368 */ 369 static int enc_phy_link_wait(enc_dev_t *enc) 370 { 371 u16 status; 372 int duplex; 373 uint64_t etime; 374 375 #ifdef CONFIG_ENC_SILENTLINK 376 /* check if we have a link, then just return */ 377 status = enc_phy_read(enc, PHY_REG_PHSTAT1); 378 if (status & ENC_PHSTAT1_LLSTAT) 379 return 0; 380 #endif 381 382 /* wait for link with 1 second timeout */ 383 etime = get_ticks() + get_tbclk(); 384 while (get_ticks() <= etime) { 385 status = enc_phy_read(enc, PHY_REG_PHSTAT1); 386 if (status & ENC_PHSTAT1_LLSTAT) { 387 /* now we have a link */ 388 status = enc_phy_read(enc, PHY_REG_PHSTAT2); 389 duplex = (status & ENC_PHSTAT2_DPXSTAT) ? 1 : 0; 390 printf("%s: link up, 10Mbps %s-duplex\n", 391 enc->dev->name, duplex ? "full" : "half"); 392 return 0; 393 } 394 udelay(1000); 395 } 396 397 /* timeout occured */ 398 printf("%s: link down\n", enc->dev->name); 399 return 1; 400 } 401 402 /* 403 * This function resets the receiver only. 404 */ 405 static void enc_reset_rx(enc_dev_t *enc) 406 { 407 u8 econ1; 408 409 econ1 = enc_r8(enc, CTL_REG_ECON1); 410 if ((econ1 & ENC_ECON1_RXRST) == 0) { 411 enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXRST); 412 enc->rx_reset_counter = RX_RESET_COUNTER; 413 } 414 } 415 416 /* 417 * Reset receiver and reenable it. 418 */ 419 static void enc_reset_rx_call(enc_dev_t *enc) 420 { 421 enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_RXRST); 422 enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXEN); 423 } 424 425 /* 426 * Copy a packet from the receive ring and forward it to 427 * the protocol stack. 428 */ 429 static void enc_receive(enc_dev_t *enc) 430 { 431 u8 *packet = (u8 *)NetRxPackets[0]; 432 u16 pkt_len; 433 u16 copy_len; 434 u16 status; 435 u8 pkt_cnt = 0; 436 u16 rxbuf_rdpt; 437 u8 hbuf[6]; 438 439 enc_w16(enc, CTL_REG_ERDPTL, enc->next_pointer); 440 do { 441 enc_rbuf(enc, 6, hbuf); 442 enc->next_pointer = hbuf[0] | (hbuf[1] << 8); 443 pkt_len = hbuf[2] | (hbuf[3] << 8); 444 status = hbuf[4] | (hbuf[5] << 8); 445 debug("next_pointer=$%04x pkt_len=%u status=$%04x\n", 446 enc->next_pointer, pkt_len, status); 447 if (pkt_len <= ENC_MAX_FRM_LEN) 448 copy_len = pkt_len; 449 else 450 copy_len = 0; 451 if ((status & (1L << 7)) == 0) /* check Received Ok bit */ 452 copy_len = 0; 453 /* check if next pointer is resonable */ 454 if (enc->next_pointer >= ENC_TX_BUF_START) 455 copy_len = 0; 456 if (copy_len > 0) { 457 enc_rbuf(enc, copy_len, packet); 458 } 459 /* advance read pointer to next pointer */ 460 enc_w16(enc, CTL_REG_ERDPTL, enc->next_pointer); 461 /* decrease packet counter */ 462 enc_bset(enc, CTL_REG_ECON2, ENC_ECON2_PKTDEC); 463 /* 464 * Only odd values should be written to ERXRDPTL, 465 * see errata B4 pt.13 466 */ 467 rxbuf_rdpt = enc->next_pointer - 1; 468 if ((rxbuf_rdpt < enc_r16(enc, CTL_REG_ERXSTL)) || 469 (rxbuf_rdpt > enc_r16(enc, CTL_REG_ERXNDL))) { 470 enc_w16(enc, CTL_REG_ERXRDPTL, 471 enc_r16(enc, CTL_REG_ERXNDL)); 472 } else { 473 enc_w16(enc, CTL_REG_ERXRDPTL, rxbuf_rdpt); 474 } 475 /* read pktcnt */ 476 pkt_cnt = enc_r8(enc, CTL_REG_EPKTCNT); 477 if (copy_len == 0) { 478 (void)enc_r8(enc, CTL_REG_EIR); 479 enc_reset_rx(enc); 480 printf("%s: receive copy_len=0\n", enc->dev->name); 481 continue; 482 } 483 /* 484 * Because NetReceive() might call enc_send(), we need to 485 * release the SPI bus, call NetReceive(), reclaim the bus 486 */ 487 enc_release_bus(enc); 488 NetReceive(packet, pkt_len); 489 if (enc_claim_bus(enc)) 490 return; 491 (void)enc_r8(enc, CTL_REG_EIR); 492 } while (pkt_cnt); 493 /* Use EPKTCNT not EIR.PKTIF flag, see errata pt. 6 */ 494 } 495 496 /* 497 * Poll for completely received packets. 498 */ 499 static void enc_poll(enc_dev_t *enc) 500 { 501 u8 eir_reg; 502 u8 pkt_cnt; 503 504 #ifdef CONFIG_USE_IRQ 505 /* clear global interrupt enable bit in enc28j60 */ 506 enc_bclr(enc, CTL_REG_EIE, ENC_EIE_INTIE); 507 #endif 508 (void)enc_r8(enc, CTL_REG_ESTAT); 509 eir_reg = enc_r8(enc, CTL_REG_EIR); 510 if (eir_reg & ENC_EIR_TXIF) { 511 /* clear TXIF bit in EIR */ 512 enc_bclr(enc, CTL_REG_EIR, ENC_EIR_TXIF); 513 } 514 /* We have to use pktcnt and not pktif bit, see errata pt. 6 */ 515 pkt_cnt = enc_r8(enc, CTL_REG_EPKTCNT); 516 if (pkt_cnt > 0) { 517 if ((eir_reg & ENC_EIR_PKTIF) == 0) { 518 debug("enc_poll: pkt cnt > 0, but pktif not set\n"); 519 } 520 enc_receive(enc); 521 /* 522 * clear PKTIF bit in EIR, this should not need to be done 523 * but it seems like we get problems if we do not 524 */ 525 enc_bclr(enc, CTL_REG_EIR, ENC_EIR_PKTIF); 526 } 527 if (eir_reg & ENC_EIR_RXERIF) { 528 printf("%s: rx error\n", enc->dev->name); 529 enc_bclr(enc, CTL_REG_EIR, ENC_EIR_RXERIF); 530 } 531 if (eir_reg & ENC_EIR_TXERIF) { 532 printf("%s: tx error\n", enc->dev->name); 533 enc_bclr(enc, CTL_REG_EIR, ENC_EIR_TXERIF); 534 } 535 #ifdef CONFIG_USE_IRQ 536 /* set global interrupt enable bit in enc28j60 */ 537 enc_bset(enc, CTL_REG_EIE, ENC_EIE_INTIE); 538 #endif 539 } 540 541 /* 542 * Completely Reset the ENC 543 */ 544 static void enc_reset(enc_dev_t *enc) 545 { 546 u8 dout[1]; 547 548 dout[0] = CMD_SRC; 549 spi_xfer(enc->slave, 8, dout, NULL, 550 SPI_XFER_BEGIN | SPI_XFER_END); 551 /* sleep 1 ms. See errata pt. 2 */ 552 udelay(1000); 553 } 554 555 /* 556 * Initialisation data for most of the ENC registers 557 */ 558 static const u16 enc_initdata[] = { 559 /* 560 * Setup the buffer space. The reset values are valid for the 561 * other pointers. 562 * 563 * We shall not write to ERXST, see errata pt. 5. Instead we 564 * have to make sure that ENC_RX_BUS_START is 0. 565 */ 566 CTL_REG_ERXSTL, ENC_RX_BUF_START, 567 CTL_REG_ERXSTH, ENC_RX_BUF_START >> 8, 568 CTL_REG_ERXNDL, ENC_RX_BUF_END, 569 CTL_REG_ERXNDH, ENC_RX_BUF_END >> 8, 570 CTL_REG_ERDPTL, ENC_RX_BUF_START, 571 CTL_REG_ERDPTH, ENC_RX_BUF_START >> 8, 572 /* 573 * Set the filter to receive only good-CRC, unicast and broadcast 574 * frames. 575 * Note: some DHCP servers return their answers as broadcasts! 576 * So its unwise to remove broadcast from this. This driver 577 * might incur receiver overruns with packet loss on a broadcast 578 * flooded network. 579 */ 580 CTL_REG_ERXFCON, ENC_RFR_BCEN | ENC_RFR_UCEN | ENC_RFR_CRCEN, 581 582 /* enable MAC to receive frames */ 583 CTL_REG_MACON1, 584 ENC_MACON1_MARXEN | ENC_MACON1_TXPAUS | ENC_MACON1_RXPAUS, 585 586 /* configure pad, tx-crc and duplex */ 587 CTL_REG_MACON3, 588 ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN | 589 ENC_MACON3_FRMLNEN, 590 591 /* Allow infinite deferals if the medium is continously busy */ 592 CTL_REG_MACON4, ENC_MACON4_DEFER, 593 594 /* Late collisions occur beyond 63 bytes */ 595 CTL_REG_MACLCON2, 63, 596 597 /* 598 * Set (low byte) Non-Back-to_Back Inter-Packet Gap. 599 * Recommended 0x12 600 */ 601 CTL_REG_MAIPGL, 0x12, 602 603 /* 604 * Set (high byte) Non-Back-to_Back Inter-Packet Gap. 605 * Recommended 0x0c for half-duplex. Nothing for full-duplex 606 */ 607 CTL_REG_MAIPGH, 0x0C, 608 609 /* set maximum frame length */ 610 CTL_REG_MAMXFLL, ENC_MAX_FRM_LEN, 611 CTL_REG_MAMXFLH, ENC_MAX_FRM_LEN >> 8, 612 613 /* 614 * Set MAC back-to-back inter-packet gap. 615 * Recommended 0x12 for half duplex 616 * and 0x15 for full duplex. 617 */ 618 CTL_REG_MABBIPG, 0x12, 619 620 /* end of table */ 621 0xffff 622 }; 623 624 /* 625 * Wait for the XTAL oscillator to become ready 626 */ 627 static int enc_clock_wait(enc_dev_t *enc) 628 { 629 uint64_t etime; 630 631 /* one second timeout */ 632 etime = get_ticks() + get_tbclk(); 633 634 /* 635 * Wait for CLKRDY to become set (i.e., check that we can 636 * communicate with the ENC) 637 */ 638 do 639 { 640 if (enc_r8(enc, CTL_REG_ESTAT) & ENC_ESTAT_CLKRDY) 641 return 0; 642 } while (get_ticks() <= etime); 643 644 printf("%s: timeout waiting for CLKRDY\n", enc->dev->name); 645 return -1; 646 } 647 648 /* 649 * Write the MAC address into the ENC 650 */ 651 static int enc_write_macaddr(enc_dev_t *enc) 652 { 653 unsigned char *p = enc->dev->enetaddr; 654 655 enc_w8_retry(enc, CTL_REG_MAADR5, *p++, 5); 656 enc_w8_retry(enc, CTL_REG_MAADR4, *p++, 5); 657 enc_w8_retry(enc, CTL_REG_MAADR3, *p++, 5); 658 enc_w8_retry(enc, CTL_REG_MAADR2, *p++, 5); 659 enc_w8_retry(enc, CTL_REG_MAADR1, *p++, 5); 660 enc_w8_retry(enc, CTL_REG_MAADR0, *p, 5); 661 return 0; 662 } 663 664 /* 665 * Setup most of the ENC registers 666 */ 667 static int enc_setup(enc_dev_t *enc) 668 { 669 u16 phid1 = 0; 670 u16 phid2 = 0; 671 const u16 *tp; 672 673 /* reset enc struct values */ 674 enc->next_pointer = ENC_RX_BUF_START; 675 enc->rx_reset_counter = RX_RESET_COUNTER; 676 enc->bank = 0xff; /* invalidate current bank in enc28j60 */ 677 678 /* verify PHY identification */ 679 phid1 = enc_phy_read(enc, PHY_REG_PHID1); 680 phid2 = enc_phy_read(enc, PHY_REG_PHID2) & ENC_PHID2_MASK; 681 if (phid1 != ENC_PHID1_VALUE || phid2 != ENC_PHID2_VALUE) { 682 printf("%s: failed to identify PHY. Found %04x:%04x\n", 683 enc->dev->name, phid1, phid2); 684 return -1; 685 } 686 687 /* now program registers */ 688 for (tp = enc_initdata; *tp != 0xffff; tp += 2) 689 enc_w8_retry(enc, tp[0], tp[1], 10); 690 691 /* 692 * Prevent automatic loopback of data beeing transmitted by setting 693 * ENC_PHCON2_HDLDIS 694 */ 695 enc_phy_write(enc, PHY_REG_PHCON2, (1<<8)); 696 697 /* 698 * LEDs configuration 699 * LEDA: LACFG = 0100 -> display link status 700 * LEDB: LBCFG = 0111 -> display TX & RX activity 701 * STRCH = 1 -> LED pulses 702 */ 703 enc_phy_write(enc, PHY_REG_PHLCON, 0x0472); 704 705 /* Reset PDPXMD-bit => half duplex */ 706 enc_phy_write(enc, PHY_REG_PHCON1, 0); 707 708 #ifdef CONFIG_USE_IRQ 709 /* enable interrupts */ 710 enc_bset(enc, CTL_REG_EIE, ENC_EIE_PKTIE); 711 enc_bset(enc, CTL_REG_EIE, ENC_EIE_TXIE); 712 enc_bset(enc, CTL_REG_EIE, ENC_EIE_RXERIE); 713 enc_bset(enc, CTL_REG_EIE, ENC_EIE_TXERIE); 714 enc_bset(enc, CTL_REG_EIE, ENC_EIE_INTIE); 715 #endif 716 717 return 0; 718 } 719 720 /* 721 * Check if ENC has been initialized. 722 * If not, try to initialize it. 723 * Remember initialized state in struct. 724 */ 725 static int enc_initcheck(enc_dev_t *enc, const enum enc_initstate requiredstate) 726 { 727 if (enc->initstate >= requiredstate) 728 return 0; 729 730 if (enc->initstate < setupdone) { 731 /* Initialize the ENC only */ 732 enc_reset(enc); 733 /* if any of functions fails, skip the rest and return an error */ 734 if (enc_clock_wait(enc) || enc_setup(enc) || enc_write_macaddr(enc)) { 735 return -1; 736 } 737 enc->initstate = setupdone; 738 } 739 /* if that's all we need, return here */ 740 if (enc->initstate >= requiredstate) 741 return 0; 742 743 /* now wait for link ready condition */ 744 if (enc_phy_link_wait(enc)) { 745 return -1; 746 } 747 enc->initstate = linkready; 748 return 0; 749 } 750 751 #if defined(CONFIG_CMD_MII) 752 /* 753 * Read a PHY register. 754 * 755 * This function is registered with miiphy_register(). 756 */ 757 int enc_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value) 758 { 759 struct eth_device *dev = eth_get_dev_by_name(devname); 760 enc_dev_t *enc; 761 762 if (!dev || phy_adr != 0) 763 return -1; 764 765 enc = dev->priv; 766 if (enc_claim_bus(enc)) 767 return -1; 768 if (enc_initcheck(enc, setupdone)) { 769 enc_release_bus(enc); 770 return -1; 771 } 772 *value = enc_phy_read(enc, reg); 773 enc_release_bus(enc); 774 return 0; 775 } 776 777 /* 778 * Write a PHY register. 779 * 780 * This function is registered with miiphy_register(). 781 */ 782 int enc_miiphy_write(const char *devname, u8 phy_adr, u8 reg, u16 value) 783 { 784 struct eth_device *dev = eth_get_dev_by_name(devname); 785 enc_dev_t *enc; 786 787 if (!dev || phy_adr != 0) 788 return -1; 789 790 enc = dev->priv; 791 if (enc_claim_bus(enc)) 792 return -1; 793 if (enc_initcheck(enc, setupdone)) { 794 enc_release_bus(enc); 795 return -1; 796 } 797 enc_phy_write(enc, reg, value); 798 enc_release_bus(enc); 799 return 0; 800 } 801 #endif 802 803 /* 804 * Write hardware (MAC) address. 805 * 806 * This function entered into eth_device structure. 807 */ 808 static int enc_write_hwaddr(struct eth_device *dev) 809 { 810 enc_dev_t *enc = dev->priv; 811 812 if (enc_claim_bus(enc)) 813 return -1; 814 if (enc_initcheck(enc, setupdone)) { 815 enc_release_bus(enc); 816 return -1; 817 } 818 enc_release_bus(enc); 819 return 0; 820 } 821 822 /* 823 * Initialize ENC28J60 for use. 824 * 825 * This function entered into eth_device structure. 826 */ 827 static int enc_init(struct eth_device *dev, bd_t *bis) 828 { 829 enc_dev_t *enc = dev->priv; 830 831 if (enc_claim_bus(enc)) 832 return -1; 833 if (enc_initcheck(enc, linkready)) { 834 enc_release_bus(enc); 835 return -1; 836 } 837 /* enable receive */ 838 enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXEN); 839 enc_release_bus(enc); 840 return 0; 841 } 842 843 /* 844 * Check for received packets. 845 * 846 * This function entered into eth_device structure. 847 */ 848 static int enc_recv(struct eth_device *dev) 849 { 850 enc_dev_t *enc = dev->priv; 851 852 if (enc_claim_bus(enc)) 853 return -1; 854 if (enc_initcheck(enc, linkready)) { 855 enc_release_bus(enc); 856 return -1; 857 } 858 /* Check for dead receiver */ 859 if (enc->rx_reset_counter > 0) 860 enc->rx_reset_counter--; 861 else 862 enc_reset_rx_call(enc); 863 enc_poll(enc); 864 enc_release_bus(enc); 865 return 0; 866 } 867 868 /* 869 * Send a packet. 870 * 871 * This function entered into eth_device structure. 872 * 873 * Should we wait here until we have a Link? Or shall we leave that to 874 * protocol retries? 875 */ 876 static int enc_send( 877 struct eth_device *dev, 878 void *packet, 879 int length) 880 { 881 enc_dev_t *enc = dev->priv; 882 883 if (enc_claim_bus(enc)) 884 return -1; 885 if (enc_initcheck(enc, linkready)) { 886 enc_release_bus(enc); 887 return -1; 888 } 889 /* setup transmit pointers */ 890 enc_w16(enc, CTL_REG_EWRPTL, ENC_TX_BUF_START); 891 enc_w16(enc, CTL_REG_ETXNDL, length + ENC_TX_BUF_START); 892 enc_w16(enc, CTL_REG_ETXSTL, ENC_TX_BUF_START); 893 /* write packet to ENC */ 894 enc_wbuf(enc, length, (u8 *) packet, 0x00); 895 /* 896 * Check that the internal transmit logic has not been altered 897 * by excessive collisions. Reset transmitter if so. 898 * See Errata B4 12 and 14. 899 */ 900 if (enc_r8(enc, CTL_REG_EIR) & ENC_EIR_TXERIF) { 901 enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_TXRST); 902 enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_TXRST); 903 } 904 enc_bclr(enc, CTL_REG_EIR, (ENC_EIR_TXERIF | ENC_EIR_TXIF)); 905 /* start transmitting */ 906 enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_TXRTS); 907 enc_release_bus(enc); 908 return 0; 909 } 910 911 /* 912 * Finish use of ENC. 913 * 914 * This function entered into eth_device structure. 915 */ 916 static void enc_halt(struct eth_device *dev) 917 { 918 enc_dev_t *enc = dev->priv; 919 920 if (enc_claim_bus(enc)) 921 return; 922 /* Just disable receiver */ 923 enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_RXEN); 924 enc_release_bus(enc); 925 } 926 927 /* 928 * This is the only exported function. 929 * 930 * It may be called several times with different bus:cs combinations. 931 */ 932 int enc28j60_initialize(unsigned int bus, unsigned int cs, 933 unsigned int max_hz, unsigned int mode) 934 { 935 struct eth_device *dev; 936 enc_dev_t *enc; 937 938 /* try to allocate, check and clear eth_device object */ 939 dev = malloc(sizeof(*dev)); 940 if (!dev) { 941 return -1; 942 } 943 memset(dev, 0, sizeof(*dev)); 944 945 /* try to allocate, check and clear enc_dev_t object */ 946 enc = malloc(sizeof(*enc)); 947 if (!enc) { 948 free(dev); 949 return -1; 950 } 951 memset(enc, 0, sizeof(*enc)); 952 953 /* try to setup the SPI slave */ 954 enc->slave = spi_setup_slave(bus, cs, max_hz, mode); 955 if (!enc->slave) { 956 printf("enc28j60: invalid SPI device %i:%i\n", bus, cs); 957 free(enc); 958 free(dev); 959 return -1; 960 } 961 962 enc->dev = dev; 963 /* now fill the eth_device object */ 964 dev->priv = enc; 965 dev->init = enc_init; 966 dev->halt = enc_halt; 967 dev->send = enc_send; 968 dev->recv = enc_recv; 969 dev->write_hwaddr = enc_write_hwaddr; 970 sprintf(dev->name, "enc%i.%i", bus, cs); 971 eth_register(dev); 972 #if defined(CONFIG_CMD_MII) 973 miiphy_register(dev->name, enc_miiphy_read, enc_miiphy_write); 974 #endif 975 return 0; 976 } 977